diff --git a/Makefile b/Makefile
index 954a865..4dc179b 100644
--- a/Makefile
+++ b/Makefile
@@ -1452,6 +1452,7 @@
 		-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
 		-o -name '*.symtypes' -o -name 'modules.order' \
 		-o -name modules.builtin -o -name '.tmp_*.o.*' \
+		-o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \
 		-o -name '*.gcno' \) -type f -print | xargs rm -f
 
 # mrproper - Delete all generated files, including .config
diff --git a/README b/README
index 88ff837..6f4c09a 100644
--- a/README
+++ b/README
@@ -1003,6 +1003,7 @@
 		CONFIG_CMD_ECHO		  echo arguments
 		CONFIG_CMD_EDITENV	  edit env variable
 		CONFIG_CMD_EEPROM	* EEPROM read/write support
+		CONFIG_CMD_EEPROM_LAYOUT* EEPROM layout aware commands
 		CONFIG_CMD_ELF		* bootelf, bootvx
 		CONFIG_CMD_ENV_CALLBACK	* display details about env callbacks
 		CONFIG_CMD_ENV_FLAGS	* display details about env flags
@@ -1066,7 +1067,7 @@
 		CONFIG_CMD_RUN		  run command in env variable
 		CONFIG_CMD_SANDBOX	* sb command to access sandbox features
 		CONFIG_CMD_SAVES	* save S record dump
-		CONFIG_CMD_SCSI		* SCSI Support
+		CONFIG_SCSI		* SCSI Support
 		CONFIG_CMD_SDRAM	* print SDRAM configuration information
 					  (requires CONFIG_CMD_I2C)
 		CONFIG_CMD_SETGETDCR	  Support for DCR Register access
@@ -1254,7 +1255,7 @@
 		CONFIG_MTD_PARTITIONS  Memory Technology Device partition table.
 
 		If IDE or SCSI support is enabled (CONFIG_CMD_IDE or
-		CONFIG_CMD_SCSI) you must configure support for at
+		CONFIG_SCSI) you must configure support for at
 		least one non-MTD partition type as well.
 
 - IDE Reset method:
@@ -3487,6 +3488,10 @@
 		consider that a completely unreadable NAND block is bad,
 		and thus should be skipped silently.
 
+		CONFIG_SPL_ABORT_ON_RAW_IMAGE
+		When defined, SPL will proceed to another boot method
+		if the image it has loaded does not have a signature.
+
 		CONFIG_SPL_RELOC_STACK
 		Adress of the start of the stack SPL will use after
 		relocation.  If unspecified, this is equal to
diff --git a/api/api.c b/api/api.c
index 457dc36..8a1433a 100644
--- a/api/api.c
+++ b/api/api.c
@@ -52,7 +52,7 @@
 {
 	int *c;
 
-	if ((c = (int *)va_arg(ap, u_int32_t)) == NULL)
+	if ((c = (int *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
 	*c = getc();
@@ -68,7 +68,7 @@
 {
 	int *t;
 
-	if ((t = (int *)va_arg(ap, u_int32_t)) == NULL)
+	if ((t = (int *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
 	*t = tstc();
@@ -84,7 +84,7 @@
 {
 	char *c;
 
-	if ((c = (char *)va_arg(ap, u_int32_t)) == NULL)
+	if ((c = (char *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
 	putc(*c);
@@ -100,7 +100,7 @@
 {
 	char *s;
 
-	if ((s = (char *)va_arg(ap, u_int32_t)) == NULL)
+	if ((s = (char *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
 	puts(s);
@@ -132,7 +132,7 @@
 {
 	struct sys_info *si;
 
-	si = (struct sys_info *)va_arg(ap, u_int32_t);
+	si = (struct sys_info *)va_arg(ap, uintptr_t);
 	if (si == NULL)
 		return API_ENOMEM;
 
@@ -148,7 +148,7 @@
 {
 	unsigned long *d;
 
-	if ((d = (unsigned long *)va_arg(ap, u_int32_t)) == NULL)
+	if ((d = (unsigned long *)va_arg(ap, unsigned long)) == NULL)
 		return API_EINVAL;
 
 	udelay(*d);
@@ -164,11 +164,11 @@
 {
 	unsigned long *base, *cur;
 
-	cur = (unsigned long *)va_arg(ap, u_int32_t);
+	cur = (unsigned long *)va_arg(ap, unsigned long);
 	if (cur == NULL)
 		return API_EINVAL;
 
-	base = (unsigned long *)va_arg(ap, u_int32_t);
+	base = (unsigned long *)va_arg(ap, unsigned long);
 	if (base == NULL)
 		return API_EINVAL;
 
@@ -199,7 +199,7 @@
 	struct device_info *di;
 
 	/* arg is ptr to the device_info struct we are going to fill out */
-	di = (struct device_info *)va_arg(ap, u_int32_t);
+	di = (struct device_info *)va_arg(ap, uintptr_t);
 	if (di == NULL)
 		return API_EINVAL;
 
@@ -233,7 +233,7 @@
 	int err = 0;
 
 	/* arg is ptr to the device_info struct */
-	di = (struct device_info *)va_arg(ap, u_int32_t);
+	di = (struct device_info *)va_arg(ap, uintptr_t);
 	if (di == NULL)
 		return API_EINVAL;
 
@@ -265,7 +265,7 @@
 	int err = 0;
 
 	/* arg is ptr to the device_info struct */
-	di = (struct device_info *)va_arg(ap, u_int32_t);
+	di = (struct device_info *)va_arg(ap, uintptr_t);
 	if (di == NULL)
 		return API_EINVAL;
 
@@ -319,7 +319,7 @@
 	int err = 0;
 
 	/* 1. arg is ptr to the device_info struct */
-	di = (struct device_info *)va_arg(ap, u_int32_t);
+	di = (struct device_info *)va_arg(ap, uintptr_t);
 	if (di == NULL)
 		return API_EINVAL;
 
@@ -329,12 +329,12 @@
 		return API_ENODEV;
 
 	/* 2. arg is ptr to buffer from where to get data to write */
-	buf = (void *)va_arg(ap, u_int32_t);
+	buf = (void *)va_arg(ap, uintptr_t);
 	if (buf == NULL)
 		return API_EINVAL;
 
 	/* 3. arg is length of buffer */
-	len = (int *)va_arg(ap, u_int32_t);
+	len = (int *)va_arg(ap, uintptr_t);
 	if (len == NULL)
 		return API_EINVAL;
 	if (*len <= 0)
@@ -387,7 +387,7 @@
 	int *len_net, *act_len_net;
 
 	/* 1. arg is ptr to the device_info struct */
-	di = (struct device_info *)va_arg(ap, u_int32_t);
+	di = (struct device_info *)va_arg(ap, uintptr_t);
 	if (di == NULL)
 		return API_EINVAL;
 
@@ -397,23 +397,23 @@
 		return API_ENODEV;
 
 	/* 2. arg is ptr to buffer from where to put the read data */
-	buf = (void *)va_arg(ap, u_int32_t);
+	buf = (void *)va_arg(ap, uintptr_t);
 	if (buf == NULL)
 		return API_EINVAL;
 
 	if (di->type & DEV_TYP_STOR) {
 		/* 3. arg - ptr to var with # of blocks to read */
-		len_stor = (lbasize_t *)va_arg(ap, u_int32_t);
+		len_stor = (lbasize_t *)va_arg(ap, uintptr_t);
 		if (!len_stor)
 			return API_EINVAL;
 		if (*len_stor <= 0)
 			return API_EINVAL;
 
 		/* 4. arg - ptr to var with start block */
-		start = (lbastart_t *)va_arg(ap, u_int32_t);
+		start = (lbastart_t *)va_arg(ap, uintptr_t);
 
 		/* 5. arg - ptr to var where to put the len actually read */
-		act_len_stor = (lbasize_t *)va_arg(ap, u_int32_t);
+		act_len_stor = (lbasize_t *)va_arg(ap, uintptr_t);
 		if (!act_len_stor)
 			return API_EINVAL;
 
@@ -422,14 +422,14 @@
 	} else if (di->type & DEV_TYP_NET) {
 
 		/* 3. arg points to the var with length of packet to read */
-		len_net = (int *)va_arg(ap, u_int32_t);
+		len_net = (int *)va_arg(ap, uintptr_t);
 		if (!len_net)
 			return API_EINVAL;
 		if (*len_net <= 0)
 			return API_EINVAL;
 
 		/* 4. - ptr to var where to put the len actually read */
-		act_len_net = (int *)va_arg(ap, u_int32_t);
+		act_len_net = (int *)va_arg(ap, uintptr_t);
 		if (!act_len_net)
 			return API_EINVAL;
 
@@ -453,9 +453,9 @@
 {
 	char *name, **value;
 
-	if ((name = (char *)va_arg(ap, u_int32_t)) == NULL)
+	if ((name = (char *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
-	if ((value = (char **)va_arg(ap, u_int32_t)) == NULL)
+	if ((value = (char **)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
 	*value = getenv(name);
@@ -476,9 +476,9 @@
 {
 	char *name, *value;
 
-	if ((name = (char *)va_arg(ap, u_int32_t)) == NULL)
+	if ((name = (char *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
-	if ((value = (char *)va_arg(ap, u_int32_t)) == NULL)
+	if ((value = (char *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
 	setenv(name, value);
@@ -498,9 +498,9 @@
 	int i, n;
 	char *last, **next;
 
-	last = (char *)va_arg(ap, u_int32_t);
+	last = (char *)va_arg(ap, unsigned long);
 
-	if ((next = (char **)va_arg(ap, u_int32_t)) == NULL)
+	if ((next = (char **)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
 	if (last == NULL)
@@ -662,14 +662,14 @@
 	}
 
 	setenv_hex("api_address", (unsigned long)sig);
-	debugf("API sig @ 0x%08x\n", sig);
+	debugf("API sig @ 0x%lX\n", (unsigned long)sig);
 	memcpy(sig->magic, API_SIG_MAGIC, 8);
 	sig->version = API_SIG_VERSION;
 	sig->syscall = &syscall;
 	sig->checksum = 0;
 	sig->checksum = crc32(0, (unsigned char *)sig,
 			      sizeof(struct api_signature));
-	debugf("syscall entry: 0x%08x\n", sig->syscall);
+	debugf("syscall entry: 0x%lX\n", (unsigned long)sig->syscall);
 }
 
 void platform_set_mr(struct sys_info *si, unsigned long start, unsigned long size,
diff --git a/api/api_storage.c b/api/api_storage.c
index 8c30c56..d425a9a 100644
--- a/api/api_storage.c
+++ b/api/api_storage.c
@@ -67,7 +67,7 @@
 	specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
 	specs[ENUM_SATA].name = "sata";
 #endif
-#if defined(CONFIG_CMD_SCSI)
+#if defined(CONFIG_SCSI)
 	specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
 	specs[ENUM_SCSI].enum_started = 0;
 	specs[ENUM_SCSI].enum_ended = 0;
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6b65d8e..729b181 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -594,6 +594,7 @@
 	select DM
 	select OF_CONTROL
 	select DM_SERIAL
+	select SUPPORT_SPL
 
 config TEGRA
 	bool "NVIDIA Tegra"
diff --git a/arch/arm/cpu/armv7/mx7/clock_slice.c b/arch/arm/cpu/armv7/mx7/clock_slice.c
index ad5d504..1665df9 100644
--- a/arch/arm/cpu/armv7/mx7/clock_slice.c
+++ b/arch/arm/cpu/armv7/mx7/clock_slice.c
@@ -55,7 +55,7 @@
 	  PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
 	},
 	{AHB_CLK_ROOT, CCM_AHB_CHANNEL,
-	 {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK,
+	 {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
 	  PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
 	  PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
 	},
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index c3cc819..e933021 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -216,7 +216,7 @@
 #endif
 #endif
 
-#ifndef CONFIG_ARMV8_MULTIENTRY
+#ifdef CONFIG_ARMV8_MULTIENTRY
 	branch_if_master x0, x1, 2f
 
 	/*
diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile
index d0ed222..be8673a 100644
--- a/arch/arm/cpu/armv8/zynqmp/Makefile
+++ b/arch/arm/cpu/armv8/zynqmp/Makefile
@@ -9,3 +9,4 @@
 obj-y	+= cpu.o
 obj-$(CONFIG_MP)	+= mp.o
 obj-y	+= slcr.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c
new file mode 100644
index 0000000..e3e2a4f
--- /dev/null
+++ b/arch/arm/cpu/armv8/zynqmp/spl.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2015 - 2016 Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <asm/spl.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+void board_init_f(ulong dummy)
+{
+	psu_init();
+	board_early_init_r();
+
+#ifdef CONFIG_DEBUG_UART
+	/* Uart debug for sure */
+	debug_uart_init();
+	puts("Debug uart enabled\n"); /* or printch() */
+#endif
+	/* Delay is required for clocks to be propagated */
+	udelay(1000000);
+
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* No need to call timer init - it is empty for ZynqMP */
+	board_init_r(NULL, 0);
+}
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+	preloader_console_init();
+	board_init();
+}
+#endif
+
+u32 spl_boot_device(void)
+{
+	u32 reg = 0;
+	u8 bootmode;
+
+	reg = readl(&crlapb_base->boot_mode);
+	bootmode = reg & BOOT_MODES_MASK;
+
+	switch (bootmode) {
+	case JTAG_MODE:
+		return BOOT_DEVICE_RAM;
+#ifdef CONFIG_SPL_MMC_SUPPORT
+	case EMMC_MODE:
+	case SD_MODE:
+	case SD_MODE1:
+		return BOOT_DEVICE_MMC1;
+#endif
+	default:
+		printf("Invalid Boot Mode:0x%x\n", bootmode);
+		break;
+	}
+
+	return 0;
+}
+
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_RAM:
+		return 0;
+	case BOOT_DEVICE_MMC1:
+		return MMCSD_MODE_FS;
+	default:
+		puts("spl: error: unsupported device\n");
+		hang();
+	}
+}
+
+__weak void psu_init(void)
+{
+	 /*
+	  * This function is overridden by the one in
+	  * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
+	  */
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
index c95d1d3..3ffa8e0 100644
--- a/arch/arm/dts/am4372.dtsi
+++ b/arch/arm/dts/am4372.dtsi
@@ -547,6 +547,7 @@
 			active_slave = <0>;
 			cpts_clock_mult = <0x80000000>;
 			cpts_clock_shift = <29>;
+			syscon = <&scm_conf>;
 			ranges;
 
 			davinci_mdio: mdio@4a101000 {
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index e7fecf7..0f242e6 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -1411,7 +1411,7 @@
 			ti,irqs-safe-map = <0>;
 		};
 
-		mac: ethernet@4a100000 {
+		mac: ethernet@48484000 {
 			compatible = "ti,cpsw";
 			ti,hwmods = "gmac";
 			clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
@@ -1426,6 +1426,7 @@
 			active_slave = <0>;
 			cpts_clock_mult = <0x80000000>;
 			cpts_clock_shift = <29>;
+			syscon = <&scm_conf>;
 			reg = <0x48484000 0x1000
 			       0x48485200 0x2E00>;
 			#address-cells = <1>;
diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts
index 16948c9..ad3527e 100644
--- a/arch/arm/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/dts/exynos4210-universal_c210.dts
@@ -42,11 +42,11 @@
 	};
 
 	soft-spi {
-		compatible = "u-boot,soft-spi";
-		cs-gpio = <&gpy4 3 0>;
-		sclk-gpio = <&gpy3 1 0>;
-		mosi-gpio = <&gpy3 3 0>;
-		miso-gpio = <&gpy3 0 0>;
+		compatible = "spi-gpio";
+		cs-gpios = <&gpy4 3 0>;
+		gpio-sck = <&gpy3 1 0>;
+		gpio-mosi = <&gpy3 3 0>;
+		gpio-miso = <&gpy3 0 0>;
 		spi-delay-us = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts
index eada590..5893d2a 100644
--- a/arch/arm/dts/tegra20-seaboard.dts
+++ b/arch/arm/dts/tegra20-seaboard.dts
@@ -40,10 +40,6 @@
 				nvidia,panel = <&lcd_panel>;
 			};
 		};
-
-		dc@54240000 {
-			status = "disabled";
-		};
 	};
 
 	/* This is not used in U-Boot, but is expected to be in kernel .dts */
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index a327557..b618a3f 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -251,7 +251,7 @@
 		slcr: slcr@f8000000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
-			compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
 			reg = <0xF8000000 0x1000>;
 			ranges;
 			clkc: clkc@100 {
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index fb95b48..619450e 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -253,9 +253,9 @@
 			compatible = "arm,gic-400", "arm,cortex-a15-gic";
 			#interrupt-cells = <3>;
 			reg = <0x0 0xf9010000 0x10000>,
-			      <0x0 0xf902f000 0x2000>,
+			      <0x0 0xf9020000 0x20000>,
 			      <0x0 0xf9040000 0x20000>,
-			      <0x0 0xf906f000 0x2000>;
+			      <0x0 0xf9060000 0x20000>;
 			interrupt-controller;
 			interrupt-parent = <&gic>;
 			interrupts = <1 9 0xf04>;
@@ -264,6 +264,7 @@
 
 	amba: amba {
 		compatible = "simple-bus";
+		u-boot,dm-pre-reloc;
 		#address-cells = <2>;
 		#size-cells = <1>;
 		ranges = <0 0 0 0 0xffffffff>;
@@ -674,6 +675,7 @@
 		};
 
 		sdhci0: sdhci@ff160000 {
+			u-boot,dm-pre-reloc;
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";
 			interrupt-parent = <&gic>;
@@ -685,6 +687,7 @@
 		};
 
 		sdhci1: sdhci@ff170000 {
+			u-boot,dm-pre-reloc;
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";
 			interrupt-parent = <&gic>;
@@ -776,6 +779,7 @@
 		};
 
 		uart0: serial@ff000000 {
+			u-boot,dm-pre-reloc;
 			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 			status = "disabled";
 			interrupt-parent = <&gic>;
@@ -786,6 +790,7 @@
 		};
 
 		uart1: serial@ff010000 {
+			u-boot,dm-pre-reloc;
 			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 			status = "disabled";
 			interrupt-parent = <&gic>;
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 5fb3ed8..4223187 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -138,7 +138,7 @@
 {
 	switch (imxtype) {
 	case MXC_CPU_MX7S:
-		return "7SOLO";	/* Single-core version of the mx7 */
+		return "7S";	/* Single-core version of the mx7 */
 	case MXC_CPU_MX7D:
 		return "7D";	/* Dual-core version of the mx7 */
 	case MXC_CPU_MX6QP:
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 139a623..04abec4 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -83,7 +83,7 @@
 /* SATA */
 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
 #define CONFIG_BOARD_LATE_INIT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 6ba1034..919d83d 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -22,6 +22,7 @@
 	MX6_PAD_SD1_DAT3__USDHC1_DAT3				= IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0),
 	MX6_PAD_SD1_DAT4__USDHC1_DAT4				= IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0),
 	MX6_PAD_SD1_DAT5__USDHC1_DAT5				= IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT5__GPIO_5_9				= IOMUX_PAD(0x0550, 0x0248, 5, 0x0000, 0, 0),
 	MX6_PAD_SD1_DAT6__USDHC1_DAT6				= IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0),
 	MX6_PAD_SD1_DAT7__USDHC1_DAT7				= IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0),
 	MX6_PAD_KEY_ROW7__GPIO_4_7					= IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx7/mx7d_pins.h b/arch/arm/include/asm/arch-mx7/mx7d_pins.h
index d8b4097..0ab1246 100644
--- a/arch/arm/include/asm/arch-mx7/mx7d_pins.h
+++ b/arch/arm/include/asm/arch-mx7/mx7d_pins.h
@@ -635,7 +635,7 @@
 	MX7D_PAD_LCD_DATA23__GPIO3_IO28                          = IOMUX_PAD(0x0394, 0x0124, 5, 0x0000, 0, 0),
 	MX7D_PAD_LCD_DATA23__I2C4_SDA                            = IOMUX_PAD(0x0394, 0x0124, IOMUX_CONFIG_SION | 6, 0x05F0, 1, 0),
 
-	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX                     = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX                     = IOMUX_PAD(0x0398, 0x0128, 0, 0x06F4, 0, 0),
 
 	MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX                     = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0),
 	MX7D_PAD_UART1_RX_DATA__I2C1_SCL                         = IOMUX_PAD(0x0398, 0x0128, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
@@ -655,7 +655,7 @@
 	MX7D_PAD_UART1_TX_DATA__GPIO4_IO1                        = IOMUX_PAD(0x039C, 0x012C, 5, 0x0000, 0, 0),
 	MX7D_PAD_UART1_TX_DATA__ENET1_MDC                        = IOMUX_PAD(0x039C, 0x012C, 6, 0x0000, 0, 0),
 
-	MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX                     = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0),
+	MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX                     = IOMUX_PAD(0x03A0, 0x0130, 0, 0x06FC, 2, 0),
 
 	MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX                     = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0),
 	MX7D_PAD_UART2_RX_DATA__I2C2_SCL                         = IOMUX_PAD(0x03A0, 0x0130, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
@@ -667,7 +667,7 @@
 
 	MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX                     = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0),
 
-	MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX                     = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0),
+	MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX                     = IOMUX_PAD(0x03A4, 0x0134, 0, 0x06FC, 3, 0),
 	MX7D_PAD_UART2_TX_DATA__I2C2_SDA                         = IOMUX_PAD(0x03A4, 0x0134, IOMUX_CONFIG_SION | 1, 0x05E0, 0, 0),
 	MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0                    = IOMUX_PAD(0x03A4, 0x0134, 2, 0x06C8, 0, 0),
 	MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY                       = IOMUX_PAD(0x03A4, 0x0134, 3, 0x0000, 0, 0),
@@ -695,7 +695,7 @@
 	MX7D_PAD_UART3_TX_DATA__GPIO4_IO5                        = IOMUX_PAD(0x03AC, 0x013C, 5, 0x0000, 0, 0),
 	MX7D_PAD_UART3_TX_DATA__SD2_LCTL                         = IOMUX_PAD(0x03AC, 0x013C, 6, 0x0000, 0, 0),
 
-	MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS                      = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0),
+	MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS                      = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0700, 2, 0),
 
 	MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS                      = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0),
 	MX7D_PAD_UART3_RTS_B__USB_OTG2_OC                        = IOMUX_PAD(0x03B0, 0x0140, 1, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index b1513e9..683d905 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -116,4 +116,16 @@
 #define CPSW_BASE			0x48484000
 #define CPSW_MDIO_BASE			0x48485000
 
+/* gmii_sel register defines */
+#define GMII1_SEL_MII		0x0
+#define GMII1_SEL_RMII		0x1
+#define GMII1_SEL_RGMII		0x2
+#define GMII2_SEL_MII		(GMII1_SEL_MII << 4)
+#define GMII2_SEL_RMII		(GMII1_SEL_RMII << 4)
+#define GMII2_SEL_RGMII		(GMII1_SEL_RGMII << 4)
+
+#define MII_MODE_ENABLE		(GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE	(GMII1_SEL_RGMII | GMII2_SEL_RGMII)
+
 #endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index 021626d..1db2bd6 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -17,4 +17,6 @@
 
 unsigned int zynqmp_get_silicon_version(void);
 
+void psu_init(void);
+
 #endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 9ce775e..73a9c74 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -71,6 +71,11 @@
 	select CPU_ARM926EJS
 	select SUPPORT_SPL
 
+config TARGET_SAMA5D2_PTC
+	bool "SAMA5D2 PTC board"
+	select CPU_V7
+	select SUPPORT_SPL
+
 config TARGET_SAMA5D2_XPLAINED
 	bool "SAMA5D2 Xplained board"
 	select CPU_V7
@@ -138,6 +143,7 @@
 source "board/atmel/at91sam9n12ek/Kconfig"
 source "board/atmel/at91sam9rlek/Kconfig"
 source "board/atmel/at91sam9x5ek/Kconfig"
+source "board/atmel/sama5d2_ptc/Kconfig"
 source "board/atmel/sama5d2_xplained/Kconfig"
 source "board/atmel/sama5d3_xplained/Kconfig"
 source "board/atmel/sama5d3xek/Kconfig"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 4424523..d2abf31 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -9,7 +9,7 @@
 obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
-obj-$(CONFIG_SAMA5D2) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
+obj-$(CONFIG_SAMA5D2) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
 obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
 obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
 obj-y += spl.o
diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c
index 81e9f69..76fcada 100644
--- a/arch/arm/mach-at91/armv7/clock.c
+++ b/arch/arm/mach-at91/armv7/clock.c
@@ -162,6 +162,11 @@
 	if (div > 0xff)
 		return -EINVAL;
 
+	if (clk_source == GCK_CSS_UPLL_CLK) {
+		if (at91_upll_clk_enable())
+			return -ENODEV;
+	}
+
 	writel(id, &pmc->pcr);
 	regval = readl(&pmc->pcr);
 	regval &= ~AT91_PMC_PCR_GCKCSS;
@@ -231,6 +236,12 @@
 	case AT91_PMC_PCR_GCKCSS_PLLA_CLK:
 		freq = gd->arch.plla_rate_hz;
 		break;
+	case AT91_PMC_PCR_GCKCSS_UPLL_CLK:
+		freq = AT91_UTMI_PLL_CLK_FREQ;
+		break;
+	case AT91_PMC_PCR_GCKCSS_MCK_CLK:
+		freq = gd->arch.mck_rate_hz;
+		break;
 	default:
 		printf("Improper GCK clock source selection!\n");
 		freq = 0;
diff --git a/arch/arm/mach-at91/bootparams_atmel.S b/arch/arm/mach-at91/bootparams_atmel.S
new file mode 100644
index 0000000..568094b
--- /dev/null
+++ b/arch/arm/mach-at91/bootparams_atmel.S
@@ -0,0 +1,18 @@
+/*
+ * Atmel SAMA5Dx boot parameter handling
+ *
+ * Copyright (c) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+	ldr	r0, =bootrom_stash
+	str	r4, [r0, #0]
+	b	save_boot_params_ret
+ENDPROC(save_boot_params)
diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h
index 8577c74..ca7d7d0 100644
--- a/arch/arm/mach-at91/include/mach/clk.h
+++ b/arch/arm/mach-at91/include/mach/clk.h
@@ -20,6 +20,8 @@
 #define GCK_CSS_MCK_CLK		4
 #define GCK_CSS_AUDIO_CLK	5
 
+#define AT91_UTMI_PLL_CLK_FREQ	480000000
+
 static inline unsigned long get_cpu_clk_rate(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h
index b040256..b805a2c 100644
--- a/arch/arm/mach-at91/include/mach/sama5_sfr.h
+++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h
@@ -32,6 +32,30 @@
 #define ATMEL_SFR_DDRCFG_FDQIEN		0x00010000
 #define ATMEL_SFR_DDRCFG_FDQSIEN	0x00020000
 
+/* Bit field in EBICFG */
+#define AT91_SFR_EBICFG_DRIVE0		(0x3 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_LOW		(0x0 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_MEDIUM		(0x2 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_HIGH		(0x3 << 0)
+#define AT91_SFR_EBICFG_PULL0		(0x3 << 2)
+#define AT91_SFR_EBICFG_PULL0_UP		(0x0 << 2)
+#define AT91_SFR_EBICFG_PULL0_NONE		(0x1 << 2)
+#define AT91_SFR_EBICFG_PULL0_DOWN		(0x3 << 2)
+#define AT91_SFR_EBICFG_SCH0		(0x1 << 4)
+#define AT91_SFR_EBICFG_SCH0_OFF		(0x0 << 4)
+#define AT91_SFR_EBICFG_SCH0_ON			(0x1 << 4)
+#define AT91_SFR_EBICFG_DRIVE1		(0x3 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_LOW		(0x0 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_MEDIUM		(0x2 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_HIGH		(0x3 << 8)
+#define AT91_SFR_EBICFG_PULL1		(0x3 << 10)
+#define AT91_SFR_EBICFG_PULL1_UP		(0x0 << 10)
+#define AT91_SFR_EBICFG_PULL1_NONE		(0x1 << 10)
+#define AT91_SFR_EBICFG_PULL1_DOWN		(0x3 << 10)
+#define AT91_SFR_EBICFG_SCH1		(0x1 << 12)
+#define AT91_SFR_EBICFG_SCH1_OFF		(0x0 << 12)
+#define AT91_SFR_EBICFG_SCH1_ON			(0x1 << 12)
+
 /* Bit field in AICREDIR */
 #define ATMEL_SFR_AICREDIR_NSAIC	0x00000001
 
diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
index dd5a2a7..ee841da 100644
--- a/arch/arm/mach-at91/include/mach/sama5d2.h
+++ b/arch/arm/mach-at91/include/mach/sama5d2.h
@@ -135,7 +135,11 @@
 /*
  * Address Memory Space
  */
+#define ATMEL_BASE_CS0			0x10000000
 #define ATMEL_BASE_DDRCS		0x20000000
+#define ATMEL_BASE_CS1			0x60000000
+#define ATMEL_BASE_CS2			0x70000000
+#define ATMEL_BASE_CS3			0x80000000
 #define ATMEL_BASE_QSPI0_AES_MEM	0x90000000
 #define ATMEL_BASE_QSPI1_AES_MEM	0x98000000
 #define ATMEL_BASE_SDMMC0		0xa0000000
@@ -165,6 +169,7 @@
  */
 #define ATMEL_BASE_PMECC	(ATMEL_BASE_HSMC + 0x70)
 #define ATMEL_BASE_PMERRLOC	(ATMEL_BASE_HSMC + 0x500)
+#define ATMEL_BASE_SMC		(ATMEL_BASE_HSMC + 0x700)
 
 #define ATMEL_BASE_PIOB		(ATMEL_BASE_PIOA + 0x40)
 #define ATMEL_BASE_PIOC		(ATMEL_BASE_PIOB + 0x40)
@@ -225,6 +230,18 @@
 /* No PMECC Galois table in ROM */
 #define NO_GALOIS_TABLE_IN_ROM
 
+/* Boot modes stored by BootROM in r4 */
+#define ATMEL_SAMA5D2_BOOT_FROM_OFF	0
+#define ATMEL_SAMA5D2_BOOT_FROM_MASK	0xf
+#define ATMEL_SAMA5D2_BOOT_FROM_SPI	(0 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_MCI	(1 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_SMC	(2 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_TWI	(3 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_QSPI	(4 << 0)
+
+#define ATMEL_SAMA5D2_BOOT_DEV_ID_OFF	4
+#define ATMEL_SAMA5D2_BOOT_DEV_ID_MASK	0xf
+
 #ifndef __ASSEMBLY__
 unsigned int get_chip_id(void);
 unsigned int get_extension_chip_id(void);
diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c
index 27a405a..c4ed224 100644
--- a/arch/arm/mach-at91/spl.c
+++ b/arch/arm/mach-at91/spl.c
@@ -23,6 +23,40 @@
 }
 #endif
 
+#if defined(CONFIG_SAMA5D2)
+struct {
+	u32	r4;
+} bootrom_stash __attribute__((section(".data")));
+
+u32 spl_boot_device(void)
+{
+	u32 dev = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_FROM_OFF) &
+		  ATMEL_SAMA5D2_BOOT_FROM_MASK;
+	u32 off = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_DEV_ID_OFF) &
+		  ATMEL_SAMA5D2_BOOT_DEV_ID_MASK;
+
+#if defined(CONFIG_SYS_USE_MMC)
+	if (dev == ATMEL_SAMA5D2_BOOT_FROM_MCI) {
+		if (off == 0)
+			return BOOT_DEVICE_MMC1;
+		if (off == 1)
+			return BOOT_DEVICE_MMC2;
+		printf("ERROR: MMC controller %i not present!\n", dev);
+		hang();
+	}
+#endif
+
+#if defined(CONFIG_SYS_USE_SERIALFLASH) || defined(CONFIG_SYS_USE_SPIFLASH)
+	if (dev == ATMEL_SAMA5D2_BOOT_FROM_SPI)
+		return BOOT_DEVICE_SPI;
+#endif
+
+	printf("ERROR: SMC/TWI/QSPI boot device not supported!\n"
+	       "       Boot device %i, controller number %i\n", dev, off);
+
+	return BOOT_DEVICE_NONE;
+}
+#else
 u32 spl_boot_device(void)
 {
 #ifdef CONFIG_SYS_USE_MMC
@@ -34,12 +68,14 @@
 #endif
 	return BOOT_DEVICE_NONE;
 }
+#endif
 
 u32 spl_boot_mode(void)
 {
 	switch (spl_boot_device()) {
 #ifdef CONFIG_SYS_USE_MMC
 	case BOOT_DEVICE_MMC1:
+	case BOOT_DEVICE_MMC2:
 		return MMCSD_MODE_FS;
 		break;
 #endif
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index d396a13..db3c579 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -1,41 +1,5 @@
 if ARCH_ZYNQ
 
-config ZYNQ_CUSTOM_INIT
-	bool "Use custom ps7_init provided by Xilinx tool"
-	help
-	  U-Boot includes ps7_init_gpl.[ch] for some Zynq board variants.
-	  If you want to override them with customized ones
-	  or ps7_init code for your board is missing, please say Y here
-	  and add ones into board/xilinx/zynq/custom_hw_platform/ directory.
-
-choice
-	prompt "Xilinx Zynq board select"
-	default TARGET_ZYNQ_ZC702
-
-config TARGET_ZYNQ_ZED
-	bool "Zynq ZedBoard"
-
-config TARGET_ZYNQ_MICROZED
-	bool "Zynq MicroZed"
-
-config TARGET_ZYNQ_PICOZED
-	bool "Zynq PicoZed"
-
-config TARGET_ZYNQ_ZC702
-	bool "Zynq ZC702 Board"
-
-config TARGET_ZYNQ_ZC706
-	bool "Zynq ZC706 Board"
-
-config TARGET_ZYNQ_ZC770
-	bool "Zynq ZC770 Board"
-	select ZYNQ_CUSTOM_INIT
-
-config TARGET_ZYNQ_ZYBO
-	bool "Zynq Zybo Board"
-
-endchoice
-
 config SYS_BOARD
 	default "zynq"
 
@@ -46,11 +10,11 @@
 	default "zynq"
 
 config SYS_CONFIG_NAME
-	default "zynq_zed" if TARGET_ZYNQ_ZED
-	default "zynq_microzed" if TARGET_ZYNQ_MICROZED
-	default "zynq_picozed" if TARGET_ZYNQ_PICOZED
-	default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706
-	default "zynq_zc770" if TARGET_ZYNQ_ZC770
-	default "zynq_zybo" if TARGET_ZYNQ_ZYBO
+	string "Board configuration name"
+	default "zynq-common"
+	help
+	  This option contains information about board configuration name.
+	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+	  will be used for board configuration.
 
 endif
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index 723019d..6c5415a 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -90,3 +90,28 @@
 	 * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
 	 */
 }
+
+__weak int ps7_post_config(void)
+{
+	/*
+	 * This function is overridden by the one in
+	 * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
+	 */
+	return 0;
+}
+
+void spl_board_prepare_for_boot(void)
+{
+	ps7_post_config();
+	debug("SPL bye\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S
index 23024f9..13c036f 100644
--- a/arch/m68k/cpu/mcf5227x/start.S
+++ b/arch/m68k/cpu/mcf5227x/start.S
@@ -372,14 +372,29 @@
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
 
-	/* set stackpointer to end of internal ram to get some stackspace for
-	   the first c-code */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	/* put relocation table address to a5 */
+	move.l #__got_start, %a5
 
-	move.l #__got_start, %a5	/* put relocation table address to a5 */
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	bsr	board_init_f_alloc_reserve
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l  %d0, -(%sp)
+	bsr     board_init_f_init_reserve
 
 	bsr cpu_init_f			/* run low-level CPU init code (from flash) */
+	clr.l   %sp@-
 	bsr board_init_f		/* run low-level board init code (from flash) */
 
 	/* board_init_f() does not return */
diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S
index 1702f98..3aa4dd6 100644
--- a/arch/m68k/cpu/mcf523x/start.S
+++ b/arch/m68k/cpu/mcf523x/start.S
@@ -134,17 +134,34 @@
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
 
-	/* set stackpointer to end of internal ram to get some stackspace for the
-	   first c-code */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	/* put relocation table address to a5 */
+	move.l #__got_start, %a5
 
-	move.l #__got_start, %a5	/* put relocation table address to a5 */
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr	(%a1)
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l  %d0, -(%sp)
+	move.l	#board_init_f_init_reserve, %a1
+	jsr	(%a1)
 
 	/* run low-level CPU init code (from flash) */
 	move.l #cpu_init_f, %a1
 	jsr (%a1)
 	/* run low-level board init code (from flash) */
+	clr.l   %sp@-
 	move.l #board_init_f, %a1
 	jsr (%a1)
 
diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index 4af691f..a048884 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -192,16 +192,34 @@
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
 
-	/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	/* put relocation table address to a5 */
+	move.l #__got_start, %a5
 
-	move.l #__got_start, %a5		/* put relocation table address to a5 */
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr (%a1)
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l  %d0, -(%sp)
+	move.l	#board_init_f_init_reserve, %a1
+	jsr (%a1)
 
 	/* run low-level CPU init code (from flash) */
 	move.l #cpu_init_f, %a1
 	jsr (%a1)
 	/* run low-level board init code (from flash) */
+	clr.l   %sp@-
 	move.l #board_init_f, %a1
 	jsr (%a1)
 
diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c
index 80dc239..b09eed8 100644
--- a/arch/m68k/cpu/mcf530x/cpu_init.c
+++ b/arch/m68k/cpu/mcf530x/cpu_init.c
@@ -142,7 +142,7 @@
 	return 0;
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
 }
 
diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S
index 097958a..ca8bb32 100644
--- a/arch/m68k/cpu/mcf530x/start.S
+++ b/arch/m68k/cpu/mcf530x/start.S
@@ -126,21 +126,32 @@
 	move.l	%d0, (%a1)
 	move.l	%d0, (%a2)
 
-	/*
-	 * set stackpointer to internal sram end - 80
-	 * (global data struct size + some bytes)
-	 * get some stackspace for the first c-code,
-	 */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l   %sp@-
-
 	/* put relocation table address to a5 */
 	move.l #__got_start, %a5
 
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	bsr	board_init_f_alloc_reserve
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l  %d0, -(%sp)
+	bsr     board_init_f_init_reserve
+
 	/* run low-level CPU init code (from flash) */
 	bsr cpu_init_f
 
 	/* run low-level board init code (from flash) */
+	clr.l   %sp@-
 	bsr board_init_f
 
 	/* board_init_f() does not return */
diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S
index 131ad6e..f25bc54 100644
--- a/arch/m68k/cpu/mcf532x/start.S
+++ b/arch/m68k/cpu/mcf532x/start.S
@@ -148,17 +148,34 @@
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
 
-	/* set stackpointer to end of internal ram to get some stackspace for the
-	   first c-code */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	/* put relocation table address to a5 */
+	move.l #__got_start, %a5
 
-	move.l #__got_start, %a5	/* put relocation table address to a5 */
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr	(%a1)
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l  %d0, -(%sp)
+	move.l	#board_init_f_init_reserve, %a1
+	jsr	(%a1)
 
 	/* run low-level CPU init code (from flash) */
 	move.l #cpu_init_f, %a1
 	jsr (%a1)
 	/* run low-level board init code (from flash) */
+	clr.l   %sp@-
 	move.l #board_init_f, %a1
 	jsr (%a1)
 
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index f50f147..ba38678 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -657,17 +657,34 @@
 	movec	%d0, %RAMBAR1
 #endif
 
-	/* set stackpointer to end of internal ram to get some stackspace for
-	   the first c-code */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	/* put relocation table address to a5 */
+	move.l #__got_start, %a5
 
-	move.l #__got_start, %a5	/* put relocation table address to a5 */
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr	(%a1)
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l  %d0, -(%sp)
+	move.l	#board_init_f_init_reserve, %a1
+	jsr	(%a1)
 
 	/* run low-level CPU init code (from flash) */
 	move.l #cpu_init_f, %a1
 	jsr (%a1)
 	/* run low-level board init code (from flash) */
+	clr.l   %sp@-
 	move.l #board_init_f, %a1
 	jsr (%a1)
 
diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S
index 75de22d..9a87a0d 100644
--- a/arch/m68k/cpu/mcf547x_8x/start.S
+++ b/arch/m68k/cpu/mcf547x_8x/start.S
@@ -141,14 +141,29 @@
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
 
-	/* set stackpointer to end of internal ram to get some stackspace for the
-	   first c-code */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	/* put relocation table address to a5 */
+	move.l #__got_start, %a5
 
-	move.l #__got_start, %a5	/* put relocation table address to a5 */
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	bsr	board_init_f_alloc_reserve
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l  %d0, -(%sp)
+	bsr     board_init_f_init_reserve
 
 	jbsr cpu_init_f			/* run low-level CPU init code (from flash) */
+	clr.l   %sp@-
 	jbsr board_init_f		/* run low-level board init code (from flash) */
 
 	/* board_init_f() does not return */
diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h
index e1458ac..9c4d3fb 100644
--- a/arch/m68k/include/asm/config.h
+++ b/arch/m68k/include/asm/config.h
@@ -7,8 +7,6 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
-
 #define CONFIG_NEEDS_MANUAL_RELOC
 
 #define CONFIG_LMB
diff --git a/arch/m68k/include/asm/fsl_i2c.h b/arch/m68k/include/asm/fsl_i2c.h
index 1b1c25e..c7d2aa3 100644
--- a/arch/m68k/include/asm/fsl_i2c.h
+++ b/arch/m68k/include/asm/fsl_i2c.h
@@ -16,7 +16,7 @@
 
 #include <asm/types.h>
 
-typedef struct fsl_i2c {
+typedef struct fsl_i2c_base {
 
 	u8 adr;		/* I2C slave address */
 	u8 res0[3];
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index fe37d1f..dc34c18 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -5,8 +5,8 @@
 	default "mips"
 
 config SYS_CPU
-	default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
-	default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2
+	default "mips32" if CPU_MIPS32
+	default "mips64" if CPU_MIPS64
 
 choice
 	prompt "Target select"
@@ -28,6 +28,7 @@
 	select SUPPORTS_LITTLE_ENDIAN
 	select SUPPORTS_CPU_MIPS32_R1
 	select SUPPORTS_CPU_MIPS32_R2
+	select SUPPORTS_CPU_MIPS32_R6
 	select SWAP_IO_SPACE
 	select MIPS_L1_CACHE_SHIFT_6
 
@@ -55,6 +56,11 @@
 	select SYS_MIPS_CACHE_INIT_RAM_LOAD
 	select MIPS_TUNE_4KC
 
+config ARCH_ATH79
+	bool "Support QCA/Atheros ath79"
+	select OF_CONTROL
+	select DM
+
 config MACH_PIC32
 	bool "Support Microchip PIC32"
 	select OF_CONTROL
@@ -67,6 +73,7 @@
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-ath79/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS
@@ -98,7 +105,7 @@
 	depends on SUPPORTS_CPU_MIPS32_R1
 	select 32BIT
 	help
-	  Choose this option to build an U-Boot for release 1 or later of the
+	  Choose this option to build an U-Boot for release 1 through 5 of the
 	  MIPS32 architecture.
 
 config CPU_MIPS32_R2
@@ -106,7 +113,15 @@
 	depends on SUPPORTS_CPU_MIPS32_R2
 	select 32BIT
 	help
-	  Choose this option to build an U-Boot for release 2 or later of the
+	  Choose this option to build an U-Boot for release 2 through 5 of the
+	  MIPS32 architecture.
+
+config CPU_MIPS32_R6
+	bool "MIPS32 Release 6"
+	depends on SUPPORTS_CPU_MIPS32_R6
+	select 32BIT
+	help
+	  Choose this option to build an U-Boot for release 6 or later of the
 	  MIPS32 architecture.
 
 config CPU_MIPS64_R1
@@ -114,7 +129,7 @@
 	depends on SUPPORTS_CPU_MIPS64_R1
 	select 64BIT
 	help
-	  Choose this option to build a kernel for release 1 or later of the
+	  Choose this option to build a kernel for release 1 through 5 of the
 	  MIPS64 architecture.
 
 config CPU_MIPS64_R2
@@ -122,7 +137,15 @@
 	depends on SUPPORTS_CPU_MIPS64_R2
 	select 64BIT
 	help
-	  Choose this option to build a kernel for release 2 or later of the
+	  Choose this option to build a kernel for release 2 through 5 of the
+	  MIPS64 architecture.
+
+config CPU_MIPS64_R6
+	bool "MIPS64 Release 6"
+	depends on SUPPORTS_CPU_MIPS64_R6
+	select 64BIT
+	help
+	  Choose this option to build a kernel for release 6 or later of the
 	  MIPS64 architecture.
 
 endchoice
@@ -169,19 +192,25 @@
 config SUPPORTS_CPU_MIPS32_R2
 	bool
 
+config SUPPORTS_CPU_MIPS32_R6
+	bool
+
 config SUPPORTS_CPU_MIPS64_R1
 	bool
 
 config SUPPORTS_CPU_MIPS64_R2
 	bool
 
+config SUPPORTS_CPU_MIPS64_R6
+	bool
+
 config CPU_MIPS32
 	bool
-	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
+	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
 
 config CPU_MIPS64
 	bool
-	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
+	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
 
 config MIPS_TUNE_4KC
 	bool
@@ -192,6 +221,9 @@
 config MIPS_TUNE_24KC
 	bool
 
+config MIPS_TUNE_74KC
+	bool
+
 config 32BIT
 	bool
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index aec5a15..655a493 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -8,6 +8,7 @@
 libs-y += arch/mips/lib/
 
 machine-$(CONFIG_SOC_AU1X00) += au1x00
+machine-$(CONFIG_ARCH_ATH79) += ath79
 machine-$(CONFIG_MACH_PIC32) += pic32
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
@@ -18,13 +19,16 @@
 # Optimize for MIPS architectures
 arch-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32
 arch-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2
+arch-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,-mips32r6
 arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
 arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
+arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
 
 # Allow extra optimization for specific CPUs/SoCs
 tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
 tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
 tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
+tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
 
 # Include default header files
 cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index 8d3b2f5..391feb3 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -7,7 +7,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <netdev.h>
 #include <linux/compiler.h>
 #include <asm/mipsregs.h>
 #include <asm/reboot.h>
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 1b56ca3..fc6dd66 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -164,12 +164,14 @@
 	li	t0, -16
 	PTR_LI	t1, CONFIG_SYS_INIT_SP_ADDR
 	and	sp, t1, t0		# force 16 byte alignment
-	PTR_SUB	sp, sp, GD_SIZE		# reserve space for gd
+	PTR_SUBU \
+		sp, sp, GD_SIZE		# reserve space for gd
 	and	sp, sp, t0		# force 16 byte alignment
 	move	k0, sp			# save gd pointer
 #ifdef CONFIG_SYS_MALLOC_F_LEN
 	li	t2, CONFIG_SYS_MALLOC_F_LEN
-	PTR_SUB	sp, sp, t2		# reserve space for early malloc
+	PTR_SUBU \
+		sp, sp, t2		# reserve space for early malloc
 	and	sp, sp, t0		# force 16 byte alignment
 #endif
 	move	fp, sp
@@ -179,7 +181,7 @@
 1:
 	PTR_S	zero, 0(t0)
 	blt	t0, t1, 1b
-	 PTR_ADDI t0, PTRSIZE
+	 PTR_ADDIU t0, PTRSIZE
 
 #ifdef CONFIG_SYS_MALLOC_F_LEN
 	PTR_S	sp, GD_MALLOC_BASE(k0)	# gd->malloc_base offset
@@ -237,7 +239,7 @@
 	 move	a0, s2			# a0 <-- destination address
 
 	/* Jump to where we've relocated ourselves */
-	PTR_ADDI t0, s2, in_ram - _start
+	PTR_ADDIU t0, s2, in_ram - _start
 	jr	t0
 	 nop
 
@@ -257,7 +259,7 @@
 	PTR_L	t3, -(1 * PTRSIZE)(t0)	# t3 <-- num_got_entries
 	PTR_L	t8, -(2 * PTRSIZE)(t0)	# t8 <-- _GLOBAL_OFFSET_TABLE_
 	PTR_ADD	t8, s1			# t8 now holds relocated _G_O_T_
-	PTR_ADDI t8, t8, 2 * PTRSIZE	# skipping first two entries
+	PTR_ADDIU t8, t8, 2 * PTRSIZE	# skipping first two entries
 	PTR_LI	t2, 2
 1:
 	PTR_L	t1, 0(t8)
@@ -265,16 +267,16 @@
 	 PTR_ADD t1, s1
 	PTR_S	t1, 0(t8)
 2:
-	PTR_ADDI t2, 1
+	PTR_ADDIU t2, 1
 	blt	t2, t3, 1b
-	 PTR_ADDI t8, PTRSIZE
+	 PTR_ADDIU t8, PTRSIZE
 
 	/* Update dynamic relocations */
 	PTR_L	t1, -(4 * PTRSIZE)(t0)	# t1 <-- __rel_dyn_start
 	PTR_L	t2, -(5 * PTRSIZE)(t0)	# t2 <-- __rel_dyn_end
 
 	b	2f			# skip first reserved entry
-	 PTR_ADDI t1, 2 * PTRSIZE
+	 PTR_ADDIU t1, 2 * PTRSIZE
 
 1:
 	lw	t8, -4(t1)		# t8 <-- relocation info
@@ -293,7 +295,7 @@
 
 2:
 	blt	t1, t2, 1b
-	 PTR_ADDI t1, 2 * PTRSIZE	# each rel.dyn entry is 2*PTRSIZE bytes
+	 PTR_ADDIU t1, 2 * PTRSIZE	# each rel.dyn entry is 2*PTRSIZE bytes
 
 	/*
 	 * Clear BSS
@@ -307,7 +309,7 @@
 1:
 	PTR_S	zero, 0(t1)
 	blt	t1, t2, 1b
-	 PTR_ADDI t1, PTRSIZE
+	 PTR_ADDIU t1, PTRSIZE
 
 	move	a0, s0			# a0 <-- gd
 	move	a1, s2
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index b513918..a94b745 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,7 +2,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
+dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
+dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts
new file mode 100644
index 0000000..e31f601
--- /dev/null
+++ b/arch/mips/dts/ap121.dts
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ar933x.dtsi"
+
+/ {
+	model = "AP121 Reference Board";
+	compatible = "qca,ap121", "qca,ar933x";
+
+	aliases {
+		spi0 = &spi0;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&xtal {
+	clock-frequency = <25000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&spi0 {
+	spi-max-frequency = <25000000>;
+	status = "okay";
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		memory-map = <0x9f000000 0x00800000>;
+		spi-max-frequency = <25000000>;
+		reg = <0>;
+	};
+};
diff --git a/arch/mips/dts/ap143.dts b/arch/mips/dts/ap143.dts
new file mode 100644
index 0000000..f53207e
--- /dev/null
+++ b/arch/mips/dts/ap143.dts
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "qca953x.dtsi"
+
+/ {
+	model = "AP143 Reference Board";
+	compatible = "qca,ap143", "qca,qca953x";
+
+	aliases {
+		spi0 = &spi0;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&xtal {
+	clock-frequency = <25000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&spi0 {
+	spi-max-frequency = <25000000>;
+	status = "okay";
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		memory-map = <0x9f000000 0x00800000>;
+		spi-max-frequency = <25000000>;
+		reg = <0>;
+	};
+};
diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi
new file mode 100644
index 0000000..00896b2
--- /dev/null
+++ b/arch/mips/dts/ar933x.dtsi
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "qca,ar933x";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "mips,mips24Kc";
+			reg = <0>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		xtal: xtal {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-output-names = "xtal";
+		};
+	};
+
+	pinctrl {
+		u-boot,dm-pre-reloc;
+		compatible = "qca,ar933x-pinctrl";
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x18040000 0x100>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		apb {
+			compatible = "simple-bus";
+			ranges;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ehci0: ehci@1b000100 {
+				compatible = "generic-ehci";
+				reg = <0x1b000100 0x100>;
+
+				status = "disabled";
+			};
+
+			uart0: uart@18020000 {
+				compatible = "qca,ar9330-uart";
+				reg = <0x18020000 0x20>;
+				interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
+
+				status = "disabled";
+			};
+
+			gmac0: eth@0x19000000 {
+				compatible = "qca,ag7240-mac";
+				reg = <0x19000000 0x200>;
+				phy = <&phy0>;
+				phy-mode = "rmii";
+
+				status = "disabled";
+
+				mdio {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					phy0: ethernet-phy@0 {
+						reg = <0>;
+					};
+				};
+			};
+
+			gmac1: eth@0x1a000000 {
+				compatible = "qca,ag7240-mac";
+				reg = <0x1a000000 0x200>;
+				phy = <&phy0>;
+				phy-mode = "rgmii";
+
+				status = "disabled";
+			};
+		};
+
+		spi0: spi@1f000000 {
+			compatible = "qca,ar7100-spi";
+			reg = <0x1f000000 0x10>;
+			interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
diff --git a/arch/mips/dts/ar934x.dtsi b/arch/mips/dts/ar934x.dtsi
new file mode 100644
index 0000000..7a036a8
--- /dev/null
+++ b/arch/mips/dts/ar934x.dtsi
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "qca,ar934x";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "mips,mips74Kc";
+			reg = <0>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		xtal: xtal {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-output-names = "xtal";
+		};
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		apb {
+			compatible = "simple-bus";
+			ranges;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ehci0: ehci@1b000100 {
+				compatible = "generic-ehci";
+				reg = <0x1b000100 0x100>;
+
+				status = "disabled";
+			};
+
+			uart0: uart@18020000 {
+				compatible = "ns16550";
+				reg = <0x18020000 0x20>;
+				reg-shift = <2>;
+
+				status = "disabled";
+			};
+
+			gmac0: eth@0x19000000 {
+				compatible = "qca,ag934x-mac";
+				reg = <0x19000000 0x200>;
+				phy = <&phy0>;
+				phy-mode = "rgmii";
+
+				status = "disabled";
+
+				mdio {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					phy0: ethernet-phy@0 {
+						reg = <0>;
+					};
+				};
+			};
+
+			gmac1: eth@0x1a000000 {
+				compatible = "qca,ag934x-mac";
+				reg = <0x1a000000 0x200>;
+				phy = <&phy1>;
+				phy-mode = "rgmii";
+
+				status = "disabled";
+
+				mdio {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					phy1: ethernet-phy@0 {
+						reg = <0>;
+					};
+				};
+			};
+		};
+
+		spi0: spi@1f000000 {
+			compatible = "qca,ar7100-spi";
+			reg = <0x1f000000 0x10>;
+
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
diff --git a/arch/mips/dts/qca953x.dtsi b/arch/mips/dts/qca953x.dtsi
new file mode 100644
index 0000000..870010f
--- /dev/null
+++ b/arch/mips/dts/qca953x.dtsi
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "qca,qca953x";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "mips,mips24Kc";
+			reg = <0>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		xtal: xtal {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-output-names = "xtal";
+		};
+	};
+
+	pinctrl {
+		u-boot,dm-pre-reloc;
+		compatible = "qca,qca953x-pinctrl";
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x18040000 0x100>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		apb {
+			compatible = "simple-bus";
+			ranges;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			uart0: uart@18020000 {
+				compatible = "ns16550";
+				reg = <0x18020000 0x20>;
+				reg-shift = <2>;
+				clock-frequency = <25000000>;
+				interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
+
+				status = "disabled";
+			};
+		};
+
+		spi0: spi@1f000000 {
+			compatible = "qca,ar7100-spi";
+			reg = <0x1f000000 0x10>;
+			interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
diff --git a/arch/mips/dts/tplink_wdr4300.dts b/arch/mips/dts/tplink_wdr4300.dts
new file mode 100644
index 0000000..cfda4df
--- /dev/null
+++ b/arch/mips/dts/tplink_wdr4300.dts
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ar934x.dtsi"
+
+/ {
+	model = "TP-Link WDR4300 Board";
+	compatible = "tplink,wdr4300", "qca,ar934x";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &spi0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&gmac0 {
+	phy-mode = "rgmii";
+	status = "okay";
+};
+
+&spi0 {
+	spi-max-frequency = <25000000>;
+	status = "okay";
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		memory-map = <0x1e000000 0x00800000>;
+		spi-max-frequency = <25000000>;
+		reg = <0>;
+	};
+};
+
+&uart0 {
+	clock-frequency = <40000000>;
+	status = "okay";
+};
+
+&xtal {
+	clock-frequency = <40000000>;
+};
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index a1ca257..3f230b0 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -23,6 +23,12 @@
 	unsigned long tbl;
 	unsigned long lastinc;
 #endif
+#ifdef CONFIG_ARCH_ATH79
+	unsigned long id;
+	unsigned long soc;
+	unsigned long rev;
+	unsigned long ver;
+#endif
 };
 
 #include <asm-generic/global_data.h>
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 14cc2c4..08b7c3a 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -64,7 +64,7 @@
 	/* detect associativity */
 	srl	\sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
 	andi	\sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF)
-	addi	\sz, \sz, 1
+	addiu	\sz, \sz, 1
 
 	/* sz *= line_sz */
 	mul	\sz, \sz, \line_sz
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
new file mode 100644
index 0000000..7d483aa
--- /dev/null
+++ b/arch/mips/mach-ath79/Kconfig
@@ -0,0 +1,55 @@
+menu "QCA/Atheros 7xxx/9xxx platforms"
+	depends on ARCH_ATH79
+
+config SYS_SOC
+	default "ath79"
+
+config SOC_AR933X
+	bool
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
+	select MIPS_TUNE_24KC
+	help
+	  This supports QCA/Atheros ar933x family SOCs.
+
+config SOC_AR934X
+	bool
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
+	select MIPS_TUNE_74KC
+	help
+	  This supports QCA/Atheros ar934x family SOCs.
+
+config SOC_QCA953X
+	bool
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
+	select MIPS_TUNE_24KC
+	help
+	  This supports QCA/Atheros qca953x family SOCs.
+
+choice
+	prompt "Board select"
+
+config TARGET_AP121
+	bool "AP121 Reference Board"
+	select SOC_AR933X
+
+config TARGET_AP143
+	bool "AP143 Reference Board"
+	select SOC_QCA953X
+
+config BOARD_TPLINK_WDR4300
+	bool "TP-Link WDR4300 Board"
+	select SOC_AR934X
+
+endchoice
+
+source "board/qca/ap121/Kconfig"
+source "board/qca/ap143/Kconfig"
+source "board/tplink/wdr4300/Kconfig"
+
+endmenu
diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
new file mode 100644
index 0000000..d7e2666
--- /dev/null
+++ b/arch/mips/mach-ath79/Makefile
@@ -0,0 +1,11 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += reset.o
+obj-y += cpu.o
+obj-y += dram.o
+
+obj-$(CONFIG_SOC_AR933X)	+= ar933x/
+obj-$(CONFIG_SOC_AR934X)	+= ar934x/
+obj-$(CONFIG_SOC_QCA953X)	+= qca953x/
diff --git a/arch/mips/mach-ath79/ar933x/Makefile b/arch/mips/mach-ath79/ar933x/Makefile
new file mode 100644
index 0000000..fd74f0c
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += clk.o
+obj-y += ddr.o
+obj-y += lowlevel_init.o
diff --git a/arch/mips/mach-ath79/ar933x/clk.c b/arch/mips/mach-ath79/ar933x/clk.c
new file mode 100644
index 0000000..9fcd496
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/clk.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 ar933x_get_xtal(void)
+{
+	u32 val;
+
+	val = get_bootstrap();
+	if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+		return 40000000;
+	else
+		return 25000000;
+}
+
+int get_serial_clock(void)
+{
+	return ar933x_get_xtal();
+}
+
+int get_clocks(void)
+{
+	void __iomem *regs;
+	u32 val, xtal, pll, div;
+
+	regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+			   MAP_NOCACHE);
+	xtal = ar933x_get_xtal();
+	val = readl(regs + AR933X_PLL_CPU_CONFIG_REG);
+
+	/* VCOOUT = XTAL * DIV_INT */
+	div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT)
+			& AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+	pll = xtal / div;
+
+	/* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+	div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT)
+			& AR933X_PLL_CPU_CONFIG_NINT_MASK;
+	pll *= div;
+	div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
+			& AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+	if (!div)
+		div = 1;
+	pll >>= div;
+
+	val = readl(regs + AR933X_PLL_CLK_CTRL_REG);
+
+	/* CPU_CLK = PLLOUT / CPU_POST_DIV */
+	div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
+			& AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
+	gd->cpu_clk = pll / div;
+
+	/* DDR_CLK = PLLOUT / DDR_POST_DIV */
+	div = ((val >> AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
+			& AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
+	gd->mem_clk = pll / div;
+
+	/* AHB_CLK = PLLOUT / AHB_POST_DIV */
+	div = ((val >> AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
+			& AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
+	gd->bus_clk = pll / div;
+
+	return 0;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+	if (!gd->bus_clk)
+		get_clocks();
+	return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+	if (!gd->mem_clk)
+		get_clocks();
+	return gd->mem_clk;
+}
diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c
new file mode 100644
index 0000000..91452bc
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/ddr.c
@@ -0,0 +1,333 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Based on Atheros LSDK/QSDK
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_CTRL_UPD_EMR3S      BIT(5)
+#define DDR_CTRL_UPD_EMR2S      BIT(4)
+#define DDR_CTRL_PRECHARGE      BIT(3)
+#define DDR_CTRL_AUTO_REFRESH   BIT(2)
+#define DDR_CTRL_UPD_EMRS       BIT(1)
+#define DDR_CTRL_UPD_MRS        BIT(0)
+
+#define DDR_REFRESH_EN          BIT(14)
+#define DDR_REFRESH_M           0x3ff
+#define DDR_REFRESH(x)          ((x) & 0x3ff)
+#define DDR_REFRESH_VAL_25M     (DDR_REFRESH_EN | DDR_REFRESH(390))
+#define DDR_REFRESH_VAL_40M     (DDR_REFRESH_EN | DDR_REFRESH(624))
+
+#define DDR_TRAS_S              0
+#define DDR_TRAS_M              0x1f
+#define DDR_TRAS(x)             ((x) << DDR_TRAS_S)
+#define DDR_TRCD_M              0xf
+#define DDR_TRCD_S              5
+#define DDR_TRCD(x)             ((x) << DDR_TRCD_S)
+#define DDR_TRP_M               0xf
+#define DDR_TRP_S               9
+#define DDR_TRP(x)              ((x) << DDR_TRP_S)
+#define DDR_TRRD_M              0xf
+#define DDR_TRRD_S              13
+#define DDR_TRRD(x)             ((x) << DDR_TRRD_S)
+#define DDR_TRFC_M              0x7f
+#define DDR_TRFC_S              17
+#define DDR_TRFC(x)             ((x) << DDR_TRFC_S)
+#define DDR_TMRD_M              0xf
+#define DDR_TMRD_S              23
+#define DDR_TMRD(x)             ((x) << DDR_TMRD_S)
+#define DDR_CAS_L_M             0x17
+#define DDR_CAS_L_S             27
+#define DDR_CAS_L(x)            (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
+#define DDR_OPEN                BIT(30)
+#define DDR_CONF_REG_VAL        (DDR_TRAS(16) | DDR_TRCD(6) | \
+				 DDR_TRP(6) | DDR_TRRD(4) | \
+				 DDR_TRFC(30) | DDR_TMRD(15) | \
+				 DDR_CAS_L(7) | DDR_OPEN)
+
+#define DDR_BURST_LEN_S         0
+#define DDR_BURST_LEN_M         0xf
+#define DDR_BURST_LEN(x)        ((x) << DDR_BURST_LEN_S)
+#define DDR_BURST_TYPE          BIT(4)
+#define DDR_CNTL_OE_EN          BIT(5)
+#define DDR_PHASE_SEL           BIT(6)
+#define DDR_CKE                 BIT(7)
+#define DDR_TWR_S               8
+#define DDR_TWR_M               0xf
+#define DDR_TWR(x)              ((x) << DDR_TWR_S)
+#define DDR_TRTW_S              12
+#define DDR_TRTW_M              0x1f
+#define DDR_TRTW(x)             ((x) << DDR_TRTW_S)
+#define DDR_TRTP_S              17
+#define DDR_TRTP_M              0xf
+#define DDR_TRTP(x)             ((x) << DDR_TRTP_S)
+#define DDR_TWTR_S              21
+#define DDR_TWTR_M              0x1f
+#define DDR_TWTR(x)             ((x) << DDR_TWTR_S)
+#define DDR_G_OPEN_L_S          26
+#define DDR_G_OPEN_L_M          0xf
+#define DDR_G_OPEN_L(x)         ((x) << DDR_G_OPEN_L_S)
+#define DDR_HALF_WIDTH_LOW      BIT(31)
+#define DDR_CONF2_REG_VAL       (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
+				 DDR_CKE | DDR_TWR(6) | DDR_TRTW(14) | \
+				 DDR_TRTP(8) | DDR_TWTR(14) | \
+				 DDR_G_OPEN_L(7) | DDR_HALF_WIDTH_LOW)
+
+#define DDR2_CONF_TWL_S         10
+#define DDR2_CONF_TWL_M         0xf
+#define DDR2_CONF_TWL(x)        (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
+#define DDR2_CONF_ODT           BIT(9)
+#define DDR2_CONF_TFAW_S        2
+#define DDR2_CONF_TFAW_M        0x3f
+#define DDR2_CONF_TFAW(x)       (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
+#define DDR2_CONF_EN            BIT(0)
+#define DDR2_CONF_VAL           (DDR2_CONF_TWL(2) | DDR2_CONF_ODT | \
+				 DDR2_CONF_TFAW(22) | DDR2_CONF_EN)
+
+#define DDR1_EXT_MODE_VAL       0x02
+#define DDR2_EXT_MODE_VAL       0x402
+#define DDR2_EXT_MODE_OCD_VAL   0x382
+#define DDR1_MODE_DLL_VAL       0x133
+#define DDR2_MODE_DLL_VAL       0x100
+#define DDR1_MODE_VAL           0x33
+#define DDR2_MODE_VAL           0xa33
+#define DDR_TAP_VAL0            0x08
+#define DDR_TAP_VAL1            0x09
+
+void ddr_init(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			   MAP_NOCACHE);
+
+	writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+	writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+
+	val = get_bootstrap();
+	if (val & AR933X_BOOTSTRAP_DDR2) {
+		/* AHB maximum timeout */
+		writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
+
+		/* Enable DDR2 */
+		writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Disable High Temperature Self-Refresh, Full Array */
+		writel(0x00, regs + AR933X_DDR_REG_EMR2);
+
+		/* Extended Mode Register 2 Set (EMR2S) */
+		writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
+
+		writel(0x00, regs + AR933X_DDR_REG_EMR3);
+
+		/* Extended Mode Register 3 Set (EMR3S) */
+		writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Enable DLL,  Full strength, ODT Disabled */
+		writel(0x00, regs + AR71XX_DDR_REG_EMR);
+
+		/* Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Reset DLL */
+		writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+
+		/* Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Auto Refresh */
+		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */
+		writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+		/* Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Enable OCD defaults, Enable DLL, Reduced Drive Strength */
+		writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
+
+		/* Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* OCD exit, Enable DLL, Enable /DQS, Reduced Drive Strength */
+		writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+		/* Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Refresh time control */
+		if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+			writel(DDR_REFRESH_VAL_40M, regs +
+			       AR71XX_DDR_REG_REFRESH);
+		else
+			writel(DDR_REFRESH_VAL_25M, regs +
+			       AR71XX_DDR_REG_REFRESH);
+
+		/* DQS 0 Tap Control */
+		writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
+
+		/* DQS 1 Tap Control */
+		writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+		/* For 16-bit DDR */
+		writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
+	} else {
+		/* AHB maximum timeout */
+		writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Reset DLL, Burst Length 8, CAS Latency 3 */
+		writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+
+		/* Forces an MRS update cycle in DDR */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Enable DLL, Full strength */
+		writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+
+		/* Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Normal DLL, Burst Length 8, CAS Latency 3 */
+		writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+
+		/* Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Refresh time control */
+		if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+			writel(DDR_REFRESH_VAL_40M, regs +
+			       AR71XX_DDR_REG_REFRESH);
+		else
+			writel(DDR_REFRESH_VAL_25M, regs +
+			       AR71XX_DDR_REG_REFRESH);
+
+		/* DQS 0 Tap Control */
+		writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
+
+		/* DQS 1 Tap Control */
+		writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+		/* For 16-bit DDR */
+		writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
+	}
+}
+
+void ddr_tap_tuning(void)
+{
+	void __iomem *regs;
+	u32 *addr_k0, *addr_k1, *addr;
+	u32 val, tap, upper, lower;
+	int i, j, dir, err, done;
+
+	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			   MAP_NOCACHE);
+
+	/* Init memory pattern */
+	addr = (void *)CKSEG0ADDR(0x2000);
+	for (i = 0; i < 256; i++) {
+		val = 0;
+		for (j = 0; j < 8; j++) {
+			if (i & (1 << j)) {
+				if (j % 2)
+					val |= 0xffff0000;
+				else
+					val |= 0x0000ffff;
+			}
+
+			if (j % 2) {
+				*addr++ = val;
+				val = 0;
+			}
+		}
+	}
+
+	err = 0;
+	done = 0;
+	dir = 1;
+	tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
+	val = tap;
+	while (!done) {
+		err = 0;
+
+		/* Update new DDR tap value */
+		writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+		writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+		/* Compare DDR with cache */
+		for (i = 0; i < 2; i++) {
+			addr_k1 = (void *)CKSEG1ADDR(0x2000);
+			addr_k0 = (void *)CKSEG0ADDR(0x2000);
+			addr = (void *)CKSEG0ADDR(0x3000);
+
+			while (addr_k0 < addr) {
+				if (*addr_k1++ != *addr_k0++) {
+					err = 1;
+					break;
+				}
+			}
+
+			if (err)
+				break;
+		}
+
+		if (err) {
+			/* Save upper/lower threshold if error  */
+			if (dir) {
+				dir = 0;
+				val--;
+				upper = val;
+				val = tap;
+			} else {
+				val++;
+				lower = val;
+				done = 1;
+			}
+		} else {
+			/* Try the next value until limitation */
+			if (dir) {
+				if (val < 0x20) {
+					val++;
+				} else {
+					dir = 0;
+					upper = val;
+					val = tap;
+				}
+			} else {
+				if (!val) {
+					lower = val;
+					done = 1;
+				} else {
+					val--;
+				}
+			}
+		}
+	}
+
+	/* compute an intermediate value and write back */
+	val = (upper + lower) / 2;
+	writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+	val++;
+	writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+}
diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S b/arch/mips/mach-ath79/ar933x/lowlevel_init.S
new file mode 100644
index 0000000..1b847f5
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S
@@ -0,0 +1,280 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Based on Atheros LSDK/QSDK and u-boot_mod project
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <mach/ar71xx_regs.h>
+
+#define SET_BIT(val, bit)   ((val) | (1 << (bit)))
+#define SET_PLL_PD(val)     SET_BIT(val, 30)
+#define AHB_DIV_TO_4(val)   SET_BIT(SET_BIT(val, 15), 16)
+#define PLL_BYPASS(val)     SET_BIT(val, 2)
+
+#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
+     (((0x3F & divint) << 10) | \
+     ((0x1F & refdiv) << 16) | \
+     ((0x1 & range)   << 21) | \
+     ((0x7 & outdiv)  << 23) )
+
+#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
+    (((0x3 & (cpudiv - 1)) << 5)  | \
+    ((0x3 & (ddrdiv - 1)) << 10) | \
+    ((0x3 & (ahbdiv - 1)) << 15) )
+
+/*
+ * PLL_CPU_CONFIG_VAL
+ *
+ * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU PLL Configuration (CPU_PLL_CONFIG)
+ *
+ * bits 10..15  (6bit)  DIV_INT (Integer part of the DIV to CPU PLL)
+ *                      =>  32  (0x20)  VCOOUT = XTAL * DIV_INT
+ * bits 16..20  (5bit)  REFDIV  (Reference clock divider)
+ *                      =>  1   (0x1)   [Must start at values 1]
+ * bits 21      (1bit)  RANGE   (VCO frequency range of the CPU PLL)
+ *                      =>  0   (0x0)   [Doesn't impact clock values]
+ * bits 23..25  (3bit)  OUTDIV  (Ratio between VCO and PLL output)
+ *                      =>  1   (0x1)   [0 is illegal!]
+ *                              PLLOUT = VCOOUT * (1/2^OUTDIV)
+ */
+/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_40M  MK_PLL_CONF(20, 1, 0, 1)
+/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_25M  MK_PLL_CONF(32, 1, 0, 1)
+
+/*
+ * PLL_CLK_CONTROL_VAL
+ *
+ * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU Clock Control Register CLOCK_CONTROL
+ *
+ * bits 2       (1bit)  BYPASS (Bypass PLL. This defaults to 1 for test.
+ *                      Software must enable the CPU PLL for normal and
+ *                      then set this bit to 0)
+ * bits 5..6    (2bit)  CPU_POST_DIV    =>  0   (DEFAULT, Ratio = 1)
+ *                      CPU_CLK = PLLOUT / CPU_POST_DIV
+ * bits 10..11  (2bit)  DDR_POST_DIV    =>  0   (DEFAULT, Ratio = 1)
+ *                      DDR_CLK = PLLOUT / DDR_POST_DIV
+ * bits 15..16  (2bit)  AHB_POST_DIV    =>  1   (DEFAULT, Ratio = 2)
+ *                      AHB_CLK = PLLOUT / AHB_POST_DIV
+ *
+ */
+#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2)
+
+    .text
+    .set noreorder
+
+LEAF(lowlevel_init)
+	/* These three WLAN_RESET will avoid original issue */
+	li      t3, 0x03
+1:
+	li      t0, CKSEG1ADDR(AR71XX_RESET_BASE)
+	lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+	ori     t1, t1, 0x0800
+	sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+	nop
+	lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+	li      t2, 0xfffff7ff
+	and     t1, t1, t2
+	sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+	nop
+	addi    t3, t3, -1
+	bnez    t3, 1b
+	nop
+
+	li      t2, 0x20
+2:
+	beqz    t2, 1b
+	nop
+	addi    t2, t2, -1
+	lw      t5, AR933X_RESET_REG_BOOTSTRAP(t0)
+	andi    t1, t5, 0x10
+	bnez    t1, 2b
+	nop
+
+	li      t1, 0x02110E
+	sw      t1, AR933X_RESET_REG_BOOTSTRAP(t0)
+	nop
+
+	/* RTC Force Wake */
+	li      t0, CKSEG1ADDR(AR933X_RTC_BASE)
+	li      t1, 0x03
+	sw      t1, AR933X_RTC_REG_FORCE_WAKE(t0)
+	nop
+	nop
+
+	/* RTC Reset */
+	li      t1, 0x00
+	sw      t1, AR933X_RTC_REG_RESET(t0)
+	nop
+	nop
+
+	li      t1, 0x01
+	sw      t1, AR933X_RTC_REG_RESET(t0)
+	nop
+	nop
+
+	/* Wait for RTC in on state */
+1:
+	lw      t1, AR933X_RTC_REG_STATUS(t0)
+	andi    t1, t1, 0x02
+	beqz    t1, 1b
+	nop
+
+	/* Program ki/kd */
+	li      t0, CKSEG1ADDR(AR933X_SRIF_BASE)
+	andi    t1, t5, 0x01            # t5 BOOT_STRAP
+	bnez    t1, 1f
+	nop
+	li      t1, 0x19e82f01
+	b       2f
+	nop
+1:
+	li      t1, 0x18e82f01
+2:
+	sw      t1, AR933X_SRIF_DDR_DPLL2_REG(t0)
+
+	/* Program phase shift */
+	lw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	li      t2, 0xc07fffff
+	and     t1, t1, t2
+	li      t2, 0x800000
+	or      t1, t1, t2
+	sw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	nop
+
+	/* in some cases, the SoC doesn't start with higher clock on AHB */
+	li      t0, CKSEG1ADDR(AR71XX_PLL_BASE)
+	li      t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL))
+	sw      t1, AR933X_PLL_CLK_CTRL_REG(t0)
+	nop
+
+	/* Set SETTLE_TIME in CPU PLL */
+	andi    t1, t5, 0x01            # t5 BOOT_STRAP
+	bnez    t1, 1f
+	nop
+	li      t1, 0x0352
+	b       2f
+	nop
+1:
+	li      t1, 0x0550
+2:
+	sw      t1, AR71XX_PLL_REG_SEC_CONFIG(t0)
+	nop
+
+	/* Set nint, frac, refdiv, outdiv, range according to xtal */
+0:
+	andi    t1, t5, 0x01            # t5 BOOT_STRAP
+	bnez    t1, 1f
+	nop
+	li      t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M)
+	b       2f
+	nop
+1:
+	li      t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M)
+2:
+	sw      t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+	nop
+1:
+	lw      t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+	li      t2, 0x80000000
+	and     t1, t1, t2
+	bnez    t1, 1b
+	nop
+
+	/* Put frac bit19:10 configuration */
+	li      t1, 0x1003E8
+	sw      t1, AR933X_PLL_DITHER_FRAC_REG(t0)
+	nop
+
+	/* Clear PLL power down bit in CPU PLL configuration */
+	andi    t1, t5, 0x01            # t5 BOOT_STRAP
+	bnez    t1, 1f
+	nop
+	li      t1, PLL_CPU_CONFIG_VAL_25M
+	b       2f
+	nop
+1:
+	li      t1, PLL_CPU_CONFIG_VAL_40M
+2:
+	sw      t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+	nop
+
+	/* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */
+1:
+	lw      t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+	li      t2, 0x80000000
+	and     t1, t1, t2
+	bnez    t1, 1b
+	nop
+
+	/* Confirm DDR PLL lock */
+	li      t3, 100
+	li      t4, 0
+
+2:
+	addi    t4, t4, 1
+	bgt     t4, t3, 0b
+	nop
+
+	li      t3, 5
+3:
+	/* Clear do_meas */
+	li      t0, CKSEG1ADDR(AR933X_SRIF_BASE)
+	lw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	li      t2, 0xBFFFFFFF
+	and     t1, t1, t2
+	sw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	nop
+
+	li      t2, 10
+1:
+	subu    t2, t2, 1
+	bnez    t2, 1b
+	nop
+
+	/* Set do_meas */
+	li      t2, 0x40000000
+	or      t1, t1, t2
+	sw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	nop
+
+	/* Check meas_done */
+1:
+	lw      t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
+	andi    t1, t1, 0x8
+	beqz    t1, 1b
+	nop
+
+	lw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	li      t2, 0x007FFFF8
+	and     t1, t1, t2
+	srl     t1, t1, 3
+	li      t2, 0x4000
+	bgt     t1, t2, 2b
+	nop
+	addi    t3, t3, -1
+	bnez    t3, 3b
+	nop
+
+	/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
+	li      t0, CKSEG1ADDR(AR71XX_PLL_BASE)
+	li      t1, PLL_CLK_CONTROL_VAL
+	sw      t1, AR933X_PLL_CLK_CTRL_REG(t0)
+	nop
+
+	nop
+	jr ra
+	nop
+    END(lowlevel_init)
diff --git a/arch/mips/mach-ath79/ar934x/Makefile b/arch/mips/mach-ath79/ar934x/Makefile
new file mode 100644
index 0000000..348c65b
--- /dev/null
+++ b/arch/mips/mach-ath79/ar934x/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += clk.o
+obj-y += ddr.o
diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c
new file mode 100644
index 0000000..9c65184
--- /dev/null
+++ b/arch/mips/mach-ath79/ar934x/clk.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The math for calculating PLL:
+ *                                       NFRAC * 2^8
+ *                               NINT + -------------
+ *                XTAL [MHz]              2^(18 - 1)
+ *   PLL [MHz] = ------------ * ----------------------
+ *                  REFDIV              2^OUTDIV
+ *
+ * Unfortunatelly, there is no way to reliably compute the variables.
+ * The vendor U-Boot port contains macros for various combinations of
+ * CPU PLL / DDR PLL / AHB bus speed and there is no obvious pattern
+ * in those numbers.
+ */
+struct ar934x_pll_config {
+	u8	range;
+	u8	refdiv;
+	u8	outdiv;
+	/* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
+	u8	nint[2];
+};
+
+struct ar934x_clock_config {
+	u16				cpu_freq;
+	u16				ddr_freq;
+	u16				ahb_freq;
+
+	struct ar934x_pll_config	cpu_pll;
+	struct ar934x_pll_config	ddr_pll;
+};
+
+static const struct ar934x_clock_config ar934x_clock_config[] = {
+	{ 300, 300, 150, { 1, 1, 1, { 24, 15 } }, { 1, 1, 1, { 24, 15 } } },
+	{ 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } },
+	{ 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } },
+	{ 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } },
+	{ 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } },
+	{ 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } },
+	{ 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } },
+	{ 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } },
+	{ 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } },
+	{ 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } },
+	{ 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } },
+	{ 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } },
+	{ 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } },
+	{ 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
+	{ 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
+	{ 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } },
+	{ 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
+	{ 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
+	{ 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } },
+	{ 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } },
+	{ 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } },
+	{ 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } },
+	{ 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } },
+	{ 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } },
+	{ 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } },
+	{ 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } },
+	{ 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } },
+	{ 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } },
+};
+
+static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val)
+{
+	u32 reg;
+	do {
+		writel(0x10810f00, pll_reg_base + 0x4);
+		writel(srif_val, pll_reg_base + 0x0);
+		writel(0xd0810f00, pll_reg_base + 0x4);
+		writel(0x03000000, pll_reg_base + 0x8);
+		writel(0xd0800f00, pll_reg_base + 0x4);
+
+		clrbits_be32(pll_reg_base + 0x8, BIT(30));
+		udelay(5);
+		setbits_be32(pll_reg_base + 0x8, BIT(30));
+		udelay(5);
+
+		wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0);
+
+		clrbits_be32(pll_reg_base + 0x8, BIT(30));
+		udelay(5);
+
+		/* Check if CPU SRIF PLL locked. */
+		reg = readl(pll_reg_base + 0x8);
+		reg = (reg & 0x7ffff8) >> 3;
+	} while (reg >= 0x40000);
+}
+
+void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
+{
+	void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE,
+					      AR934X_SRIF_SIZE, MAP_NOCACHE);
+	void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
+					     AR71XX_PLL_SIZE, MAP_NOCACHE);
+	const struct ar934x_pll_config *pll_cfg;
+	int i, pll_nint, pll_refdiv, xtal_40 = 0;
+	u32 reg, cpu_pll, cpu_srif, ddr_pll, ddr_srif;
+
+	/* Configure SRIF PLL with initial values. */
+	writel(0x13210f00, srif_regs + AR934X_SRIF_CPU_DPLL2_REG);
+	writel(0x03000000, srif_regs + AR934X_SRIF_CPU_DPLL3_REG);
+	writel(0x13210f00, srif_regs + AR934X_SRIF_DDR_DPLL2_REG);
+	writel(0x03000000, srif_regs + AR934X_SRIF_DDR_DPLL3_REG);
+	writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */
+
+	/* Test for 40MHz XTAL */
+	reg = get_bootstrap();
+	if (reg & AR934X_BOOTSTRAP_REF_CLK_40) {
+		xtal_40 = 1;
+		cpu_srif = 0x41c00000;
+		ddr_srif = 0x41680000;
+	} else {
+		xtal_40 = 0;
+		cpu_srif = 0x29c00000;
+		ddr_srif = 0x29680000;
+	}
+
+	/* Locate CPU/DDR PLL configuration */
+	for (i = 0; i < ARRAY_SIZE(ar934x_clock_config); i++) {
+		if (cpu_mhz != ar934x_clock_config[i].cpu_freq)
+			continue;
+		if (ddr_mhz != ar934x_clock_config[i].ddr_freq)
+			continue;
+		if (ahb_mhz != ar934x_clock_config[i].ahb_freq)
+			continue;
+
+		/* Entry found */
+		pll_cfg = &ar934x_clock_config[i].cpu_pll;
+		pll_nint = pll_cfg->nint[xtal_40];
+		pll_refdiv = pll_cfg->refdiv;
+		cpu_pll =
+			(pll_nint << AR934X_PLL_CPU_CONFIG_NINT_SHIFT) |
+			(pll_refdiv << AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) |
+			(pll_cfg->range << AR934X_PLL_CPU_CONFIG_RANGE_SHIFT) |
+			(pll_cfg->outdiv << AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT);
+
+		pll_cfg = &ar934x_clock_config[i].ddr_pll;
+		pll_nint = pll_cfg->nint[xtal_40];
+		pll_refdiv = pll_cfg->refdiv;
+		ddr_pll =
+			(pll_nint << AR934X_PLL_DDR_CONFIG_NINT_SHIFT) |
+			(pll_refdiv << AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) |
+			(pll_cfg->range << AR934X_PLL_DDR_CONFIG_RANGE_SHIFT) |
+			(pll_cfg->outdiv << AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT);
+		break;
+	}
+
+	/* PLL configuration not found, hang. */
+	if (i == ARRAY_SIZE(ar934x_clock_config))
+		hang();
+
+	/* Set PLL Bypass */
+	setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+		     AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);
+	setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+		     AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);
+	setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+		     AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);
+
+	/* Configure CPU PLL */
+	writel(cpu_pll | AR934X_PLL_CPU_CONFIG_PLLPWD,
+	       pll_regs + AR934X_PLL_CPU_CONFIG_REG);
+	/* Configure DDR PLL */
+	writel(ddr_pll | AR934X_PLL_DDR_CONFIG_PLLPWD,
+	       pll_regs + AR934X_PLL_DDR_CONFIG_REG);
+	/* Configure PLL routing */
+	writel(AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS |
+	       AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS |
+	       AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS |
+	       (0 << AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) |
+	       (0 << AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) |
+	       (1 << AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) |
+	       AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL |
+	       AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL |
+	       AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL,
+	       pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
+
+	/* Configure SRIF PLLs, which is completely undocumented :-) */
+	ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_CPU_DPLL1_REG, cpu_srif);
+	ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_DDR_DPLL1_REG, ddr_srif);
+
+	/* Unset PLL Bypass */
+	clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+		     AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);
+	clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+		     AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);
+	clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+		     AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);
+
+	/* Enable PLL dithering */
+	writel((1 << AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT) |
+	       (0xf << AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT),
+	       pll_regs + AR934X_PLL_DDR_DIT_FRAC_REG);
+	writel(48 << AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT,
+	       pll_regs + AR934X_PLL_CPU_DIT_FRAC_REG);
+}
+
+static u32 ar934x_get_xtal(void)
+{
+	u32 val;
+
+	val = get_bootstrap();
+	if (val & AR934X_BOOTSTRAP_REF_CLK_40)
+		return 40000000;
+	else
+		return 25000000;
+}
+
+int get_serial_clock(void)
+{
+	return ar934x_get_xtal();
+}
+
+static u32 ar934x_cpupll_to_hz(const u32 regval)
+{
+	const u32 outdiv = (regval >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+			   AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
+	const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+			   AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
+	const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
+			   AR934X_PLL_CPU_CONFIG_NINT_MASK;
+	const u32 nfrac = (regval >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
+			   AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
+	const u32 xtal = ar934x_get_xtal();
+
+	return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
+}
+
+static u32 ar934x_ddrpll_to_hz(const u32 regval)
+{
+	const u32 outdiv = (regval >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+			   AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
+	const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+			   AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
+	const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
+			   AR934X_PLL_DDR_CONFIG_NINT_MASK;
+	const u32 nfrac = (regval >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
+			   AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
+	const u32 xtal = ar934x_get_xtal();
+
+	return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
+}
+
+static void ar934x_update_clock(void)
+{
+	void __iomem *regs;
+	u32 ctrl, cpu, cpupll, ddr, ddrpll;
+	u32 cpudiv, ddrdiv, busdiv;
+	u32 cpuclk, ddrclk, busclk;
+
+	regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+			   MAP_NOCACHE);
+
+	cpu = readl(regs + AR934X_PLL_CPU_CONFIG_REG);
+	ddr = readl(regs + AR934X_PLL_DDR_CONFIG_REG);
+	ctrl = readl(regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
+
+	cpupll = ar934x_cpupll_to_hz(cpu);
+	ddrpll = ar934x_ddrpll_to_hz(ddr);
+
+	if (ctrl & AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
+		cpuclk = ar934x_get_xtal();
+	else if (ctrl & AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
+		cpuclk = cpupll;
+	else
+		cpuclk = ddrpll;
+
+	if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
+		ddrclk = ar934x_get_xtal();
+	else if (ctrl & AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
+		ddrclk = ddrpll;
+	else
+		ddrclk = cpupll;
+
+	if (ctrl & AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
+		busclk = ar934x_get_xtal();
+	else if (ctrl & AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
+		busclk = ddrpll;
+	else
+		busclk = cpupll;
+
+	cpudiv = (ctrl >> AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+		 AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+	ddrdiv = (ctrl >> AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
+		 AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
+	busdiv = (ctrl >> AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
+		 AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
+
+	gd->cpu_clk = cpuclk / (cpudiv + 1);
+	gd->mem_clk = ddrclk / (ddrdiv + 1);
+	gd->bus_clk = busclk / (busdiv + 1);
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+	ar934x_update_clock();
+	return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+	ar934x_update_clock();
+	return gd->mem_clk;
+}
+
+int do_ar934x_showclk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ar934x_update_clock();
+	printf("CPU:       %8ld MHz\n", gd->cpu_clk / 1000000);
+	printf("Memory:    %8ld MHz\n", gd->mem_clk / 1000000);
+	printf("AHB:       %8ld MHz\n", gd->bus_clk / 1000000);
+	return 0;
+}
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_ar934x_showclk,
+	"display clocks",
+	""
+);
diff --git a/arch/mips/mach-ath79/ar934x/cpu.c b/arch/mips/mach-ath79/ar934x/cpu.c
new file mode 100644
index 0000000..8fcdf65
--- /dev/null
+++ b/arch/mips/mach-ath79/ar934x/cpu.c
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+/* The lowlevel_init() is not needed on AR934x */
+void lowlevel_init(void) {}
diff --git a/arch/mips/mach-ath79/ar934x/ddr.c b/arch/mips/mach-ath79/ar934x/ddr.c
new file mode 100644
index 0000000..4621d58
--- /dev/null
+++ b/arch/mips/mach-ath79/ar934x/ddr.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * Based on RAM init sequence by Piotr Dymacz <pepe2k@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	AR934X_SDRAM = 0,
+	AR934X_DDR1,
+	AR934X_DDR2,
+};
+
+struct ar934x_mem_config {
+	u32	config1;
+	u32	config2;
+	u32	mode;
+	u32	extmode;
+	u32	tap;
+};
+
+static const struct ar934x_mem_config ar934x_mem_config[] = {
+	[AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f },
+	[AR934X_DDR1]  = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 },
+	[AR934X_DDR2]  = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 },
+};
+
+void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
+{
+	void __iomem *ddr_regs;
+	const struct ar934x_mem_config *memcfg;
+	int memtype;
+	u32 reg, cycle, ctl;
+
+	ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			       MAP_NOCACHE);
+
+	reg = get_bootstrap();
+	if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) {	/* DDR */
+		if (reg & AR934X_BOOTSTRAP_DDR1) {	/* DDR 1 */
+			memtype = AR934X_DDR1;
+			cycle = 0xffff;
+		} else {				/* DDR 2 */
+			memtype = AR934X_DDR2;
+			if (gd->arch.rev) {
+				ctl = BIT(6);	/* Undocumented bit :-( */
+				if (reg & BIT(3))
+					cycle = 0xff;
+				else
+					cycle = 0xffff;
+			} else {
+				/* Force DDR2/x16 configuratio on old chips. */
+				ctl = 0;
+				cycle = 0xffff;		/* DDR2 16bit */
+			}
+
+			writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG);
+			udelay(100);
+
+			writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);
+			udelay(10);
+
+			writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);
+			udelay(10);
+
+			writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF);
+			udelay(10);
+		}
+	} else {					/* SDRAM */
+		memtype = AR934X_SDRAM;
+		cycle = 0xffffffff;
+
+		writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF);
+		udelay(100);
+
+		/* Undocumented register */
+		writel(0x13b, ddr_regs + 0x118);
+		udelay(100);
+	}
+
+	memcfg = &ar934x_mem_config[memtype];
+
+	writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG);
+	udelay(100);
+
+	writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);
+	udelay(100);
+
+	writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
+	udelay(10);
+
+	writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE);
+	mdelay(1);
+
+	writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
+	udelay(10);
+
+	if (memtype == AR934X_DDR2) {
+		writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR);
+		udelay(100);
+
+		writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
+		udelay(10);
+	}
+
+	if (memtype != AR934X_SDRAM)
+		writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR);
+
+	udelay(100);
+
+	writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
+	udelay(10);
+
+	writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
+	udelay(10);
+
+	writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE);
+	udelay(100);
+
+	writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
+	udelay(10);
+
+	writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH);
+	udelay(100);
+
+	writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);
+	writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+	if (memtype != AR934X_SDRAM) {
+		if ((gd->arch.rev && (reg & BIT(3))) || !gd->arch.rev) {
+			writel(memcfg->tap,
+			       ddr_regs + AR934X_DDR_REG_TAP_CTRL2);
+			writel(memcfg->tap,
+			       ddr_regs + AR934X_DDR_REG_TAP_CTRL3);
+		}
+	}
+
+	writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE);
+	udelay(100);
+
+	writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST);
+	udelay(100);
+
+	writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2);
+	udelay(100);
+
+	writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX);
+	udelay(100);
+}
+
+void ddr_tap_tuning(void)
+{
+}
diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c
new file mode 100644
index 0000000..5756a06
--- /dev/null
+++ b/arch/mips/mach-ath79/cpu.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>
+
+struct ath79_soc_desc {
+	const enum ath79_soc_type soc;
+	const char *chip;
+	const int major;
+	const int minor;
+};
+
+static const struct ath79_soc_desc desc[] = {
+	{ATH79_SOC_AR7130,      "7130",
+	 REV_ID_MAJOR_AR71XX,   AR71XX_REV_ID_MINOR_AR7130},
+	{ATH79_SOC_AR7141,      "7141",
+	 REV_ID_MAJOR_AR71XX,   AR71XX_REV_ID_MINOR_AR7141},
+	{ATH79_SOC_AR7161,      "7161",
+	 REV_ID_MAJOR_AR71XX,   AR71XX_REV_ID_MINOR_AR7161},
+	{ATH79_SOC_AR7240,      "7240", REV_ID_MAJOR_AR7240,    0},
+	{ATH79_SOC_AR7241,      "7241", REV_ID_MAJOR_AR7241,    0},
+	{ATH79_SOC_AR7242,      "7242", REV_ID_MAJOR_AR7242,    0},
+	{ATH79_SOC_AR9130,      "9130",
+	 REV_ID_MAJOR_AR913X,   AR913X_REV_ID_MINOR_AR9130},
+	{ATH79_SOC_AR9132,      "9132",
+	 REV_ID_MAJOR_AR913X,   AR913X_REV_ID_MINOR_AR9132},
+	{ATH79_SOC_AR9330,      "9330", REV_ID_MAJOR_AR9330,    0},
+	{ATH79_SOC_AR9331,      "9331", REV_ID_MAJOR_AR9331,    0},
+	{ATH79_SOC_AR9341,      "9341", REV_ID_MAJOR_AR9341,    0},
+	{ATH79_SOC_AR9342,      "9342", REV_ID_MAJOR_AR9342,    0},
+	{ATH79_SOC_AR9344,      "9344", REV_ID_MAJOR_AR9344,    0},
+	{ATH79_SOC_QCA9533,     "9533", REV_ID_MAJOR_QCA9533,   0},
+	{ATH79_SOC_QCA9533,     "9533",
+	 REV_ID_MAJOR_QCA9533_V2,       0},
+	{ATH79_SOC_QCA9556,     "9556", REV_ID_MAJOR_QCA9556,   0},
+	{ATH79_SOC_QCA9558,     "9558", REV_ID_MAJOR_QCA9558,   0},
+	{ATH79_SOC_TP9343,      "9343", REV_ID_MAJOR_TP9343,    0},
+	{ATH79_SOC_QCA9561,     "9561", REV_ID_MAJOR_QCA9561,   0},
+};
+
+int arch_cpu_init(void)
+{
+	void __iomem *base;
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	u32 id, major, minor = 0;
+	u32 rev = 0, ver = 1;
+	int i;
+
+	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+			   MAP_NOCACHE);
+
+	id = readl(base + AR71XX_RESET_REG_REV_ID);
+	major = id & REV_ID_MAJOR_MASK;
+	switch (major) {
+	case REV_ID_MAJOR_AR71XX:
+	case REV_ID_MAJOR_AR913X:
+		minor = id & AR71XX_REV_ID_MINOR_MASK;
+		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+		rev &= AR71XX_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_QCA9533_V2:
+		ver = 2;
+		/* drop through */
+
+	case REV_ID_MAJOR_AR9341:
+	case REV_ID_MAJOR_AR9342:
+	case REV_ID_MAJOR_AR9344:
+	case REV_ID_MAJOR_QCA9533:
+	case REV_ID_MAJOR_QCA9556:
+	case REV_ID_MAJOR_QCA9558:
+	case REV_ID_MAJOR_TP9343:
+	case REV_ID_MAJOR_QCA9561:
+		rev = id & AR71XX_REV_ID_REVISION2_MASK;
+		break;
+	default:
+		rev = id & AR71XX_REV_ID_REVISION_MASK;
+		break;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(desc); i++) {
+		if ((desc[i].major == major) &&
+		    (desc[i].minor == minor)) {
+			soc = desc[i].soc;
+			break;
+		}
+	}
+
+	gd->arch.id = id;
+	gd->arch.soc = soc;
+	gd->arch.rev = rev;
+	gd->arch.ver = ver;
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	const char *chip = "????";
+	u32 id, rev, ver;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(desc); i++) {
+		if (desc[i].soc == gd->arch.soc) {
+			chip = desc[i].chip;
+			soc = desc[i].soc;
+			break;
+		}
+	}
+
+	id = gd->arch.id;
+	rev = gd->arch.rev;
+	ver = gd->arch.ver;
+
+	switch (soc) {
+	case ATH79_SOC_QCA9533:
+	case ATH79_SOC_QCA9556:
+	case ATH79_SOC_QCA9558:
+	case ATH79_SOC_QCA9561:
+		printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip,
+		       ver, rev);
+		break;
+	case ATH79_SOC_TP9343:
+		printf("Qualcomm Atheros TP%s rev %u\n", chip, rev);
+		break;
+	case ATH79_SOC_UNKNOWN:
+		printf("ATH79: unknown SoC, id:0x%08x", id);
+		break;
+	default:
+		printf("Atheros AR%s rev %u\n", chip, rev);
+	}
+
+	return 0;
+}
diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c
new file mode 100644
index 0000000..c29e98c
--- /dev/null
+++ b/arch/mips/mach-ath79/dram.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/addrspace.h>
+#include <mach/ddr.h>
+
+phys_size_t initdram(int board_type)
+{
+	ddr_tap_tuning();
+	return get_ram_size((void *)KSEG1, SZ_256M);
+}
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
new file mode 100644
index 0000000..a8e51cb
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -0,0 +1,1263 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H
+#define __ASM_MACH_AR71XX_REGS_H
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#else
+#ifndef BIT
+#define BIT(nr)		(1 << (nr))
+#endif
+#endif
+
+#define AR71XX_APB_BASE					0x18000000
+#define AR71XX_GE0_BASE					0x19000000
+#define AR71XX_GE0_SIZE					0x10000
+#define AR71XX_GE1_BASE					0x1a000000
+#define AR71XX_GE1_SIZE					0x10000
+#define AR71XX_EHCI_BASE				0x1b000000
+#define AR71XX_EHCI_SIZE				0x1000
+#define AR71XX_OHCI_BASE				0x1c000000
+#define AR71XX_OHCI_SIZE				0x1000
+#define AR71XX_SPI_BASE					0x1f000000
+#define AR71XX_SPI_SIZE					0x01000000
+
+#define AR71XX_DDR_CTRL_BASE \
+	(AR71XX_APB_BASE + 0x00000000)
+#define AR71XX_DDR_CTRL_SIZE				0x100
+#define AR71XX_UART_BASE \
+	(AR71XX_APB_BASE + 0x00020000)
+#define AR71XX_UART_SIZE				0x100
+#define AR71XX_USB_CTRL_BASE \
+	(AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_SIZE				0x100
+#define AR71XX_GPIO_BASE \
+	(AR71XX_APB_BASE + 0x00040000)
+#define AR71XX_GPIO_SIZE				0x100
+#define AR71XX_PLL_BASE \
+	(AR71XX_APB_BASE + 0x00050000)
+#define AR71XX_PLL_SIZE					0x100
+#define AR71XX_RESET_BASE \
+	(AR71XX_APB_BASE + 0x00060000)
+#define AR71XX_RESET_SIZE				0x100
+#define AR71XX_MII_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
+#define AR71XX_MII_SIZE					0x100
+
+#define AR71XX_PCI_MEM_BASE				0x10000000
+#define AR71XX_PCI_MEM_SIZE				0x07000000
+
+#define AR71XX_PCI_WIN0_OFFS				0x10000000
+#define AR71XX_PCI_WIN1_OFFS				0x11000000
+#define AR71XX_PCI_WIN2_OFFS				0x12000000
+#define AR71XX_PCI_WIN3_OFFS				0x13000000
+#define AR71XX_PCI_WIN4_OFFS				0x14000000
+#define AR71XX_PCI_WIN5_OFFS				0x15000000
+#define AR71XX_PCI_WIN6_OFFS				0x16000000
+#define AR71XX_PCI_WIN7_OFFS				0x07000000
+
+#define AR71XX_PCI_CFG_BASE \
+	(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
+#define AR71XX_PCI_CFG_SIZE				0x100
+
+#define AR7240_USB_CTRL_BASE \
+	(AR71XX_APB_BASE + 0x00030000)
+#define AR7240_USB_CTRL_SIZE				0x100
+#define AR7240_OHCI_BASE				0x1b000000
+#define AR7240_OHCI_SIZE				0x1000
+
+#define AR724X_PCI_MEM_BASE				0x10000000
+#define AR724X_PCI_MEM_SIZE				0x04000000
+
+#define AR724X_PCI_CFG_BASE				0x14000000
+#define AR724X_PCI_CFG_SIZE				0x1000
+#define AR724X_PCI_CRP_BASE \
+	(AR71XX_APB_BASE + 0x000c0000)
+#define AR724X_PCI_CRP_SIZE				0x1000
+#define AR724X_PCI_CTRL_BASE \
+	(AR71XX_APB_BASE + 0x000f0000)
+#define AR724X_PCI_CTRL_SIZE				0x100
+
+#define AR724X_EHCI_BASE				0x1b000000
+#define AR724X_EHCI_SIZE				0x1000
+
+#define AR913X_EHCI_BASE				0x1b000000
+#define AR913X_EHCI_SIZE				0x1000
+#define AR913X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x000C0000)
+#define AR913X_WMAC_SIZE				0x30000
+
+#define AR933X_UART_BASE \
+	(AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE				0x14
+#define AR933X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
+#define AR933X_GMAC_SIZE				0x04
+#define AR933X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE				0x20000
+#define AR933X_RTC_BASE \
+	(AR71XX_APB_BASE + 0x00107000)
+#define AR933X_RTC_SIZE					0x1000
+#define AR933X_EHCI_BASE				0x1b000000
+#define AR933X_EHCI_SIZE				0x1000
+#define AR933X_SRIF_BASE \
+	(AR71XX_APB_BASE + 0x00116000)
+#define AR933X_SRIF_SIZE				0x1000
+
+#define AR934X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
+#define AR934X_GMAC_SIZE				0x14
+#define AR934X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE				0x20000
+#define AR934X_EHCI_BASE				0x1b000000
+#define AR934X_EHCI_SIZE				0x200
+#define AR934X_NFC_BASE					0x1b000200
+#define AR934X_NFC_SIZE					0xb8
+#define AR934X_SRIF_BASE \
+	(AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_SIZE				0x1000
+
+#define QCA953X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
+#define QCA953X_GMAC_SIZE				0x14
+#define QCA953X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
+#define QCA953X_WMAC_SIZE				0x20000
+#define QCA953X_RTC_BASE \
+	(AR71XX_APB_BASE + 0x00107000)
+#define QCA953X_RTC_SIZE				0x1000
+#define QCA953X_EHCI_BASE				0x1b000000
+#define QCA953X_EHCI_SIZE				0x200
+#define QCA953X_SRIF_BASE \
+	(AR71XX_APB_BASE + 0x00116000)
+#define QCA953X_SRIF_SIZE				0x1000
+
+#define QCA953X_PCI_CFG_BASE0				0x14000000
+#define QCA953X_PCI_CTRL_BASE0 \
+	(AR71XX_APB_BASE + 0x000f0000)
+#define QCA953X_PCI_CRP_BASE0 \
+	(AR71XX_APB_BASE + 0x000c0000)
+#define QCA953X_PCI_MEM_BASE0				0x10000000
+#define QCA953X_PCI_MEM_SIZE				0x02000000
+
+#define QCA955X_PCI_MEM_BASE0				0x10000000
+#define QCA955X_PCI_MEM_BASE1				0x12000000
+#define QCA955X_PCI_MEM_SIZE				0x02000000
+#define QCA955X_PCI_CFG_BASE0				0x14000000
+#define QCA955X_PCI_CFG_BASE1				0x16000000
+#define QCA955X_PCI_CFG_SIZE				0x1000
+#define QCA955X_PCI_CRP_BASE0 \
+	(AR71XX_APB_BASE + 0x000c0000)
+#define QCA955X_PCI_CRP_BASE1 \
+	(AR71XX_APB_BASE + 0x00250000)
+#define QCA955X_PCI_CRP_SIZE				0x1000
+#define QCA955X_PCI_CTRL_BASE0 \
+	(AR71XX_APB_BASE + 0x000f0000)
+#define QCA955X_PCI_CTRL_BASE1 \
+	(AR71XX_APB_BASE + 0x00280000)
+#define QCA955X_PCI_CTRL_SIZE				0x100
+
+#define QCA955X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
+#define QCA955X_GMAC_SIZE				0x40
+#define QCA955X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
+#define QCA955X_WMAC_SIZE				0x20000
+#define QCA955X_EHCI0_BASE				0x1b000000
+#define QCA955X_EHCI1_BASE				0x1b400000
+#define QCA955X_EHCI_SIZE				0x1000
+#define QCA955X_NFC_BASE				0x1b800200
+#define QCA955X_NFC_SIZE				0xb8
+
+#define QCA956X_PCI_MEM_BASE1				0x12000000
+#define QCA956X_PCI_MEM_SIZE				0x02000000
+#define QCA956X_PCI_CFG_BASE1				0x16000000
+#define QCA956X_PCI_CFG_SIZE				0x1000
+#define QCA956X_PCI_CRP_BASE1 \
+	(AR71XX_APB_BASE + 0x00250000)
+#define QCA956X_PCI_CRP_SIZE				0x1000
+#define QCA956X_PCI_CTRL_BASE1 \
+	(AR71XX_APB_BASE + 0x00280000)
+#define QCA956X_PCI_CTRL_SIZE				0x100
+
+#define QCA956X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
+#define QCA956X_WMAC_SIZE				0x20000
+#define QCA956X_EHCI0_BASE				0x1b000000
+#define QCA956X_EHCI1_BASE				0x1b400000
+#define QCA956X_EHCI_SIZE				0x200
+#define QCA956X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
+#define QCA956X_GMAC_SIZE				0x64
+
+/*
+ * DDR_CTRL block
+ */
+#define AR71XX_DDR_REG_CONFIG				0x00
+#define AR71XX_DDR_REG_CONFIG2				0x04
+#define AR71XX_DDR_REG_MODE				0x08
+#define AR71XX_DDR_REG_EMR				0x0c
+#define AR71XX_DDR_REG_CONTROL				0x10
+#define AR71XX_DDR_REG_REFRESH				0x14
+#define AR71XX_DDR_REG_RD_CYCLE				0x18
+#define AR71XX_DDR_REG_TAP_CTRL0			0x1c
+#define AR71XX_DDR_REG_TAP_CTRL1			0x20
+
+#define AR71XX_DDR_REG_PCI_WIN0				0x7c
+#define AR71XX_DDR_REG_PCI_WIN1				0x80
+#define AR71XX_DDR_REG_PCI_WIN2				0x84
+#define AR71XX_DDR_REG_PCI_WIN3				0x88
+#define AR71XX_DDR_REG_PCI_WIN4				0x8c
+#define AR71XX_DDR_REG_PCI_WIN5				0x90
+#define AR71XX_DDR_REG_PCI_WIN6				0x94
+#define AR71XX_DDR_REG_PCI_WIN7				0x98
+#define AR71XX_DDR_REG_FLUSH_GE0			0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1			0xa0
+#define AR71XX_DDR_REG_FLUSH_USB			0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI			0xa8
+
+#define AR724X_DDR_REG_FLUSH_GE0			0x7c
+#define AR724X_DDR_REG_FLUSH_GE1			0x80
+#define AR724X_DDR_REG_FLUSH_USB			0x84
+#define AR724X_DDR_REG_FLUSH_PCIE			0x88
+
+#define AR913X_DDR_REG_FLUSH_GE0			0x7c
+#define AR913X_DDR_REG_FLUSH_GE1			0x80
+#define AR913X_DDR_REG_FLUSH_USB			0x84
+#define AR913X_DDR_REG_FLUSH_WMAC			0x88
+
+#define AR933X_DDR_REG_FLUSH_GE0			0x7c
+#define AR933X_DDR_REG_FLUSH_GE1			0x80
+#define AR933X_DDR_REG_FLUSH_USB			0x84
+#define AR933X_DDR_REG_FLUSH_WMAC			0x88
+#define AR933X_DDR_REG_DDR2_CONFIG			0x8c
+#define AR933X_DDR_REG_EMR2				0x90
+#define AR933X_DDR_REG_EMR3				0x94
+#define AR933X_DDR_REG_BURST				0x98
+#define AR933X_DDR_REG_TIMEOUT_MAX			0x9c
+#define AR933X_DDR_REG_TIMEOUT_CNT			0x9c
+#define AR933X_DDR_REG_TIMEOUT_ADDR			0x9c
+
+#define AR934X_DDR_REG_TAP_CTRL2			0x24
+#define AR934X_DDR_REG_TAP_CTRL3			0x28
+#define AR934X_DDR_REG_FLUSH_GE0			0x9c
+#define AR934X_DDR_REG_FLUSH_GE1			0xa0
+#define AR934X_DDR_REG_FLUSH_USB			0xa4
+#define AR934X_DDR_REG_FLUSH_PCIE			0xa8
+#define AR934X_DDR_REG_FLUSH_WMAC			0xac
+#define AR934X_DDR_REG_FLUSH_SRC1			0xb0
+#define AR934X_DDR_REG_FLUSH_SRC2			0xb4
+#define AR934X_DDR_REG_DDR2_CONFIG			0xb8
+#define AR934X_DDR_REG_EMR2				0xbc
+#define AR934X_DDR_REG_EMR3				0xc0
+#define AR934X_DDR_REG_BURST				0xc4
+#define AR934X_DDR_REG_BURST2				0xc8
+#define AR934X_DDR_REG_TIMEOUT_MAX			0xcc
+#define AR934X_DDR_REG_CTL_CONF				0x108
+
+#define QCA953X_DDR_REG_FLUSH_GE0			0x9c
+#define QCA953X_DDR_REG_FLUSH_GE1			0xa0
+#define QCA953X_DDR_REG_FLUSH_USB			0xa4
+#define QCA953X_DDR_REG_FLUSH_PCIE			0xa8
+#define QCA953X_DDR_REG_FLUSH_WMAC			0xac
+#define QCA953X_DDR_REG_DDR2_CONFIG			0xb8
+#define QCA953X_DDR_REG_BURST				0xc4
+#define QCA953X_DDR_REG_BURST2				0xc8
+#define QCA953X_DDR_REG_TIMEOUT_MAX			0xcc
+#define QCA953X_DDR_REG_CTL_CONF			0x108
+#define QCA953X_DDR_REG_CONFIG3				0x15c
+
+/*
+ * PLL block
+ */
+#define AR71XX_PLL_REG_CPU_CONFIG			0x00
+#define AR71XX_PLL_REG_SEC_CONFIG			0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK			0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK			0x14
+
+#define AR71XX_PLL_DIV_SHIFT				3
+#define AR71XX_PLL_DIV_MASK				0x1f
+#define AR71XX_CPU_DIV_SHIFT				16
+#define AR71XX_CPU_DIV_MASK				0x3
+#define AR71XX_DDR_DIV_SHIFT				18
+#define AR71XX_DDR_DIV_MASK				0x3
+#define AR71XX_AHB_DIV_SHIFT				20
+#define AR71XX_AHB_DIV_MASK				0x7
+
+#define AR71XX_ETH0_PLL_SHIFT				17
+#define AR71XX_ETH1_PLL_SHIFT				19
+
+#define AR724X_PLL_REG_CPU_CONFIG			0x00
+#define AR724X_PLL_REG_PCIE_CONFIG			0x18
+
+#define AR724X_PLL_DIV_SHIFT				0
+#define AR724X_PLL_DIV_MASK				0x3ff
+#define AR724X_PLL_REF_DIV_SHIFT			10
+#define AR724X_PLL_REF_DIV_MASK				0xf
+#define AR724X_AHB_DIV_SHIFT				19
+#define AR724X_AHB_DIV_MASK				0x1
+#define AR724X_DDR_DIV_SHIFT				22
+#define AR724X_DDR_DIV_MASK				0x3
+
+#define AR7242_PLL_REG_ETH0_INT_CLOCK			0x2c
+
+#define AR913X_PLL_REG_CPU_CONFIG			0x00
+#define AR913X_PLL_REG_ETH_CONFIG			0x04
+#define AR913X_PLL_REG_ETH0_INT_CLOCK			0x14
+#define AR913X_PLL_REG_ETH1_INT_CLOCK			0x18
+
+#define AR913X_PLL_DIV_SHIFT				0
+#define AR913X_PLL_DIV_MASK				0x3ff
+#define AR913X_DDR_DIV_SHIFT				22
+#define AR913X_DDR_DIV_MASK				0x3
+#define AR913X_AHB_DIV_SHIFT				19
+#define AR913X_AHB_DIV_MASK				0x1
+
+#define AR913X_ETH0_PLL_SHIFT				20
+#define AR913X_ETH1_PLL_SHIFT				22
+
+#define AR933X_PLL_CPU_CONFIG_REG			0x00
+#define AR933X_PLL_CLK_CTRL_REG				0x08
+#define AR933X_PLL_DITHER_FRAC_REG			0x10
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT		10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK			0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT		16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK		0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT		23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK		0x7
+
+#define AR933X_PLL_CLK_CTRL_BYPASS			BIT(2)
+#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
+#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x3
+#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
+#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x3
+#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
+#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x7
+
+#define AR934X_PLL_CPU_CONFIG_REG			0x00
+#define AR934X_PLL_DDR_CONFIG_REG			0x04
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG			0x08
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG		0x24
+#define AR934X_PLL_ETH_XMII_CONTROL_REG			0x2c
+#define AR934X_PLL_DDR_DIT_FRAC_REG			0x44
+#define AR934X_PLL_CPU_DIT_FRAC_REG			0x48
+
+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT		0
+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK		0x3f
+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT		6
+#define AR934X_PLL_CPU_CONFIG_NINT_MASK			0x3f
+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT		12
+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK		0x1f
+#define AR934X_PLL_CPU_CONFIG_RANGE_SHIFT		17
+#define AR934X_PLL_CPU_CONFIG_RANGE_MASK		0x3
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT		19
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK		0x3
+#define AR934X_PLL_CPU_CONFIG_PLLPWD			BIT(30)
+#define AR934X_PLL_CPU_CONFIG_UPDATING			BIT(31)
+
+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT		0
+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK		0x3ff
+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT		10
+#define AR934X_PLL_DDR_CONFIG_NINT_MASK			0x3f
+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT		16
+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK		0x1f
+#define AR934X_PLL_DDR_CONFIG_RANGE_SHIFT		21
+#define AR934X_PLL_DDR_CONFIG_RANGE_MASK		0x3
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT		23
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK		0x7
+#define AR934X_PLL_DDR_CONFIG_PLLPWD			BIT(30)
+#define AR934X_PLL_DDR_CONFIG_UPDATING			BIT(31)
+
+#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
+#define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
+#define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
+#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
+#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
+#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
+#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
+#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
+#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
+#define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
+#define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
+#define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
+
+#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL		BIT(6)
+
+#define AR934X_PLL_DDR_DIT_FRAC_MAX_SHIFT		0
+#define AR934X_PLL_DDR_DIT_FRAC_MAX_MASK		0x3ff
+#define AR934X_PLL_DDR_DIT_FRAC_MIN_SHIFT		10
+#define AR934X_PLL_DDR_DIT_FRAC_MIN_MASK		0x3ff
+#define AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT		20
+#define AR934X_PLL_DDR_DIT_FRAC_STEP_MASK		0x3f
+#define AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT		27
+#define AR934X_PLL_DDR_DIT_UPD_CNT_MASK			0x3f
+#define AR934X_PLL_DDR_DIT_DITHER_EN			BIT(31)
+
+#define AR934X_PLL_CPU_DIT_FRAC_MAX_SHIFT		0
+#define AR934X_PLL_CPU_DIT_FRAC_MAX_MASK		0x3f
+#define AR934X_PLL_CPU_DIT_FRAC_MIN_SHIFT		6
+#define AR934X_PLL_CPU_DIT_FRAC_MIN_MASK		0x3f
+#define AR934X_PLL_CPU_DIT_FRAC_STEP_SHIFT		12
+#define AR934X_PLL_CPU_DIT_FRAC_STEP_MASK		0x3f
+#define AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT		18
+#define AR934X_PLL_CPU_DIT_UPD_CNT_MASK			0x3f
+#define AR934X_PLL_CPU_DIT_DITHER_EN			BIT(31)
+
+#define QCA953X_PLL_CPU_CONFIG_REG			0x00
+#define QCA953X_PLL_DDR_CONFIG_REG			0x04
+#define QCA953X_PLL_CLK_CTRL_REG			0x08
+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG		0x24
+#define QCA953X_PLL_ETH_XMII_CONTROL_REG		0x2c
+#define QCA953X_PLL_DDR_DIT_FRAC_REG			0x44
+#define QCA953X_PLL_CPU_DIT_FRAC_REG			0x48
+
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT		0
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK		0x3f
+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT		6
+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK		0x3f
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT		12
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK		0x1f
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT		19
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK		0x7
+
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT		0
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK		0x3ff
+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT		10
+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK		0x3f
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT		16
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK		0x1f
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT		23
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK		0x7
+
+#define QCA953X_PLL_CONFIG_PWD		BIT(30)
+
+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
+
+#define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT		0
+#define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK		0x3f
+#define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT		6
+#define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK		0x3f
+#define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT		12
+#define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK		0x3f
+#define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT		18
+#define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK		0x3f
+
+#define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT		0
+#define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK		0x3ff
+#define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT		9
+#define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK		0x3ff
+#define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT		20
+#define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK		0x3f
+#define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT		27
+#define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK		0x3f
+
+#define QCA953X_PLL_DIT_FRAC_EN				BIT(31)
+
+#define QCA955X_PLL_CPU_CONFIG_REG			0x00
+#define QCA955X_PLL_DDR_CONFIG_REG			0x04
+#define QCA955X_PLL_CLK_CTRL_REG			0x08
+#define QCA955X_PLL_ETH_XMII_CONTROL_REG		0x28
+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG		0x48
+
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT		0
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK		0x3f
+#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT		6
+#define QCA955X_PLL_CPU_CONFIG_NINT_MASK		0x3f
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT		12
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK		0x1f
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT		19
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK		0x3
+
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT		0
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK		0x3ff
+#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT		10
+#define QCA955X_PLL_DDR_CONFIG_NINT_MASK		0x3f
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT		16
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK		0x1f
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT		23
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK		0x7
+
+#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
+#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
+#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
+#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
+#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
+#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
+
+#define QCA956X_PLL_CPU_CONFIG_REG			0x00
+#define QCA956X_PLL_CPU_CONFIG1_REG			0x04
+#define QCA956X_PLL_DDR_CONFIG_REG			0x08
+#define QCA956X_PLL_DDR_CONFIG1_REG			0x0c
+#define QCA956X_PLL_CLK_CTRL_REG			0x10
+
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT		12
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK		0x1f
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT		19
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK		0x7
+
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT		0
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK		0x1f
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT		5
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK		0x3fff
+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT		18
+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK		0x1ff
+
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT		16
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK		0x1f
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT		23
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK		0x7
+
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT		0
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK		0x1f
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT		5
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK		0x3fff
+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT		18
+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK		0x1ff
+
+#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
+#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
+#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL	BIT(20)
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL	BIT(21)
+#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
+
+/*
+ * USB_CONFIG block
+ */
+#define AR71XX_USB_CTRL_REG_FLADJ			0x00
+#define AR71XX_USB_CTRL_REG_CONFIG			0x04
+
+/*
+ * RESET block
+ */
+#define AR71XX_RESET_REG_TIMER				0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD			0x04
+#define AR71XX_RESET_REG_WDOG_CTRL			0x08
+#define AR71XX_RESET_REG_WDOG				0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS		0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE		0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS			0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE			0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS		0x20
+#define AR71XX_RESET_REG_RESET_MODULE			0x24
+#define AR71XX_RESET_REG_PERFC_CTRL			0x2c
+#define AR71XX_RESET_REG_PERFC0				0x30
+#define AR71XX_RESET_REG_PERFC1				0x34
+#define AR71XX_RESET_REG_REV_ID				0x90
+
+#define AR913X_RESET_REG_GLOBAL_INT_STATUS		0x18
+#define AR913X_RESET_REG_RESET_MODULE			0x1c
+#define AR913X_RESET_REG_PERF_CTRL			0x20
+#define AR913X_RESET_REG_PERFC0				0x24
+#define AR913X_RESET_REG_PERFC1				0x28
+
+#define AR724X_RESET_REG_RESET_MODULE			0x1c
+
+#define AR933X_RESET_REG_RESET_MODULE			0x1c
+#define AR933X_RESET_REG_BOOTSTRAP			0xac
+
+#define AR934X_RESET_REG_RESET_MODULE			0x1c
+#define AR934X_RESET_REG_BOOTSTRAP			0xb0
+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS		0xac
+
+#define QCA953X_RESET_REG_RESET_MODULE			0x1c
+#define QCA953X_RESET_REG_BOOTSTRAP			0xb0
+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS		0xac
+
+#define QCA955X_RESET_REG_RESET_MODULE			0x1c
+#define QCA955X_RESET_REG_BOOTSTRAP			0xb0
+#define QCA955X_RESET_REG_EXT_INT_STATUS		0xac
+
+#define QCA956X_RESET_REG_RESET_MODULE			0x1c
+#define QCA956X_RESET_REG_BOOTSTRAP			0xb0
+#define QCA956X_RESET_REG_EXT_INT_STATUS		0xac
+
+#define MISC_INT_MIPS_SI_TIMERINT_MASK			BIT(28)
+#define MISC_INT_ETHSW					BIT(12)
+#define MISC_INT_TIMER4					BIT(10)
+#define MISC_INT_TIMER3					BIT(9)
+#define MISC_INT_TIMER2					BIT(8)
+#define MISC_INT_DMA					BIT(7)
+#define MISC_INT_OHCI					BIT(6)
+#define MISC_INT_PERFC					BIT(5)
+#define MISC_INT_WDOG					BIT(4)
+#define MISC_INT_UART					BIT(3)
+#define MISC_INT_GPIO					BIT(2)
+#define MISC_INT_ERROR					BIT(1)
+#define MISC_INT_TIMER					BIT(0)
+
+#define AR71XX_RESET_EXTERNAL				BIT(28)
+#define AR71XX_RESET_FULL_CHIP				BIT(24)
+#define AR71XX_RESET_CPU_NMI				BIT(21)
+#define AR71XX_RESET_CPU_COLD				BIT(20)
+#define AR71XX_RESET_DMA				BIT(19)
+#define AR71XX_RESET_SLIC				BIT(18)
+#define AR71XX_RESET_STEREO				BIT(17)
+#define AR71XX_RESET_DDR				BIT(16)
+#define AR71XX_RESET_GE1_MAC				BIT(13)
+#define AR71XX_RESET_GE1_PHY				BIT(12)
+#define AR71XX_RESET_USBSUS_OVERRIDE			BIT(10)
+#define AR71XX_RESET_GE0_MAC				BIT(9)
+#define AR71XX_RESET_GE0_PHY				BIT(8)
+#define AR71XX_RESET_USB_OHCI_DLL			BIT(6)
+#define AR71XX_RESET_USB_HOST				BIT(5)
+#define AR71XX_RESET_USB_PHY				BIT(4)
+#define AR71XX_RESET_PCI_BUS				BIT(1)
+#define AR71XX_RESET_PCI_CORE				BIT(0)
+
+#define AR7240_RESET_USB_HOST				BIT(5)
+#define AR7240_RESET_OHCI_DLL				BIT(3)
+
+#define AR724X_RESET_GE1_MDIO				BIT(23)
+#define AR724X_RESET_GE0_MDIO				BIT(22)
+#define AR724X_RESET_PCIE_PHY_SERIAL			BIT(10)
+#define AR724X_RESET_PCIE_PHY				BIT(7)
+#define AR724X_RESET_PCIE				BIT(6)
+#define AR724X_RESET_USB_HOST				BIT(5)
+#define AR724X_RESET_USB_PHY				BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE			BIT(3)
+
+#define AR913X_RESET_AMBA2WMAC				BIT(22)
+#define AR913X_RESET_USBSUS_OVERRIDE			BIT(10)
+#define AR913X_RESET_USB_HOST				BIT(5)
+#define AR913X_RESET_USB_PHY				BIT(4)
+
+#define AR933X_RESET_GE1_MDIO				BIT(23)
+#define AR933X_RESET_GE0_MDIO				BIT(22)
+#define AR933X_RESET_GE1_MAC				BIT(13)
+#define AR933X_RESET_WMAC				BIT(11)
+#define AR933X_RESET_GE0_MAC				BIT(9)
+#define AR933X_RESET_ETH_SWITCH				BIT(8)
+#define AR933X_RESET_USB_HOST				BIT(5)
+#define AR933X_RESET_USB_PHY				BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE			BIT(3)
+
+#define AR934X_RESET_HOST				BIT(31)
+#define AR934X_RESET_SLIC				BIT(30)
+#define AR934X_RESET_HDMA				BIT(29)
+#define AR934X_RESET_EXTERNAL				BIT(28)
+#define AR934X_RESET_RTC				BIT(27)
+#define AR934X_RESET_PCIE_EP_INT			BIT(26)
+#define AR934X_RESET_CHKSUM_ACC				BIT(25)
+#define AR934X_RESET_FULL_CHIP				BIT(24)
+#define AR934X_RESET_GE1_MDIO				BIT(23)
+#define AR934X_RESET_GE0_MDIO				BIT(22)
+#define AR934X_RESET_CPU_NMI				BIT(21)
+#define AR934X_RESET_CPU_COLD				BIT(20)
+#define AR934X_RESET_HOST_RESET_INT			BIT(19)
+#define AR934X_RESET_PCIE_EP				BIT(18)
+#define AR934X_RESET_UART1				BIT(17)
+#define AR934X_RESET_DDR				BIT(16)
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT		BIT(15)
+#define AR934X_RESET_NANDF				BIT(14)
+#define AR934X_RESET_GE1_MAC				BIT(13)
+#define AR934X_RESET_ETH_SWITCH_ANALOG			BIT(12)
+#define AR934X_RESET_USB_PHY_ANALOG			BIT(11)
+#define AR934X_RESET_HOST_DMA_INT			BIT(10)
+#define AR934X_RESET_GE0_MAC				BIT(9)
+#define AR934X_RESET_ETH_SWITCH				BIT(8)
+#define AR934X_RESET_PCIE_PHY				BIT(7)
+#define AR934X_RESET_PCIE				BIT(6)
+#define AR934X_RESET_USB_HOST				BIT(5)
+#define AR934X_RESET_USB_PHY				BIT(4)
+#define AR934X_RESET_USBSUS_OVERRIDE			BIT(3)
+#define AR934X_RESET_LUT				BIT(2)
+#define AR934X_RESET_MBOX				BIT(1)
+#define AR934X_RESET_I2S				BIT(0)
+
+#define QCA953X_RESET_USB_EXT_PWR			BIT(29)
+#define QCA953X_RESET_EXTERNAL				BIT(28)
+#define QCA953X_RESET_RTC				BIT(27)
+#define QCA953X_RESET_FULL_CHIP				BIT(24)
+#define QCA953X_RESET_GE1_MDIO				BIT(23)
+#define QCA953X_RESET_GE0_MDIO				BIT(22)
+#define QCA953X_RESET_CPU_NMI				BIT(21)
+#define QCA953X_RESET_CPU_COLD				BIT(20)
+#define QCA953X_RESET_DDR				BIT(16)
+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT		BIT(15)
+#define QCA953X_RESET_GE1_MAC				BIT(13)
+#define QCA953X_RESET_ETH_SWITCH_ANALOG			BIT(12)
+#define QCA953X_RESET_USB_PHY_ANALOG			BIT(11)
+#define QCA953X_RESET_GE0_MAC				BIT(9)
+#define QCA953X_RESET_ETH_SWITCH			BIT(8)
+#define QCA953X_RESET_PCIE_PHY				BIT(7)
+#define QCA953X_RESET_PCIE				BIT(6)
+#define QCA953X_RESET_USB_HOST				BIT(5)
+#define QCA953X_RESET_USB_PHY				BIT(4)
+#define QCA953X_RESET_USBSUS_OVERRIDE			BIT(3)
+
+#define QCA955X_RESET_HOST				BIT(31)
+#define QCA955X_RESET_SLIC				BIT(30)
+#define QCA955X_RESET_HDMA				BIT(29)
+#define QCA955X_RESET_EXTERNAL				BIT(28)
+#define QCA955X_RESET_RTC				BIT(27)
+#define QCA955X_RESET_PCIE_EP_INT			BIT(26)
+#define QCA955X_RESET_CHKSUM_ACC			BIT(25)
+#define QCA955X_RESET_FULL_CHIP				BIT(24)
+#define QCA955X_RESET_GE1_MDIO				BIT(23)
+#define QCA955X_RESET_GE0_MDIO				BIT(22)
+#define QCA955X_RESET_CPU_NMI				BIT(21)
+#define QCA955X_RESET_CPU_COLD				BIT(20)
+#define QCA955X_RESET_HOST_RESET_INT			BIT(19)
+#define QCA955X_RESET_PCIE_EP				BIT(18)
+#define QCA955X_RESET_UART1				BIT(17)
+#define QCA955X_RESET_DDR				BIT(16)
+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT		BIT(15)
+#define QCA955X_RESET_NANDF				BIT(14)
+#define QCA955X_RESET_GE1_MAC				BIT(13)
+#define QCA955X_RESET_SGMII_ANALOG			BIT(12)
+#define QCA955X_RESET_USB_PHY_ANALOG			BIT(11)
+#define QCA955X_RESET_HOST_DMA_INT			BIT(10)
+#define QCA955X_RESET_GE0_MAC				BIT(9)
+#define QCA955X_RESET_SGMII				BIT(8)
+#define QCA955X_RESET_PCIE_PHY				BIT(7)
+#define QCA955X_RESET_PCIE				BIT(6)
+#define QCA955X_RESET_USB_HOST				BIT(5)
+#define QCA955X_RESET_USB_PHY				BIT(4)
+#define QCA955X_RESET_USBSUS_OVERRIDE			BIT(3)
+#define QCA955X_RESET_LUT				BIT(2)
+#define QCA955X_RESET_MBOX				BIT(1)
+#define QCA955X_RESET_I2S				BIT(0)
+
+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN			BIT(18)
+#define AR933X_BOOTSTRAP_DDR2				BIT(13)
+#define AR933X_BOOTSTRAP_EEPBUSY			BIT(4)
+#define AR933X_BOOTSTRAP_REF_CLK_40			BIT(0)
+
+#define AR934X_BOOTSTRAP_SW_OPTION8			BIT(23)
+#define AR934X_BOOTSTRAP_SW_OPTION7			BIT(22)
+#define AR934X_BOOTSTRAP_SW_OPTION6			BIT(21)
+#define AR934X_BOOTSTRAP_SW_OPTION5			BIT(20)
+#define AR934X_BOOTSTRAP_SW_OPTION4			BIT(19)
+#define AR934X_BOOTSTRAP_SW_OPTION3			BIT(18)
+#define AR934X_BOOTSTRAP_SW_OPTION2			BIT(17)
+#define AR934X_BOOTSTRAP_SW_OPTION1			BIT(16)
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE		BIT(7)
+#define AR934X_BOOTSTRAP_PCIE_RC			BIT(6)
+#define AR934X_BOOTSTRAP_EJTAG_MODE			BIT(5)
+#define AR934X_BOOTSTRAP_REF_CLK_40			BIT(4)
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI			BIT(2)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED			BIT(1)
+#define AR934X_BOOTSTRAP_DDR1				BIT(0)
+
+#define QCA953X_BOOTSTRAP_SW_OPTION2			BIT(12)
+#define QCA953X_BOOTSTRAP_SW_OPTION1			BIT(11)
+#define QCA953X_BOOTSTRAP_EJTAG_MODE			BIT(5)
+#define QCA953X_BOOTSTRAP_REF_CLK_40			BIT(4)
+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED		BIT(1)
+#define QCA953X_BOOTSTRAP_DDR1				BIT(0)
+
+#define QCA955X_BOOTSTRAP_REF_CLK_40			BIT(4)
+
+#define QCA956X_BOOTSTRAP_REF_CLK_40			BIT(2)
+
+#define AR934X_PCIE_WMAC_INT_WMAC_MISC			BIT(0)
+#define AR934X_PCIE_WMAC_INT_WMAC_TX			BIT(1)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP			BIT(2)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP			BIT(3)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC			BIT(4)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC0			BIT(5)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC1			BIT(6)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC2			BIT(7)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC3			BIT(8)
+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
+	(AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
+	 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
+	(AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
+	 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+	 AR934X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC			BIT(0)
+#define QCA953X_PCIE_WMAC_INT_WMAC_TX			BIT(1)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP			BIT(2)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP			BIT(3)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC			BIT(4)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0			BIT(5)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1			BIT(6)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2			BIT(7)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3			BIT(8)
+#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
+	(QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
+	 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
+	(QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
+	 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
+	 QCA953X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define QCA955X_EXT_INT_WMAC_MISC			BIT(0)
+#define QCA955X_EXT_INT_WMAC_TX				BIT(1)
+#define QCA955X_EXT_INT_WMAC_RXLP			BIT(2)
+#define QCA955X_EXT_INT_WMAC_RXHP			BIT(3)
+#define QCA955X_EXT_INT_PCIE_RC1			BIT(4)
+#define QCA955X_EXT_INT_PCIE_RC1_INT0			BIT(5)
+#define QCA955X_EXT_INT_PCIE_RC1_INT1			BIT(6)
+#define QCA955X_EXT_INT_PCIE_RC1_INT2			BIT(7)
+#define QCA955X_EXT_INT_PCIE_RC1_INT3			BIT(8)
+#define QCA955X_EXT_INT_PCIE_RC2			BIT(12)
+#define QCA955X_EXT_INT_PCIE_RC2_INT0			BIT(13)
+#define QCA955X_EXT_INT_PCIE_RC2_INT1			BIT(14)
+#define QCA955X_EXT_INT_PCIE_RC2_INT2			BIT(15)
+#define QCA955X_EXT_INT_PCIE_RC2_INT3			BIT(16)
+#define QCA955X_EXT_INT_USB1				BIT(24)
+#define QCA955X_EXT_INT_USB2				BIT(28)
+
+#define QCA955X_EXT_INT_WMAC_ALL \
+	(QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
+	 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
+
+#define QCA955X_EXT_INT_PCIE_RC1_ALL \
+	(QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
+	 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
+	 QCA955X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA955X_EXT_INT_PCIE_RC2_ALL \
+	(QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
+	 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
+	 QCA955X_EXT_INT_PCIE_RC2_INT3)
+
+#define QCA956X_EXT_INT_WMAC_MISC			BIT(0)
+#define QCA956X_EXT_INT_WMAC_TX				BIT(1)
+#define QCA956X_EXT_INT_WMAC_RXLP			BIT(2)
+#define QCA956X_EXT_INT_WMAC_RXHP			BIT(3)
+#define QCA956X_EXT_INT_PCIE_RC1			BIT(4)
+#define QCA956X_EXT_INT_PCIE_RC1_INT0			BIT(5)
+#define QCA956X_EXT_INT_PCIE_RC1_INT1			BIT(6)
+#define QCA956X_EXT_INT_PCIE_RC1_INT2			BIT(7)
+#define QCA956X_EXT_INT_PCIE_RC1_INT3			BIT(8)
+#define QCA956X_EXT_INT_PCIE_RC2			BIT(12)
+#define QCA956X_EXT_INT_PCIE_RC2_INT0			BIT(13)
+#define QCA956X_EXT_INT_PCIE_RC2_INT1			BIT(14)
+#define QCA956X_EXT_INT_PCIE_RC2_INT2			BIT(15)
+#define QCA956X_EXT_INT_PCIE_RC2_INT3			BIT(16)
+#define QCA956X_EXT_INT_USB1				BIT(24)
+#define QCA956X_EXT_INT_USB2				BIT(28)
+
+#define QCA956X_EXT_INT_WMAC_ALL \
+	(QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
+	 QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
+
+#define QCA956X_EXT_INT_PCIE_RC1_ALL \
+	(QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
+	 QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
+	 QCA956X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA956X_EXT_INT_PCIE_RC2_ALL \
+	(QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
+	 QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
+	 QCA956X_EXT_INT_PCIE_RC2_INT3)
+
+#define REV_ID_MAJOR_MASK				0xfff0
+#define REV_ID_MAJOR_AR71XX				0x00a0
+#define REV_ID_MAJOR_AR913X				0x00b0
+#define REV_ID_MAJOR_AR7240				0x00c0
+#define REV_ID_MAJOR_AR7241				0x0100
+#define REV_ID_MAJOR_AR7242				0x1100
+#define REV_ID_MAJOR_AR9330				0x0110
+#define REV_ID_MAJOR_AR9331				0x1110
+#define REV_ID_MAJOR_AR9341				0x0120
+#define REV_ID_MAJOR_AR9342				0x1120
+#define REV_ID_MAJOR_AR9344				0x2120
+#define REV_ID_MAJOR_QCA9533				0x0140
+#define REV_ID_MAJOR_QCA9533_V2				0x0160
+#define REV_ID_MAJOR_QCA9556				0x0130
+#define REV_ID_MAJOR_QCA9558				0x1130
+#define REV_ID_MAJOR_TP9343				0x0150
+#define REV_ID_MAJOR_QCA9561				0x1150
+
+#define AR71XX_REV_ID_MINOR_MASK			0x3
+#define AR71XX_REV_ID_MINOR_AR7130			0x0
+#define AR71XX_REV_ID_MINOR_AR7141			0x1
+#define AR71XX_REV_ID_MINOR_AR7161			0x2
+#define AR913X_REV_ID_MINOR_AR9130			0x0
+#define AR913X_REV_ID_MINOR_AR9132			0x1
+
+#define AR71XX_REV_ID_REVISION_MASK			0x3
+#define AR71XX_REV_ID_REVISION_SHIFT			2
+#define AR71XX_REV_ID_REVISION2_MASK			0xf
+
+/*
+ * RTC block
+ */
+#define AR933X_RTC_REG_RESET				0x40
+#define AR933X_RTC_REG_STATUS				0x44
+#define AR933X_RTC_REG_DERIVED				0x48
+#define AR933X_RTC_REG_FORCE_WAKE			0x4c
+#define AR933X_RTC_REG_INT_CAUSE			0x50
+#define AR933X_RTC_REG_CAUSE_CLR			0x50
+#define AR933X_RTC_REG_INT_ENABLE			0x54
+#define AR933X_RTC_REG_INT_MASKE			0x58
+
+#define QCA953X_RTC_REG_SYNC_RESET			0x40
+#define QCA953X_RTC_REG_SYNC_STATUS			0x44
+
+/*
+ * SPI block
+ */
+#define AR71XX_SPI_REG_FS				0x00
+#define AR71XX_SPI_REG_CTRL				0x04
+#define AR71XX_SPI_REG_IOC				0x08
+#define AR71XX_SPI_REG_RDS				0x0c
+
+#define AR71XX_SPI_FS_GPIO				BIT(0)
+
+#define AR71XX_SPI_CTRL_RD				BIT(6)
+#define AR71XX_SPI_CTRL_DIV_MASK			0x3f
+
+#define AR71XX_SPI_IOC_DO				BIT(0)
+#define AR71XX_SPI_IOC_CLK				BIT(8)
+#define AR71XX_SPI_IOC_CS(n)				BIT(16 + (n))
+#define AR71XX_SPI_IOC_CS0				AR71XX_SPI_IOC_CS(0)
+#define AR71XX_SPI_IOC_CS1				AR71XX_SPI_IOC_CS(1)
+#define AR71XX_SPI_IOC_CS2				AR71XX_SPI_IOC_CS(2)
+#define AR71XX_SPI_IOC_CS_ALL \
+	(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2)
+
+/*
+ * GPIO block
+ */
+#define AR71XX_GPIO_REG_OE				0x00
+#define AR71XX_GPIO_REG_IN				0x04
+#define AR71XX_GPIO_REG_OUT				0x08
+#define AR71XX_GPIO_REG_SET				0x0c
+#define AR71XX_GPIO_REG_CLEAR				0x10
+#define AR71XX_GPIO_REG_INT_MODE			0x14
+#define AR71XX_GPIO_REG_INT_TYPE			0x18
+#define AR71XX_GPIO_REG_INT_POLARITY			0x1c
+#define AR71XX_GPIO_REG_INT_PENDING			0x20
+#define AR71XX_GPIO_REG_INT_ENABLE			0x24
+#define AR71XX_GPIO_REG_FUNC				0x28
+#define AR933X_GPIO_REG_FUNC				0x30
+
+#define AR934X_GPIO_REG_OUT_FUNC0			0x2c
+#define AR934X_GPIO_REG_OUT_FUNC1			0x30
+#define AR934X_GPIO_REG_OUT_FUNC2			0x34
+#define AR934X_GPIO_REG_OUT_FUNC3			0x38
+#define AR934X_GPIO_REG_OUT_FUNC4			0x3c
+#define AR934X_GPIO_REG_OUT_FUNC5			0x40
+#define AR934X_GPIO_REG_FUNC				0x6c
+
+#define QCA953X_GPIO_REG_OUT_FUNC0			0x2c
+#define QCA953X_GPIO_REG_OUT_FUNC1			0x30
+#define QCA953X_GPIO_REG_OUT_FUNC2			0x34
+#define QCA953X_GPIO_REG_OUT_FUNC3			0x38
+#define QCA953X_GPIO_REG_OUT_FUNC4			0x3c
+#define QCA953X_GPIO_REG_IN_ENABLE0			0x44
+#define QCA953X_GPIO_REG_FUNC				0x6c
+
+#define QCA955X_GPIO_REG_OUT_FUNC0			0x2c
+#define QCA955X_GPIO_REG_OUT_FUNC1			0x30
+#define QCA955X_GPIO_REG_OUT_FUNC2			0x34
+#define QCA955X_GPIO_REG_OUT_FUNC3			0x38
+#define QCA955X_GPIO_REG_OUT_FUNC4			0x3c
+#define QCA955X_GPIO_REG_OUT_FUNC5			0x40
+#define QCA955X_GPIO_REG_FUNC				0x6c
+
+#define QCA956X_GPIO_REG_OUT_FUNC0			0x2c
+#define QCA956X_GPIO_REG_OUT_FUNC1			0x30
+#define QCA956X_GPIO_REG_OUT_FUNC2			0x34
+#define QCA956X_GPIO_REG_OUT_FUNC3			0x38
+#define QCA956X_GPIO_REG_OUT_FUNC4			0x3c
+#define QCA956X_GPIO_REG_OUT_FUNC5			0x40
+#define QCA956X_GPIO_REG_IN_ENABLE0			0x44
+#define QCA956X_GPIO_REG_IN_ENABLE3			0x50
+#define QCA956X_GPIO_REG_FUNC				0x6c
+
+#define AR71XX_GPIO_FUNC_STEREO_EN			BIT(17)
+#define AR71XX_GPIO_FUNC_SLIC_EN			BIT(16)
+#define AR71XX_GPIO_FUNC_SPI_CS2_EN			BIT(13)
+#define AR71XX_GPIO_FUNC_SPI_CS1_EN			BIT(12)
+#define AR71XX_GPIO_FUNC_UART_EN			BIT(8)
+#define AR71XX_GPIO_FUNC_USB_OC_EN			BIT(4)
+#define AR71XX_GPIO_FUNC_USB_CLK_EN			BIT(0)
+
+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN			BIT(19)
+#define AR724X_GPIO_FUNC_SPI_EN				BIT(18)
+#define AR724X_GPIO_FUNC_SPI_CS_EN2			BIT(14)
+#define AR724X_GPIO_FUNC_SPI_CS_EN1			BIT(13)
+#define AR724X_GPIO_FUNC_CLK_OBS5_EN			BIT(12)
+#define AR724X_GPIO_FUNC_CLK_OBS4_EN			BIT(11)
+#define AR724X_GPIO_FUNC_CLK_OBS3_EN			BIT(10)
+#define AR724X_GPIO_FUNC_CLK_OBS2_EN			BIT(9)
+#define AR724X_GPIO_FUNC_CLK_OBS1_EN			BIT(8)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN		BIT(7)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN		BIT(6)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN		BIT(5)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN		BIT(4)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN		BIT(3)
+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN		BIT(2)
+#define AR724X_GPIO_FUNC_UART_EN			BIT(1)
+#define AR724X_GPIO_FUNC_JTAG_DISABLE			BIT(0)
+
+#define AR913X_GPIO_FUNC_WMAC_LED_EN			BIT(22)
+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN			BIT(21)
+#define AR913X_GPIO_FUNC_I2S_REFCLKEN			BIT(20)
+#define AR913X_GPIO_FUNC_I2S_MCKEN			BIT(19)
+#define AR913X_GPIO_FUNC_I2S1_EN			BIT(18)
+#define AR913X_GPIO_FUNC_I2S0_EN			BIT(17)
+#define AR913X_GPIO_FUNC_SLIC_EN			BIT(16)
+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN			BIT(9)
+#define AR913X_GPIO_FUNC_UART_EN			BIT(8)
+#define AR913X_GPIO_FUNC_USB_CLK_EN			BIT(4)
+
+#define AR933X_GPIO(x)					BIT(x)
+#define AR933X_GPIO_FUNC_SPDIF2TCK			BIT(31)
+#define AR933X_GPIO_FUNC_SPDIF_EN			BIT(30)
+#define AR933X_GPIO_FUNC_I2SO_22_18_EN			BIT(29)
+#define AR933X_GPIO_FUNC_I2S_MCK_EN			BIT(27)
+#define AR933X_GPIO_FUNC_I2SO_EN			BIT(26)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL		BIT(25)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL		BIT(24)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT		BIT(23)
+#define AR933X_GPIO_FUNC_SPI_EN				BIT(18)
+#define AR933X_GPIO_FUNC_RES_TRUE			BIT(15)
+#define AR933X_GPIO_FUNC_SPI_CS_EN2			BIT(14)
+#define AR933X_GPIO_FUNC_SPI_CS_EN1			BIT(13)
+#define AR933X_GPIO_FUNC_XLNA_EN			BIT(12)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN		BIT(7)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN		BIT(6)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN		BIT(5)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN		BIT(4)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN		BIT(3)
+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN		BIT(2)
+#define AR933X_GPIO_FUNC_UART_EN			BIT(1)
+#define AR933X_GPIO_FUNC_JTAG_DISABLE			BIT(0)
+
+#define AR934X_GPIO_FUNC_CLK_OBS7_EN			BIT(9)
+#define AR934X_GPIO_FUNC_CLK_OBS6_EN			BIT(8)
+#define AR934X_GPIO_FUNC_CLK_OBS5_EN			BIT(7)
+#define AR934X_GPIO_FUNC_CLK_OBS4_EN			BIT(6)
+#define AR934X_GPIO_FUNC_CLK_OBS3_EN			BIT(5)
+#define AR934X_GPIO_FUNC_CLK_OBS2_EN			BIT(4)
+#define AR934X_GPIO_FUNC_CLK_OBS1_EN			BIT(3)
+#define AR934X_GPIO_FUNC_CLK_OBS0_EN			BIT(2)
+#define AR934X_GPIO_FUNC_JTAG_DISABLE			BIT(1)
+
+#define AR934X_GPIO_OUT_GPIO				0
+#define AR934X_GPIO_OUT_SPI_CS1				7
+#define AR934X_GPIO_OUT_LED_LINK0			41
+#define AR934X_GPIO_OUT_LED_LINK1			42
+#define AR934X_GPIO_OUT_LED_LINK2			43
+#define AR934X_GPIO_OUT_LED_LINK3			44
+#define AR934X_GPIO_OUT_LED_LINK4			45
+#define AR934X_GPIO_OUT_EXT_LNA0			46
+#define AR934X_GPIO_OUT_EXT_LNA1			47
+
+#define QCA953X_GPIO(x)					BIT(x)
+#define QCA953X_GPIO_MUX_MASK(x)			(0xff << (x))
+#define QCA953X_GPIO_OUT_MUX_SPI_CS1			10
+#define QCA953X_GPIO_OUT_MUX_SPI_CS2			11
+#define QCA953X_GPIO_OUT_MUX_SPI_CS0			9
+#define QCA953X_GPIO_OUT_MUX_SPI_CLK			8
+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI			12
+#define QCA953X_GPIO_OUT_MUX_UART0_SOUT			22
+#define QCA953X_GPIO_OUT_MUX_LED_LINK1			41
+#define QCA953X_GPIO_OUT_MUX_LED_LINK2			42
+#define QCA953X_GPIO_OUT_MUX_LED_LINK3			43
+#define QCA953X_GPIO_OUT_MUX_LED_LINK4			44
+#define QCA953X_GPIO_OUT_MUX_LED_LINK5			45
+
+#define QCA953X_GPIO_IN_MUX_UART0_SIN			9
+#define QCA953X_GPIO_IN_MUX_SPI_DATA_IN			8
+
+#define QCA956X_GPIO_OUT_MUX_GE0_MDO			32
+#define QCA956X_GPIO_OUT_MUX_GE0_MDC			33
+
+#define AR71XX_GPIO_COUNT				16
+#define AR7240_GPIO_COUNT				18
+#define AR7241_GPIO_COUNT				20
+#define AR913X_GPIO_COUNT				22
+#define AR933X_GPIO_COUNT				30
+#define AR934X_GPIO_COUNT				23
+#define QCA953X_GPIO_COUNT				18
+#define QCA955X_GPIO_COUNT				24
+#define QCA956X_GPIO_COUNT				23
+
+/*
+ * SRIF block
+ */
+#define AR933X_SRIF_DDR_DPLL1_REG			0x240
+#define AR933X_SRIF_DDR_DPLL2_REG			0x244
+#define AR933X_SRIF_DDR_DPLL3_REG			0x248
+#define AR933X_SRIF_DDR_DPLL4_REG			0x24c
+
+#define AR934X_SRIF_CPU_DPLL1_REG			0x1c0
+#define AR934X_SRIF_CPU_DPLL2_REG			0x1c4
+#define AR934X_SRIF_CPU_DPLL3_REG			0x1c8
+#define AR934X_SRIF_CPU_DPLL4_REG			0x1cc
+
+#define AR934X_SRIF_DDR_DPLL1_REG			0x240
+#define AR934X_SRIF_DDR_DPLL2_REG			0x244
+#define AR934X_SRIF_DDR_DPLL3_REG			0x248
+#define AR934X_SRIF_DDR_DPLL4_REG			0x24c
+
+#define AR934X_SRIF_DPLL1_REFDIV_SHIFT			27
+#define AR934X_SRIF_DPLL1_REFDIV_MASK			0x1f
+#define AR934X_SRIF_DPLL1_NINT_SHIFT			18
+#define AR934X_SRIF_DPLL1_NINT_MASK			0x1ff
+#define AR934X_SRIF_DPLL1_NFRAC_MASK			0x0003ffff
+
+#define AR934X_SRIF_DPLL2_LOCAL_PLL			BIT(30)
+#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT			13
+#define AR934X_SRIF_DPLL2_OUTDIV_MASK			0x7
+
+#define QCA953X_SRIF_BB_DPLL1_REG			0x180
+#define QCA953X_SRIF_BB_DPLL2_REG			0x184
+#define QCA953X_SRIF_BB_DPLL3_REG			0x188
+
+#define QCA953X_SRIF_CPU_DPLL1_REG			0x1c0
+#define QCA953X_SRIF_CPU_DPLL2_REG			0x1c4
+#define QCA953X_SRIF_CPU_DPLL3_REG			0x1c8
+
+#define QCA953X_SRIF_DDR_DPLL1_REG			0x240
+#define QCA953X_SRIF_DDR_DPLL2_REG			0x244
+#define QCA953X_SRIF_DDR_DPLL3_REG			0x248
+
+#define QCA953X_SRIF_PCIE_DPLL1_REG			0xc00
+#define QCA953X_SRIF_PCIE_DPLL2_REG			0xc04
+#define QCA953X_SRIF_PCIE_DPLL3_REG			0xc08
+
+#define QCA953X_SRIF_PMU1_REG				0xc40
+#define QCA953X_SRIF_PMU2_REG				0xc44
+
+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT			27
+#define QCA953X_SRIF_DPLL1_REFDIV_MASK			0x1f
+
+#define QCA953X_SRIF_DPLL1_NINT_SHIFT			18
+#define QCA953X_SRIF_DPLL1_NINT_MASK			0x1ff
+#define QCA953X_SRIF_DPLL1_NFRAC_MASK			0x0003ffff
+
+#define QCA953X_SRIF_DPLL2_LOCAL_PLL			BIT(30)
+
+#define QCA953X_SRIF_DPLL2_KI_SHIFT			29
+#define QCA953X_SRIF_DPLL2_KI_MASK			0x3
+
+#define QCA953X_SRIF_DPLL2_KD_SHIFT			25
+#define QCA953X_SRIF_DPLL2_KD_MASK			0xf
+
+#define QCA953X_SRIF_DPLL2_PWD				BIT(22)
+
+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT			13
+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK			0x7
+
+/*
+ * MII_CTRL block
+ */
+#define AR71XX_MII_REG_MII0_CTRL			0x00
+#define AR71XX_MII_REG_MII1_CTRL			0x04
+
+#define AR71XX_MII_CTRL_IF_MASK				3
+#define AR71XX_MII_CTRL_SPEED_SHIFT			4
+#define AR71XX_MII_CTRL_SPEED_MASK			3
+#define AR71XX_MII_CTRL_SPEED_10			0
+#define AR71XX_MII_CTRL_SPEED_100			1
+#define AR71XX_MII_CTRL_SPEED_1000			2
+
+#define AR71XX_MII0_CTRL_IF_GMII			0
+#define AR71XX_MII0_CTRL_IF_MII				1
+#define AR71XX_MII0_CTRL_IF_RGMII			2
+#define AR71XX_MII0_CTRL_IF_RMII			3
+
+#define AR71XX_MII1_CTRL_IF_RGMII			0
+#define AR71XX_MII1_CTRL_IF_RMII			1
+
+/*
+ * AR933X GMAC interface
+ */
+#define AR933X_GMAC_REG_ETH_CFG				0x00
+
+#define AR933X_ETH_CFG_RGMII_GE0			BIT(0)
+#define AR933X_ETH_CFG_MII_GE0				BIT(1)
+#define AR933X_ETH_CFG_GMII_GE0				BIT(2)
+#define AR933X_ETH_CFG_MII_GE0_MASTER			BIT(3)
+#define AR933X_ETH_CFG_MII_GE0_SLAVE			BIT(4)
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN			BIT(5)
+#define AR933X_ETH_CFG_SW_PHY_SWAP			BIT(7)
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP			BIT(8)
+#define AR933X_ETH_CFG_RMII_GE0				BIT(9)
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10			0
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100			BIT(10)
+
+/*
+ * AR934X GMAC Interface
+ */
+#define AR934X_GMAC_REG_ETH_CFG				0x00
+
+#define AR934X_ETH_CFG_RGMII_GMAC0			BIT(0)
+#define AR934X_ETH_CFG_MII_GMAC0			BIT(1)
+#define AR934X_ETH_CFG_GMII_GMAC0			BIT(2)
+#define AR934X_ETH_CFG_MII_GMAC0_MASTER			BIT(3)
+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE			BIT(4)
+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN			BIT(5)
+#define AR934X_ETH_CFG_SW_ONLY_MODE			BIT(6)
+#define AR934X_ETH_CFG_SW_PHY_SWAP			BIT(7)
+#define AR934X_ETH_CFG_SW_APB_ACCESS			BIT(9)
+#define AR934X_ETH_CFG_RMII_GMAC0			BIT(10)
+#define AR933X_ETH_CFG_MII_CNTL_SPEED			BIT(11)
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER			BIT(12)
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST			BIT(13)
+#define AR934X_ETH_CFG_RXD_DELAY			BIT(14)
+#define AR934X_ETH_CFG_RXD_DELAY_MASK			0x3
+#define AR934X_ETH_CFG_RXD_DELAY_SHIFT			14
+#define AR934X_ETH_CFG_RDV_DELAY			BIT(16)
+#define AR934X_ETH_CFG_RDV_DELAY_MASK			0x3
+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT			16
+
+/*
+ * QCA953X GMAC Interface
+ */
+#define QCA953X_GMAC_REG_ETH_CFG			0x00
+
+#define QCA953X_ETH_CFG_SW_ONLY_MODE			BIT(6)
+#define QCA953X_ETH_CFG_SW_PHY_SWAP			BIT(7)
+#define QCA953X_ETH_CFG_SW_APB_ACCESS			BIT(9)
+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST		BIT(13)
+
+/*
+ * QCA955X GMAC Interface
+ */
+
+#define QCA955X_GMAC_REG_ETH_CFG			0x00
+
+#define QCA955X_ETH_CFG_RGMII_EN			BIT(0)
+#define QCA955X_ETH_CFG_GE0_SGMII			BIT(6)
+
+#endif /* __ASM_AR71XX_H */
diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h
new file mode 100644
index 0000000..17af082
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/ath79.h
@@ -0,0 +1,149 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X common definitions
+ *
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_ATH79_H
+#define __ASM_MACH_ATH79_H
+
+#include <linux/types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ath79_soc_type {
+	ATH79_SOC_UNKNOWN,
+	ATH79_SOC_AR7130,
+	ATH79_SOC_AR7141,
+	ATH79_SOC_AR7161,
+	ATH79_SOC_AR7240,
+	ATH79_SOC_AR7241,
+	ATH79_SOC_AR7242,
+	ATH79_SOC_AR9130,
+	ATH79_SOC_AR9132,
+	ATH79_SOC_AR9330,
+	ATH79_SOC_AR9331,
+	ATH79_SOC_AR9341,
+	ATH79_SOC_AR9342,
+	ATH79_SOC_AR9344,
+	ATH79_SOC_QCA9533,
+	ATH79_SOC_QCA9556,
+	ATH79_SOC_QCA9558,
+	ATH79_SOC_TP9343,
+	ATH79_SOC_QCA9561,
+};
+
+static inline int soc_is_ar71xx(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7130 ||
+		gd->arch.soc == ATH79_SOC_AR7141 ||
+		gd->arch.soc == ATH79_SOC_AR7161;
+}
+
+static inline int soc_is_ar724x(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7240 ||
+		gd->arch.soc == ATH79_SOC_AR7241 ||
+		gd->arch.soc == ATH79_SOC_AR7242;
+}
+
+static inline int soc_is_ar7240(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7240;
+}
+
+static inline int soc_is_ar7241(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7241;
+}
+
+static inline int soc_is_ar7242(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7242;
+}
+
+static inline int soc_is_ar913x(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9130 ||
+		gd->arch.soc == ATH79_SOC_AR9132;
+}
+
+static inline int soc_is_ar933x(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9330 ||
+		gd->arch.soc == ATH79_SOC_AR9331;
+}
+
+static inline int soc_is_ar9341(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9341;
+}
+
+static inline int soc_is_ar9342(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9342;
+}
+
+static inline int soc_is_ar9344(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9344;
+}
+
+static inline int soc_is_ar934x(void)
+{
+	return soc_is_ar9341() ||
+		soc_is_ar9342() ||
+		soc_is_ar9344();
+}
+
+static inline int soc_is_qca9533(void)
+{
+	return gd->arch.soc == ATH79_SOC_QCA9533;
+}
+
+static inline int soc_is_qca953x(void)
+{
+	return soc_is_qca9533();
+}
+
+static inline int soc_is_qca9556(void)
+{
+	return gd->arch.soc == ATH79_SOC_QCA9556;
+}
+
+static inline int soc_is_qca9558(void)
+{
+	return gd->arch.soc == ATH79_SOC_QCA9558;
+}
+
+static inline int soc_is_qca955x(void)
+{
+	return soc_is_qca9556() || soc_is_qca9558();
+}
+
+static inline int soc_is_tp9343(void)
+{
+	return gd->arch.soc == ATH79_SOC_TP9343;
+}
+
+static inline int soc_is_qca9561(void)
+{
+	return gd->arch.soc == ATH79_SOC_QCA9561;
+}
+
+static inline int soc_is_qca956x(void)
+{
+	return soc_is_tp9343() || soc_is_qca9561();
+}
+
+int ath79_eth_reset(void);
+int ath79_usb_reset(void);
+
+void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz);
+void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz);
+
+#endif /* __ASM_MACH_ATH79_H */
diff --git a/arch/mips/mach-ath79/include/mach/ddr.h b/arch/mips/mach-ath79/include/mach/ddr.h
new file mode 100644
index 0000000..181179a
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/ddr.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_DDR_H
+#define __ASM_MACH_DDR_H
+
+void ddr_init(void);
+void ddr_tap_tuning(void);
+
+#endif /* __ASM_MACH_DDR_H */
diff --git a/arch/mips/mach-ath79/include/mach/reset.h b/arch/mips/mach-ath79/include/mach/reset.h
new file mode 100644
index 0000000..c383bfe
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/reset.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_RESET_H
+#define __ASM_MACH_RESET_H
+
+#include <linux/types.h>
+
+u32 get_bootstrap(void);
+
+#endif /* __ASM_MACH_RESET_H */
diff --git a/arch/mips/mach-ath79/qca953x/Makefile b/arch/mips/mach-ath79/qca953x/Makefile
new file mode 100644
index 0000000..fd74f0c
--- /dev/null
+++ b/arch/mips/mach-ath79/qca953x/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += clk.o
+obj-y += ddr.o
+obj-y += lowlevel_init.o
diff --git a/arch/mips/mach-ath79/qca953x/clk.c b/arch/mips/mach-ath79/qca953x/clk.c
new file mode 100644
index 0000000..ef0a28e
--- /dev/null
+++ b/arch/mips/mach-ath79/qca953x/clk.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 qca953x_get_xtal(void)
+{
+	u32 val;
+
+	val = get_bootstrap();
+	if (val & QCA953X_BOOTSTRAP_REF_CLK_40)
+		return 40000000;
+	else
+		return 25000000;
+}
+
+int get_serial_clock(void)
+{
+	return qca953x_get_xtal();
+}
+
+int get_clocks(void)
+{
+	void __iomem *regs;
+	u32 val, ctrl, xtal, pll, div;
+
+	regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+			   MAP_NOCACHE);
+
+	xtal = qca953x_get_xtal();
+	ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG);
+	val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG);
+
+	/* VCOOUT = XTAL * DIV_INT */
+	div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT)
+			& QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
+	pll = xtal / div;
+
+	/* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+	div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT)
+			& QCA953X_PLL_CPU_CONFIG_NINT_MASK;
+	pll *= div;
+	div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
+			& QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
+	if (!div)
+		div = 1;
+	pll >>= div;
+
+	/* CPU_CLK = PLLOUT / CPU_POST_DIV */
+	div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
+			& QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
+	gd->cpu_clk = pll / div;
+
+
+	val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG);
+	/* VCOOUT = XTAL * DIV_INT */
+	div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT)
+			& QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
+	pll = xtal / div;
+
+	/* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+	div = (val >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT)
+			& QCA953X_PLL_DDR_CONFIG_NINT_MASK;
+	pll *= div;
+	div = (val >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT)
+			& QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
+	if (!div)
+		div = 1;
+	pll >>= div;
+
+	/* DDR_CLK = PLLOUT / DDR_POST_DIV */
+	div = ((ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
+			& QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
+	gd->mem_clk = pll / div;
+
+	div = ((ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
+			& QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
+	if (ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) {
+		/* AHB_CLK = DDR_CLK / AHB_POST_DIV */
+		gd->bus_clk = gd->mem_clk / (div + 1);
+	} else {
+		/* AHB_CLK = CPU_CLK / AHB_POST_DIV */
+		gd->bus_clk = gd->cpu_clk / (div + 1);
+	}
+
+	return 0;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+	if (!gd->bus_clk)
+		get_clocks();
+	return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+	if (!gd->mem_clk)
+		get_clocks();
+	return gd->mem_clk;
+}
diff --git a/arch/mips/mach-ath79/qca953x/ddr.c b/arch/mips/mach-ath79/qca953x/ddr.c
new file mode 100644
index 0000000..ac0130c
--- /dev/null
+++ b/arch/mips/mach-ath79/qca953x/ddr.c
@@ -0,0 +1,472 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Based on Atheros LSDK/QSDK
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_CTRL_UPD_EMR3S      BIT(5)
+#define DDR_CTRL_UPD_EMR2S      BIT(4)
+#define DDR_CTRL_PRECHARGE      BIT(3)
+#define DDR_CTRL_AUTO_REFRESH   BIT(2)
+#define DDR_CTRL_UPD_EMRS       BIT(1)
+#define DDR_CTRL_UPD_MRS        BIT(0)
+
+#define DDR_REFRESH_EN          BIT(14)
+#define DDR_REFRESH_M           0x3ff
+#define DDR_REFRESH(x)          ((x) & DDR_REFRESH_M)
+#define DDR_REFRESH_VAL         (DDR_REFRESH_EN | DDR_REFRESH(312))
+
+#define DDR_TRAS_S              0
+#define DDR_TRAS_M              0x1f
+#define DDR_TRAS(x)             (((x) & DDR_TRAS_M) << DDR_TRAS_S)
+#define DDR_TRCD_M              0xf
+#define DDR_TRCD_S              5
+#define DDR_TRCD(x)             (((x) & DDR_TRCD_M) << DDR_TRCD_S)
+#define DDR_TRP_M               0xf
+#define DDR_TRP_S               9
+#define DDR_TRP(x)              (((x) & DDR_TRP_M) << DDR_TRP_S)
+#define DDR_TRRD_M              0xf
+#define DDR_TRRD_S              13
+#define DDR_TRRD(x)             (((x) & DDR_TRRD_M) << DDR_TRRD_S)
+#define DDR_TRFC_M              0x7f
+#define DDR_TRFC_S              17
+#define DDR_TRFC(x)             (((x) & DDR_TRFC_M) << DDR_TRFC_S)
+#define DDR_TMRD_M              0xf
+#define DDR_TMRD_S              23
+#define DDR_TMRD(x)             (((x) & DDR_TMRD_M) << DDR_TMRD_S)
+#define DDR_CAS_L_M             0x17
+#define DDR_CAS_L_S             27
+#define DDR_CAS_L(x)            (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
+#define DDR_OPEN                BIT(30)
+#define DDR1_CONF_REG_VAL       (DDR_TRAS(16) | DDR_TRCD(6) | \
+				 DDR_TRP(6) | DDR_TRRD(4) | \
+				 DDR_TRFC(7) | DDR_TMRD(5) | \
+				 DDR_CAS_L(7) | DDR_OPEN)
+#define DDR2_CONF_REG_VAL       (DDR_TRAS(27) | DDR_TRCD(9) | \
+				 DDR_TRP(9) | DDR_TRRD(7) | \
+				 DDR_TRFC(21) | DDR_TMRD(15) | \
+				 DDR_CAS_L(17) | DDR_OPEN)
+
+#define DDR_BURST_LEN_S         0
+#define DDR_BURST_LEN_M         0xf
+#define DDR_BURST_LEN(x)        ((x) << DDR_BURST_LEN_S)
+#define DDR_BURST_TYPE          BIT(4)
+#define DDR_CNTL_OE_EN          BIT(5)
+#define DDR_PHASE_SEL           BIT(6)
+#define DDR_CKE                 BIT(7)
+#define DDR_TWR_S               8
+#define DDR_TWR_M               0xf
+#define DDR_TWR(x)              (((x) & DDR_TWR_M) << DDR_TWR_S)
+#define DDR_TRTW_S              12
+#define DDR_TRTW_M              0x1f
+#define DDR_TRTW(x)             (((x) & DDR_TRTW_M) << DDR_TRTW_S)
+#define DDR_TRTP_S              17
+#define DDR_TRTP_M              0xf
+#define DDR_TRTP(x)             (((x) & DDR_TRTP_M) << DDR_TRTP_S)
+#define DDR_TWTR_S              21
+#define DDR_TWTR_M              0x1f
+#define DDR_TWTR(x)             (((x) & DDR_TWTR_M) << DDR_TWTR_S)
+#define DDR_G_OPEN_L_S          26
+#define DDR_G_OPEN_L_M          0xf
+#define DDR_G_OPEN_L(x)         ((x) << DDR_G_OPEN_L_S)
+#define DDR_HALF_WIDTH_LOW      BIT(31)
+#define DDR1_CONF2_REG_VAL      (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
+				 DDR_CKE | DDR_TWR(13) | DDR_TRTW(14) | \
+				 DDR_TRTP(8) | DDR_TWTR(14) | \
+				 DDR_G_OPEN_L(6) | DDR_HALF_WIDTH_LOW)
+#define DDR2_CONF2_REG_VAL      (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
+				 DDR_CKE | DDR_TWR(1) | DDR_TRTW(14) | \
+				 DDR_TRTP(9) | DDR_TWTR(21) | \
+				 DDR_G_OPEN_L(8) | DDR_HALF_WIDTH_LOW)
+
+#define DDR_TWR_MSB             BIT(3)
+#define DDR_TRAS_MSB            BIT(2)
+#define DDR_TRFC_MSB_M          0x3
+#define DDR_TRFC_MSB(x)         (x)
+#define DDR1_CONF3_REG_VAL      0
+#define DDR2_CONF3_REG_VAL      (DDR_TWR_MSB | DDR_TRFC_MSB(2))
+
+#define DDR_CTL_SRAM_TSEL       BIT(30)
+#define DDR_CTL_SRAM_GE0_SYNC   BIT(20)
+#define DDR_CTL_SRAM_GE1_SYNC   BIT(19)
+#define DDR_CTL_SRAM_USB_SYNC   BIT(18)
+#define DDR_CTL_SRAM_PCIE_SYNC  BIT(17)
+#define DDR_CTL_SRAM_WMAC_SYNC  BIT(16)
+#define DDR_CTL_SRAM_MISC1_SYNC BIT(15)
+#define DDR_CTL_SRAM_MISC2_SYNC BIT(14)
+#define DDR_CTL_PAD_DDR2_SEL    BIT(6)
+#define DDR_CTL_HALF_WIDTH      BIT(1)
+#define DDR_CTL_CONFIG_VAL      (DDR_CTL_SRAM_TSEL | \
+				 DDR_CTL_SRAM_GE0_SYNC | \
+				 DDR_CTL_SRAM_GE1_SYNC | \
+				 DDR_CTL_SRAM_USB_SYNC | \
+				 DDR_CTL_SRAM_PCIE_SYNC | \
+				 DDR_CTL_SRAM_WMAC_SYNC | \
+				 DDR_CTL_HALF_WIDTH)
+
+#define DDR_BURST_GE0_MAX_BL_S  0
+#define DDR_BURST_GE0_MAX_BL_M  0xf
+#define DDR_BURST_GE0_MAX_BL(x) \
+	(((x) & DDR_BURST_GE0_MAX_BL_M) << DDR_BURST_GE0_MAX_BL_S)
+#define DDR_BURST_GE1_MAX_BL_S  4
+#define DDR_BURST_GE1_MAX_BL_M  0xf
+#define DDR_BURST_GE1_MAX_BL(x) \
+	(((x) & DDR_BURST_GE1_MAX_BL_M) << DDR_BURST_GE1_MAX_BL_S)
+#define DDR_BURST_PCIE_MAX_BL_S 8
+#define DDR_BURST_PCIE_MAX_BL_M 0xf
+#define DDR_BURST_PCIE_MAX_BL(x) \
+	(((x) & DDR_BURST_PCIE_MAX_BL_M) << DDR_BURST_PCIE_MAX_BL_S)
+#define DDR_BURST_USB_MAX_BL_S  12
+#define DDR_BURST_USB_MAX_BL_M  0xf
+#define DDR_BURST_USB_MAX_BL(x) \
+	(((x) & DDR_BURST_USB_MAX_BL_M) << DDR_BURST_USB_MAX_BL_S)
+#define DDR_BURST_CPU_MAX_BL_S  16
+#define DDR_BURST_CPU_MAX_BL_M  0xf
+#define DDR_BURST_CPU_MAX_BL(x) \
+	(((x) & DDR_BURST_CPU_MAX_BL_M) << DDR_BURST_CPU_MAX_BL_S)
+#define DDR_BURST_RD_MAX_BL_S   20
+#define DDR_BURST_RD_MAX_BL_M   0xf
+#define DDR_BURST_RD_MAX_BL(x) \
+	(((x) & DDR_BURST_RD_MAX_BL_M) << DDR_BURST_RD_MAX_BL_S)
+#define DDR_BURST_WR_MAX_BL_S   24
+#define DDR_BURST_WR_MAX_BL_M   0xf
+#define DDR_BURST_WR_MAX_BL(x) \
+	(((x) & DDR_BURST_WR_MAX_BL_M) << DDR_BURST_WR_MAX_BL_S)
+#define DDR_BURST_RWP_MASK_EN_S 28
+#define DDR_BURST_RWP_MASK_EN_M 0x3
+#define DDR_BURST_RWP_MASK_EN(x) \
+	(((x) & DDR_BURST_RWP_MASK_EN_M) << DDR_BURST_RWP_MASK_EN_S)
+#define DDR_BURST_CPU_PRI_BE    BIT(30)
+#define DDR_BURST_CPU_PRI       BIT(31)
+#define DDR_BURST_VAL           (DDR_BURST_CPU_PRI_BE | \
+				 DDR_BURST_RWP_MASK_EN(3) | \
+				 DDR_BURST_WR_MAX_BL(4) | \
+				 DDR_BURST_RD_MAX_BL(4) | \
+				 DDR_BURST_CPU_MAX_BL(4) | \
+				 DDR_BURST_USB_MAX_BL(4) | \
+				 DDR_BURST_PCIE_MAX_BL(4) | \
+				 DDR_BURST_GE1_MAX_BL(4) | \
+				 DDR_BURST_GE0_MAX_BL(4))
+
+#define DDR_BURST_WMAC_MAX_BL_S 0
+#define DDR_BURST_WMAC_MAX_BL_M 0xf
+#define DDR_BURST_WMAC_MAX_BL(x) \
+	(((x) & DDR_BURST_WMAC_MAX_BL_M) << DDR_BURST_WMAC_MAX_BL_S)
+#define DDR_BURST2_VAL          DDR_BURST_WMAC_MAX_BL(4)
+
+#define DDR2_CONF_TWL_S         10
+#define DDR2_CONF_TWL_M         0xf
+#define DDR2_CONF_TWL(x) \
+	(((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
+#define DDR2_CONF_ODT           BIT(9)
+#define DDR2_CONF_TFAW_S        2
+#define DDR2_CONF_TFAW_M        0x3f
+#define DDR2_CONF_TFAW(x) \
+	(((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
+#define DDR2_CONF_EN            BIT(0)
+#define DDR2_CONF_VAL           (DDR2_CONF_TWL(5) | \
+				 DDR2_CONF_TFAW(31) | \
+				 DDR2_CONF_ODT | \
+				 DDR2_CONF_EN)
+
+#define DDR1_EXT_MODE_VAL       0
+#define DDR2_EXT_MODE_VAL       0x402
+#define DDR2_EXT_MODE_OCD_VAL   0x782
+#define DDR1_MODE_DLL_VAL       0x133
+#define DDR2_MODE_DLL_VAL       0x143
+#define DDR1_MODE_VAL           0x33
+#define DDR2_MODE_VAL           0x43
+#define DDR1_TAP_VAL            0x20
+#define DDR2_TAP_VAL            0x10
+
+#define DDR_REG_BIST_MASK_ADDR_0        0x2c
+#define DDR_REG_BIST_MASK_ADDR_1        0x30
+#define DDR_REG_BIST_MASK_AHB_GE0_0     0x34
+#define DDR_REG_BIST_COMP_AHB_GE0_0     0x38
+#define DDR_REG_BIST_MASK_AHB_GE1_0     0x3c
+#define DDR_REG_BIST_COMP_AHB_GE1_0     0x40
+#define DDR_REG_BIST_COMP_ADDR_0        0x64
+#define DDR_REG_BIST_COMP_ADDR_1        0x68
+#define DDR_REG_BIST_MASK_AHB_GE0_1     0x6c
+#define DDR_REG_BIST_COMP_AHB_GE0_1     0x70
+#define DDR_REG_BIST_MASK_AHB_GE1_1     0x74
+#define DDR_REG_BIST_COMP_AHB_GE1_1     0x78
+#define DDR_REG_BIST                    0x11c
+#define DDR_REG_BIST_STATUS             0x120
+
+#define DDR_BIST_COMP_CNT_S     1
+#define DDR_BIST_COMP_CNT_M     0xff
+#define DDR_BIST_COMP_CNT(x) \
+	(((x) & DDR_BIST_COMP_CNT_M) << DDR_BIST_COMP_CNT_S)
+#define DDR_BIST_COMP_CNT_MASK \
+	(DDR_BIST_COMP_CNT_M << DDR_BIST_COMP_CNT_S)
+#define DDR_BIST_TEST_START     BIT(0)
+#define DDR_BIST_STATUS_DONE    BIT(0)
+
+/* 4 Row Address Bits, 4 Column Address Bits, 2 BA bits */
+#define DDR_BIST_MASK_ADDR_VAL  0xfa5de83f
+
+#define DDR_TAP_MAGIC_VAL       0xaa55aa55
+#define DDR_TAP_MAX_VAL         0x40
+
+void ddr_init(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			   MAP_NOCACHE);
+	val = get_bootstrap();
+	if (val & QCA953X_BOOTSTRAP_DDR1) {
+		writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
+		udelay(10);
+
+		/* For 16-bit DDR */
+		writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
+		udelay(100);
+
+		/* Burst size */
+		writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
+		udelay(100);
+		writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
+		udelay(100);
+
+		/* AHB maximum timeout */
+		writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
+		udelay(100);
+
+		/* DRAM timing */
+		writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+		udelay(100);
+		writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+		udelay(100);
+		writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
+		udelay(100);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* ODT disable, Full strength, Enable DLL */
+		writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+		udelay(100);
+
+		/* Update Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Reset DLL, CAS Latency 3, Burst Length 8 */
+		writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+		udelay(100);
+
+		/* Update Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Auto Refresh */
+		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Normal DLL, CAS Latency 3, Burst Length 8 */
+		writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+		udelay(100);
+
+		/* Update Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Refresh time control */
+		writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
+		udelay(100);
+
+		/* DQS 0 Tap Control */
+		writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
+
+		/* DQS 1 Tap Control */
+		writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
+	} else {
+		writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(10);
+		writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(10);
+		writel(DDR_CTL_CONFIG_VAL | DDR_CTL_PAD_DDR2_SEL,
+		       regs + QCA953X_DDR_REG_CTL_CONF);
+		udelay(10);
+
+		/* For 16-bit DDR */
+		writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
+		udelay(100);
+
+		/* Burst size */
+		writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
+		udelay(100);
+		writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
+		udelay(100);
+
+		/* AHB maximum timeout */
+		writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
+		udelay(100);
+
+		/* DRAM timing */
+		writel(DDR2_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+		udelay(100);
+		writel(DDR2_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+		udelay(100);
+		writel(DDR2_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
+		udelay(100);
+
+		/* Enable DDR2 */
+		writel(DDR2_CONF_VAL, regs + QCA953X_DDR_REG_DDR2_CONFIG);
+		udelay(100);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Update Extended Mode Register 2 Set (EMR2S) */
+		writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Update Extended Mode Register 3 Set (EMR3S) */
+		writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* 150 ohm, Reduced strength, Enable DLL */
+		writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+		udelay(100);
+
+		/* Update Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Reset DLL, CAS Latency 4, Burst Length 8 */
+		writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+		udelay(100);
+
+		/* Update Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Auto Refresh */
+		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Normal DLL, CAS Latency 4, Burst Length 8 */
+		writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+		udelay(100);
+
+		/* Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Enable OCD, Enable DLL, Reduced Drive Strength */
+		writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
+		udelay(100);
+
+		/* Update Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* OCD diable, Enable DLL, Reduced Drive Strength */
+		writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+		udelay(100);
+
+		/* Update Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Refresh time control */
+		writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
+		udelay(100);
+
+		/* DQS 0 Tap Control */
+		writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
+
+		/* DQS 1 Tap Control */
+		writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
+	}
+}
+
+void ddr_tap_tuning(void)
+{
+	void __iomem *regs;
+	u32 val, pass, tap, cnt, tap_val, last, first;
+
+	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			   MAP_NOCACHE);
+
+	tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
+	first = DDR_TAP_MAGIC_VAL;
+	last = 0;
+	cnt = 0;
+	tap = 0;
+
+	do {
+		writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL0);
+		writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+		writel(DDR_BIST_COMP_CNT(8), regs + DDR_REG_BIST_COMP_ADDR_1);
+		writel(DDR_BIST_MASK_ADDR_VAL, regs + DDR_REG_BIST_MASK_ADDR_0);
+		writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_1);
+		writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_0);
+		writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_1);
+		writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_0);
+		writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_1);
+		writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_0);
+		writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_1);
+		writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_0);
+
+		/* Start BIST test */
+		writel(DDR_BIST_TEST_START, regs + DDR_REG_BIST);
+
+		do {
+			val = readl(regs + DDR_REG_BIST_STATUS);
+		} while (!(val & DDR_BIST_STATUS_DONE));
+
+		/* Stop BIST test */
+		writel(0, regs + DDR_REG_BIST);
+
+		pass = val & DDR_BIST_COMP_CNT_MASK;
+		pass ^= DDR_BIST_COMP_CNT(8);
+		if (!pass) {
+			if (first != DDR_TAP_MAGIC_VAL) {
+				last = tap;
+			} else  {
+				first = tap;
+				last = tap;
+			}
+			cnt++;
+		}
+		tap++;
+	} while (tap < DDR_TAP_MAX_VAL);
+
+	if (cnt) {
+		tap_val = (first + last) / 2;
+		tap_val %= DDR_TAP_MAX_VAL;
+	}
+
+	writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+	writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+}
diff --git a/arch/mips/mach-ath79/qca953x/lowlevel_init.S b/arch/mips/mach-ath79/qca953x/lowlevel_init.S
new file mode 100644
index 0000000..d7038fa
--- /dev/null
+++ b/arch/mips/mach-ath79/qca953x/lowlevel_init.S
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Based on Atheros LSDK/QSDK
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <mach/ar71xx_regs.h>
+
+#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
+     (((0x3F & divint) << 10) | \
+     ((0x1F & refdiv) << 16) | \
+     ((0x1 & range)   << 21) | \
+     ((0x7 & outdiv)  << 23) )
+
+#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
+    (((0x3 & (cpudiv - 1)) << 5)  | \
+    ((0x3 & (ddrdiv - 1)) << 10) | \
+    ((0x3 & (ahbdiv - 1)) << 15) )
+
+#define SET_FIELD(name, v)      (((v) & QCA953X_##name##_MASK) << \
+				 QCA953X_##name##_SHIFT)
+
+#define DPLL2_KI(v)             SET_FIELD(SRIF_DPLL2_KI, v)
+#define DPLL2_KD(v)             SET_FIELD(SRIF_DPLL2_KD, v)
+#define DPLL2_PWD               QCA953X_SRIF_DPLL2_PWD
+#define MK_DPLL2(ki, kd)        (DPLL2_KI(ki) | DPLL2_KD(kd) | DPLL2_PWD)
+
+#define PLL_CPU_NFRAC(v)        SET_FIELD(PLL_CPU_CONFIG_NFRAC, v)
+#define PLL_CPU_NINT(v)         SET_FIELD(PLL_CPU_CONFIG_NINT, v)
+#define PLL_CPU_REFDIV(v)       SET_FIELD(PLL_CPU_CONFIG_REFDIV, v)
+#define PLL_CPU_OUTDIV(v)       SET_FIELD(PLL_CPU_CONFIG_OUTDIV, v)
+#define MK_PLL_CPU_CONF(frac, nint, ref, outdiv) \
+				(PLL_CPU_NFRAC(frac) | \
+				 PLL_CPU_NINT(nint) | \
+				 PLL_CPU_REFDIV(ref) | \
+				 PLL_CPU_OUTDIV(outdiv))
+
+#define PLL_DDR_NFRAC(v)        SET_FIELD(PLL_DDR_CONFIG_NFRAC, v)
+#define PLL_DDR_NINT(v)         SET_FIELD(PLL_DDR_CONFIG_NINT, v)
+#define PLL_DDR_REFDIV(v)       SET_FIELD(PLL_DDR_CONFIG_REFDIV, v)
+#define PLL_DDR_OUTDIV(v)       SET_FIELD(PLL_DDR_CONFIG_OUTDIV, v)
+#define MK_PLL_DDR_CONF(frac, nint, ref, outdiv) \
+				(PLL_DDR_NFRAC(frac) | \
+				 PLL_DDR_REFDIV(ref) | \
+				 PLL_DDR_NINT(nint) | \
+				 PLL_DDR_OUTDIV(outdiv) | \
+				 QCA953X_PLL_CONFIG_PWD)
+
+#define PLL_CPU_CONF_VAL        MK_PLL_CPU_CONF(0, 26, 1, 0)
+#define PLL_DDR_CONF_VAL        MK_PLL_DDR_CONF(0, 15, 1, 0)
+
+#define PLL_CLK_CTRL_PLL_BYPASS (QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS | \
+				 QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS | \
+				 QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
+
+#define PLL_CLK_CTRL_CPU_DIV(v) SET_FIELD(PLL_CLK_CTRL_CPU_POST_DIV, v)
+#define PLL_CLK_CTRL_DDR_DIV(v) SET_FIELD(PLL_CLK_CTRL_DDR_POST_DIV, v)
+#define PLL_CLK_CTRL_AHB_DIV(v) SET_FIELD(PLL_CLK_CTRL_AHB_POST_DIV, v)
+#define MK_PLL_CLK_CTRL(cpu, ddr, ahb) \
+				(PLL_CLK_CTRL_CPU_DIV(cpu) | \
+				 PLL_CLK_CTRL_DDR_DIV(ddr) | \
+				 PLL_CLK_CTRL_AHB_DIV(ahb))
+#define PLL_CLK_CTRL_VAL    (MK_PLL_CLK_CTRL(0, 0, 2) | \
+			     PLL_CLK_CTRL_PLL_BYPASS | \
+			     QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL | \
+			     QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
+
+#define PLL_DDR_DIT_FRAC_MAX(v)     SET_FIELD(PLL_DDR_DIT_FRAC_MAX, v)
+#define PLL_DDR_DIT_FRAC_MIN(v)     SET_FIELD(PLL_DDR_DIT_FRAC_MIN, v)
+#define PLL_DDR_DIT_FRAC_STEP(v)    SET_FIELD(PLL_DDR_DIT_FRAC_STEP, v)
+#define PLL_DDR_DIT_UPD_CNT(v)      SET_FIELD(PLL_DDR_DIT_UPD_CNT, v)
+#define PLL_CPU_DIT_FRAC_MAX(v)     SET_FIELD(PLL_CPU_DIT_FRAC_MAX, v)
+#define PLL_CPU_DIT_FRAC_MIN(v)     SET_FIELD(PLL_CPU_DIT_FRAC_MIN, v)
+#define PLL_CPU_DIT_FRAC_STEP(v)    SET_FIELD(PLL_CPU_DIT_FRAC_STEP, v)
+#define PLL_CPU_DIT_UPD_CNT(v)      SET_FIELD(PLL_CPU_DIT_UPD_CNT, v)
+#define MK_PLL_DDR_DIT_FRAC(max, min, step, cnt) \
+				(QCA953X_PLL_DIT_FRAC_EN | \
+				 PLL_DDR_DIT_FRAC_MAX(max) | \
+				 PLL_DDR_DIT_FRAC_MIN(min) | \
+				 PLL_DDR_DIT_FRAC_STEP(step) | \
+				 PLL_DDR_DIT_UPD_CNT(cnt))
+#define MK_PLL_CPU_DIT_FRAC(max, min, step, cnt) \
+				(QCA953X_PLL_DIT_FRAC_EN | \
+				 PLL_CPU_DIT_FRAC_MAX(max) | \
+				 PLL_CPU_DIT_FRAC_MIN(min) | \
+				 PLL_CPU_DIT_FRAC_STEP(step) | \
+				 PLL_CPU_DIT_UPD_CNT(cnt))
+#define PLL_CPU_DIT_FRAC_VAL    MK_PLL_CPU_DIT_FRAC(63, 0, 1, 15)
+#define PLL_DDR_DIT_FRAC_VAL    MK_PLL_DDR_DIT_FRAC(763, 635, 1, 15)
+
+    .text
+    .set noreorder
+
+LEAF(lowlevel_init)
+	/* RTC Reset */
+	li      t0, CKSEG1ADDR(AR71XX_RESET_BASE)
+	lw      t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+	li      t2, 0x08000000
+	or      t1, t1, t2
+	sw      t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+	nop
+	lw      t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+	li      t2, 0xf7ffffff
+	and     t1, t1, t2
+	sw      t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+	nop
+
+	/* RTC Force Wake */
+	li      t0, CKSEG1ADDR(QCA953X_RTC_BASE)
+	li      t1, 0x01
+	sw      t1, QCA953X_RTC_REG_SYNC_RESET(t0)
+	nop
+	nop
+
+	/* Wait for RTC in on state */
+1:
+	lw      t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
+	andi    t1, t1, 0x02
+	beqz    t1, 1b
+	nop
+
+	li      t0, CKSEG1ADDR(QCA953X_SRIF_BASE)
+	li      t1, MK_DPLL2(2, 16)
+	sw      t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
+	sw      t1, QCA953X_SRIF_PCIE_DPLL2_REG(t0)
+	sw      t1, QCA953X_SRIF_DDR_DPLL2_REG(t0)
+	sw      t1, QCA953X_SRIF_CPU_DPLL2_REG(t0)
+
+	li      t0, CKSEG1ADDR(AR71XX_PLL_BASE)
+	lw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+	ori     t1, PLL_CLK_CTRL_PLL_BYPASS
+	sw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+	nop
+
+	li      t1, PLL_CPU_CONF_VAL
+	sw      t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
+	nop
+
+	li      t1, PLL_DDR_CONF_VAL
+	sw      t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
+	nop
+
+	li      t1, PLL_CLK_CTRL_VAL
+	sw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+	nop
+
+	lw      t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
+	li      t2, ~QCA953X_PLL_CONFIG_PWD
+	and     t1, t1, t2
+	sw      t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
+	nop
+
+	lw      t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
+	li      t2, ~QCA953X_PLL_CONFIG_PWD
+	and     t1, t1, t2
+	sw      t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
+	nop
+
+	lw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+	li      t2, ~PLL_CLK_CTRL_PLL_BYPASS
+	and     t1, t1, t2
+	sw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+	nop
+
+	li      t1, PLL_DDR_DIT_FRAC_VAL
+	sw      t1, QCA953X_PLL_DDR_DIT_FRAC_REG(t0)
+	nop
+
+	li      t1, PLL_CPU_DIT_FRAC_VAL
+	sw      t1, QCA953X_PLL_CPU_DIT_FRAC_REG(t0)
+	nop
+
+	li      t0, CKSEG1ADDR(AR71XX_RESET_BASE)
+	lui     t1, 0x03fc
+	sw      t1, 0xb4(t0)
+
+	nop
+	jr ra
+	 nop
+    END(lowlevel_init)
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
new file mode 100644
index 0000000..188eccb
--- /dev/null
+++ b/arch/mips/mach-ath79/reset.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>
+
+void _machine_restart(void)
+{
+	void __iomem *base;
+	u32 reg = 0;
+
+	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+			   MAP_NOCACHE);
+	if (soc_is_ar71xx())
+		reg = AR71XX_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar724x())
+		reg = AR724X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar913x())
+		reg = AR913X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar933x())
+		reg = AR933X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar934x())
+		reg = AR934X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca953x())
+		reg = QCA953X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca955x())
+		reg = QCA955X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca956x())
+		reg = QCA956X_RESET_REG_RESET_MODULE;
+	else
+		puts("Reset register not defined for this SOC\n");
+
+	if (reg)
+		setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP);
+
+	while (1)
+		/* NOP */;
+}
+
+u32 get_bootstrap(void)
+{
+	void __iomem *base;
+	u32 reg = 0;
+
+	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+			   MAP_NOCACHE);
+	if (soc_is_ar933x())
+		reg = AR933X_RESET_REG_BOOTSTRAP;
+	else if (soc_is_ar934x())
+		reg = AR934X_RESET_REG_BOOTSTRAP;
+	else if (soc_is_qca953x())
+		reg = QCA953X_RESET_REG_BOOTSTRAP;
+	else if (soc_is_qca955x())
+		reg = QCA955X_RESET_REG_BOOTSTRAP;
+	else if (soc_is_qca956x())
+		reg = QCA956X_RESET_REG_BOOTSTRAP;
+	else
+		puts("Bootstrap register not defined for this SOC\n");
+
+	if (reg)
+		return readl(base + reg);
+
+	return 0;
+}
+
+static int eth_init_ar933x(void)
+{
+	void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+					  MAP_NOCACHE);
+	void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+					  MAP_NOCACHE);
+	void __iomem *gregs = map_physmem(AR933X_GMAC_BASE, AR933X_GMAC_SIZE,
+					  MAP_NOCACHE);
+	const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
+			 AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
+			 AR933X_RESET_ETH_SWITCH;
+
+	/* Clear MDIO slave EN bit. */
+	clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
+	mdelay(10);
+
+	/* Get Atheros S26 PHY out of reset. */
+	clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
+			0x1f, 0x10);
+	mdelay(10);
+
+	setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
+	mdelay(10);
+	clrbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
+	mdelay(10);
+
+	/* Configure AR93xx GMAC register. */
+	clrsetbits_be32(gregs + AR933X_GMAC_REG_ETH_CFG,
+			AR933X_ETH_CFG_MII_GE0_MASTER |
+			AR933X_ETH_CFG_MII_GE0_SLAVE,
+			AR933X_ETH_CFG_MII_GE0_SLAVE);
+	return 0;
+}
+
+static int eth_init_ar934x(void)
+{
+	void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+					  MAP_NOCACHE);
+	void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+					  MAP_NOCACHE);
+	void __iomem *gregs = map_physmem(AR934X_GMAC_BASE, AR934X_GMAC_SIZE,
+					  MAP_NOCACHE);
+	const u32 mask = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO |
+			 AR934X_RESET_GE1_MAC | AR934X_RESET_GE1_MDIO |
+			 AR934X_RESET_ETH_SWITCH_ANALOG;
+	u32 reg;
+
+	reg = readl(rregs + AR934X_RESET_REG_BOOTSTRAP);
+	if (reg & AR934X_BOOTSTRAP_REF_CLK_40)
+		writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
+	else
+		writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
+	writel(BIT(26) | BIT(25), pregs + AR934X_PLL_ETH_XMII_CONTROL_REG);
+
+	setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+	clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+
+	/* Configure AR934x GMAC register. */
+	writel(AR934X_ETH_CFG_RGMII_GMAC0, gregs + AR934X_GMAC_REG_ETH_CFG);
+	return 0;
+}
+
+int ath79_eth_reset(void)
+{
+	/*
+	 * Un-reset ethernet. DM still doesn't have any notion of reset
+	 * framework, so we do it by hand here.
+	 */
+	if (soc_is_ar933x())
+		return eth_init_ar933x();
+	if (soc_is_ar934x())
+		return eth_init_ar934x();
+
+	return -EINVAL;
+}
+
+static int usb_reset_ar933x(void __iomem *reset_regs)
+{
+	/* Ungate the USB block */
+	setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
+		     AR933X_RESET_USBSUS_OVERRIDE);
+	mdelay(1);
+	clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
+		     AR933X_RESET_USB_HOST);
+	mdelay(1);
+	clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
+		     AR933X_RESET_USB_PHY);
+	mdelay(1);
+
+	return 0;
+}
+
+static int usb_reset_ar934x(void __iomem *reset_regs)
+{
+	/* Ungate the USB block */
+	setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
+		     AR934X_RESET_USBSUS_OVERRIDE);
+	mdelay(1);
+	clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
+		     AR934X_RESET_USB_PHY);
+	mdelay(1);
+	clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
+		     AR934X_RESET_USB_PHY_ANALOG);
+	mdelay(1);
+	clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
+		     AR934X_RESET_USB_HOST);
+	mdelay(1);
+
+	return 0;
+}
+
+int ath79_usb_reset(void)
+{
+	void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
+					      AR71XX_USB_CTRL_SIZE,
+					      MAP_NOCACHE);
+	void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
+					       AR71XX_RESET_SIZE,
+					       MAP_NOCACHE);
+	/*
+	 * Turn on the Buff and Desc swap bits.
+	 * NOTE: This write into an undocumented register in mandatory to
+	 *       get the USB controller operational in BigEndian mode.
+	 */
+	writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG);
+
+	if (soc_is_ar933x())
+		return usb_reset_ar933x(reset_regs);
+	if (soc_is_ar934x())
+		return usb_reset_ar934x(reset_regs);
+
+	return -EINVAL;
+}
diff --git a/arch/powerpc/include/asm/fsl_i2c.h b/arch/powerpc/include/asm/fsl_i2c.h
index cbbc834..d2586f9 100644
--- a/arch/powerpc/include/asm/fsl_i2c.h
+++ b/arch/powerpc/include/asm/fsl_i2c.h
@@ -16,7 +16,7 @@
 
 #include <asm/types.h>
 
-typedef struct fsl_i2c {
+typedef struct fsl_i2c_base {
 
 	u8 adr;		/* I2C slave address */
 	u8 res0[3];
@@ -68,4 +68,14 @@
 	u8 res6[0xE8];
 } fsl_i2c_t;
 
+#ifdef CONFIG_DM_I2C
+struct fsl_i2c_dev {
+	struct fsl_i2c_base __iomem *base;      /* register base */
+	u32 i2c_clk;
+	u32 index;
+	u8 slaveadd;
+	uint speed;
+};
+#endif
+
 #endif	/* _ASM_I2C_H_ */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 53ca6d9..07d2adf 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -120,8 +120,8 @@
 
 /* I2C Registers */
 typedef struct ccsr_i2c {
-	struct fsl_i2c	i2c[1];
-	u8	res[4096 - 1 * sizeof(struct fsl_i2c)];
+	struct fsl_i2c_base	i2c[1];
+	u8	res[4096 - 1 * sizeof(struct fsl_i2c_base)];
 } ccsr_i2c_t;
 
 #if defined(CONFIG_MPC8540) \
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
index 177918b..b078569 100644
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -92,8 +92,8 @@
 
 /* Daul I2C Registers(0x3000-0x4000) */
 typedef struct ccsr_i2c {
-	struct fsl_i2c	i2c[2];
-	u8	res[4096 - 2 * sizeof(struct fsl_i2c)];
+	struct fsl_i2c_base	i2c[2];
+	u8	res[4096 - 2 * sizeof(struct fsl_i2c_base)];
 } ccsr_i2c_t;
 
 /* DUART Registers(0x4000-0x5000) */
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index b87ee19..6919632 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -56,6 +56,21 @@
 void outw(unsigned int value, unsigned int addr);
 void outb(unsigned int value, unsigned int addr);
 
+static inline void _insw(volatile u16 *port, void *buf, int ns)
+{
+}
+
+static inline void _outsw(volatile u16 *port, const void *buf, int ns)
+{
+}
+
+#define insw(port, buf, ns)		_insw((u16 *)port, buf, ns)
+#define outsw(port, buf, ns)		_outsw((u16 *)port, buf, ns)
+
+/* For systemace.c */
+#define out16(addr, val)
+#define in16(addr)		0
+
 #include <iotrace.h>
 #include <asm/types.h>
 
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 4ef27dc..29d2307 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -47,6 +47,9 @@
 
 # architecture-specific options below
 
+config AHCI
+	default y
+
 config SYS_MALLOC_F_LEN
 	default 0x800
 
@@ -271,6 +274,13 @@
 	  to be used for speeding up boot time on future reboots and/or
 	  power cycles.
 
+	  For platforms that use Intel FSP for the memory initialization,
+	  please check FSP output HOB via U-Boot command 'fsp hob' to see
+	  if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
+	  If such GUID does not exist, MRC cache is not avaiable on such
+	  platform (eg: Intel Queensbay), which means selecting this option
+	  here does not make any difference.
+
 config HAVE_MRC
 	bool "Add a System Agent binary"
 	depends on !HAVE_FSP
@@ -436,21 +446,13 @@
 config GENERATE_ACPI_TABLE
 	bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
 	default n
+	select QFW if QEMU
 	help
 	  The Advanced Configuration and Power Interface (ACPI) specification
 	  provides an open standard for device configuration and management
 	  by the operating system. It defines platform-independent interfaces
 	  for configuration and power management monitoring.
 
-config QEMU_ACPI_TABLE
-	bool "Load ACPI table from QEMU fw_cfg interface"
-	depends on GENERATE_ACPI_TABLE && QEMU
-	default y
-	help
-	  By default, U-Boot generates its own ACPI tables. This option, if
-	  enabled, disables U-Boot's version and loads ACPI tables generated
-	  by QEMU.
-
 config GENERATE_SMBIOS_TABLE
 	bool "Generate an SMBIOS (System Management BIOS) table"
 	default y
@@ -462,6 +464,22 @@
 
 	  Check http://www.dmtf.org/standards/smbios for details.
 
+config SMBIOS_MANUFACTURER
+	string "SMBIOS Manufacturer"
+	depends on GENERATE_SMBIOS_TABLE
+	default SYS_VENDOR
+	help
+	  The board manufacturer to store in SMBIOS structures.
+	  Change this to override the default one (CONFIG_SYS_VENDOR).
+
+config SMBIOS_PRODUCT_NAME
+	string "SMBIOS Product Name"
+	depends on GENERATE_SMBIOS_TABLE
+	default SYS_BOARD
+	help
+	  The product name to store in SMBIOS structures.
+	  Change this to override the default one (CONFIG_SYS_BOARD).
+
 endmenu
 
 config MAX_PIRQ_LINKS
@@ -536,6 +554,20 @@
 
 	  Check http://www.seabios.org/SeaBIOS for details.
 
+config HIGH_TABLE_SIZE
+	hex "Size of configuration tables which reside in high memory"
+	default 0x10000
+	depends on SEABIOS
+	help
+	  SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
+	  configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
+	  puts a copy of configuration tables in high memory region which
+	  is reserved on the stack before relocation. The region size is
+	  determined by this option.
+
+	  Increse it if the default size does not fit the board's needs.
+	  This is most likely due to a large ACPI DSDT table is used.
+
 source "arch/x86/lib/efi/Kconfig"
 
 endmenu
diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
index 5be5491..a0216f3 100644
--- a/arch/x86/cpu/baytrail/Makefile
+++ b/arch/x86/cpu/baytrail/Makefile
@@ -8,3 +8,4 @@
 obj-y += early_uart.o
 obj-y += fsp_configs.o
 obj-y += valleyview.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
new file mode 100644
index 0000000..1d54f7d
--- /dev/null
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/acpi_table.h>
+#include <asm/ioapic.h>
+#include <asm/mpspec.h>
+#include <asm/tables.h>
+#include <asm/arch/iomap.h>
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt)
+{
+	struct acpi_table_header *header = &(fadt->header);
+	u16 pmbase = ACPI_BASE_ADDRESS;
+
+	memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+	acpi_fill_header(header, "FACP");
+	header->length = sizeof(struct acpi_fadt);
+	header->revision = 4;
+
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	fadt->preferred_pm_profile = ACPI_PM_MOBILE;
+	fadt->sci_int = 9;
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0;
+	fadt->acpi_disable = 0;
+	fadt->s4bios_req = 0;
+	fadt->pstate_cnt = 0;
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x50;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x20;
+	fadt->gpe1_blk = 0;
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0x0d;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+		ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+		ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
+		ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->reset_reg.addrl = IO_PORT_RESET;
+	fadt->reset_reg.addrh = 0;
+	fadt->reset_value = SYS_RST | RST_CPU;
+
+	fadt->x_firmware_ctl_l = (u32)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.access_size = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.access_size = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.access_size = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+static int acpi_create_madt_irq_overrides(u32 current)
+{
+	struct acpi_madt_irqoverride *irqovr;
+	u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+	int length = 0;
+
+	irqovr = (void *)current;
+	length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+	irqovr = (void *)(current + length);
+	length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
+
+	return length;
+}
+
+u32 acpi_fill_madt(u32 current)
+{
+	current += acpi_create_madt_lapics(current);
+
+	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
+			2, IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irq_overrides(current);
+
+	return current;
+}
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index 25382f9..b31f24e 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -53,14 +53,6 @@
 	return 0;
 }
 
-int reserve_arch(void)
-{
-#ifdef CONFIG_ENABLE_MRC_CACHE
-	return mrccache_reserve();
-#else
-	return 0;
-#endif
-}
 #endif
 
 void reset_cpu(ulong addr)
diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c
index f0798a7..317f57d 100644
--- a/arch/x86/cpu/broadwell/pch.c
+++ b/arch/x86/cpu/broadwell/pch.c
@@ -109,7 +109,8 @@
 {
 	u32 reg32;
 
-	io_apic_set_id(0x02);
+	/* Make sure this is a unique ID within system */
+	io_apic_set_id(0x04);
 
 	/* affirm full set of redirection table entries ("write once") */
 	reg32 = io_apic_read(0x01);
diff --git a/arch/x86/cpu/broadwell/sata.c b/arch/x86/cpu/broadwell/sata.c
index dfb8486..2e47082 100644
--- a/arch/x86/cpu/broadwell/sata.c
+++ b/arch/x86/cpu/broadwell/sata.c
@@ -261,7 +261,7 @@
 
 U_BOOT_DRIVER(ahci_broadwell_drv) = {
 	.name		= "ahci_broadwell",
-	.id		= UCLASS_DISK,
+	.id		= UCLASS_AHCI,
 	.of_match	= broadwell_ahci_ids,
 	.ofdata_to_platdata	= broadwell_sata_ofdata_to_platdata,
 	.probe		= broadwell_sata_probe,
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index 4bf5d15..e7befde 100644
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -190,11 +190,6 @@
 	return 0;
 }
 
-int reserve_arch(void)
-{
-	return mrccache_reserve();
-}
-
 int dram_init(void)
 {
 	struct pei_data _pei_data __aligned(8);
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 845f86a..1b04203 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -39,15 +39,7 @@
 	return default_print_cpuinfo();
 }
 
-int last_stage_init(void)
-{
-	if (gd->flags & GD_FLG_COLD_BOOT)
-		timestamp_add_to_bootstage();
-
-	return 0;
-}
-
-void board_final_cleanup(void)
+static void board_final_cleanup(void)
 {
 	/*
 	 * Un-cache the ROM so the kernel has one
@@ -79,6 +71,16 @@
 	}
 }
 
+int last_stage_init(void)
+{
+	if (gd->flags & GD_FLG_COLD_BOOT)
+		timestamp_add_to_bootstage();
+
+	board_final_cleanup();
+
+	return 0;
+}
+
 int misc_init_r(void)
 {
 	return 0;
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 233a6c8..e522ff3 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -25,10 +25,12 @@
 #include <errno.h>
 #include <malloc.h>
 #include <asm/control_regs.h>
+#include <asm/coreboot_tables.h>
 #include <asm/cpu.h>
 #include <asm/lapic.h>
 #include <asm/microcode.h>
 #include <asm/mp.h>
+#include <asm/mrccache.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
 #include <asm/post.h>
@@ -661,10 +663,20 @@
 }
 
 #ifndef CONFIG_SYS_COREBOOT
+/*
+ * Implement a weak default function for boards that optionally
+ * need to clean up the system before jumping to the kernel.
+ */
+__weak void board_final_cleanup(void)
+{
+}
+
 int last_stage_init(void)
 {
 	write_tables();
 
+	board_final_cleanup();
+
 	return 0;
 }
 #endif
@@ -741,3 +753,18 @@
 
 	return 0;
 }
+
+#ifndef CONFIG_EFI_STUB
+int reserve_arch(void)
+{
+#ifdef CONFIG_ENABLE_MRC_CACHE
+	mrccache_reserve();
+#endif
+
+#ifdef CONFIG_SEABIOS
+	high_table_reserve();
+#endif
+
+	return 0;
+}
+#endif
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index 93e4505..0fdef6f 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -58,7 +58,7 @@
 		return -ENODEV;
 
 	/* Cause the SATA device to do its early init */
-	uclass_first_device(UCLASS_DISK, &dev);
+	uclass_first_device(UCLASS_AHCI, &dev);
 
 	return 0;
 }
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index 10dc4d4..dd2819a 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -15,14 +15,14 @@
 #include <dm.h>
 #include <asm/cache.h>
 #include <asm/control_regs.h>
+#include <asm/i8259.h>
 #include <asm/interrupt.h>
 #include <asm/io.h>
-#include <asm/processor-flags.h>
-#include <linux/compiler.h>
+#include <asm/lapic.h>
 #include <asm/msr.h>
+#include <asm/processor-flags.h>
 #include <asm/processor.h>
 #include <asm/u-boot-x86.h>
-#include <asm/i8259.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -266,6 +266,8 @@
 	i8259_init();
 #endif
 
+	lapic_setup();
+
 	/* Initialize core interrupt and exception functionality of CPU */
 	cpu_init_interrupts();
 
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 295078305..df3cd0a 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -13,6 +13,7 @@
 #include <asm/irq.h>
 #include <asm/pci.h>
 #include <asm/pirq_routing.h>
+#include <asm/tables.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -121,6 +122,11 @@
 	priv->irq_mask = fdtdec_get_int(blob, node,
 					"intel,pirq-mask", PIRQ_BITMAP);
 
+	if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
+		/* Reserve IRQ9 for SCI */
+		priv->irq_mask &= ~(1 << 9);
+	}
+
 	if (priv->config == PIRQ_VIA_IBASE) {
 		int ibase_off;
 
@@ -142,6 +148,9 @@
 		priv->ibase &= ~0xf;
 	}
 
+	priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
+	priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
+
 	cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
 	if (!cell || len % sizeof(struct pirq_routing))
 		return -EINVAL;
@@ -206,11 +215,30 @@
 
 	rt->size = irq_entries * sizeof(struct irq_info) + 32;
 
+	/* Fix up the table checksum */
+	rt->checksum = table_compute_checksum(rt, rt->size);
+
 	pirq_routing_table = rt;
 
 	return 0;
 }
 
+static void irq_enable_sci(struct udevice *dev)
+{
+	struct irq_router *priv = dev_get_priv(dev);
+
+	if (priv->actl_8bit) {
+		/* Bit7 must be turned on to enable ACPI */
+		dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
+	} else {
+		/* Write 0 to enable SCI on IRQ9 */
+		if (priv->config == PIRQ_VIA_PCI)
+			dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
+		else
+			writel(0, priv->ibase + priv->actl_addr);
+	}
+}
+
 int irq_router_common_init(struct udevice *dev)
 {
 	int ret;
@@ -224,6 +252,9 @@
 	pirq_route_irqs(dev, pirq_routing_table->slots,
 			get_irq_slot_count(pirq_routing_table));
 
+	if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
+		irq_enable_sci(dev);
+
 	return 0;
 }
 
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 4c039ac..5b58d6c 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -162,7 +162,7 @@
 		return 0;
 
 	/* Cause the SATA device to do its init */
-	uclass_first_device(UCLASS_DISK, &dev);
+	uclass_first_device(UCLASS_AHCI, &dev);
 
 	ret = syscon_get_by_driver_data(X86_SYSCON_GMA, &gma_dev);
 	if (ret)
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 88ab797..ff1faa5 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -12,7 +12,6 @@
 #include <fdtdec.h>
 #include <rtc.h>
 #include <pci.h>
-#include <asm/acpi.h>
 #include <asm/intel_regs.h>
 #include <asm/interrupt.h>
 #include <asm/io.h>
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index cef4256..38e244b 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -12,10 +12,8 @@
 #include <dm.h>
 #include <fdtdec.h>
 #include <malloc.h>
-#include <asm/acpi.h>
 #include <asm/cpu.h>
 #include <asm/cpu_x86.h>
-#include <asm/lapic.h>
 #include <asm/msr.h>
 #include <asm/msr-index.h>
 #include <asm/mtrr.h>
@@ -419,7 +417,6 @@
 
 	/* Enable the local cpu apics */
 	enable_lapic_tpr();
-	lapic_setup();
 
 	/* Enable virtualization if enabled in CMOS */
 	enable_vmx();
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index f7e0bc3..491f289 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -10,7 +10,6 @@
 #include <common.h>
 #include <dm.h>
 #include <asm/msr.h>
-#include <asm/acpi.h>
 #include <asm/cpu.h>
 #include <asm/intel_regs.h>
 #include <asm/io.h>
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index c3d1057..1ce8195 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -233,7 +233,7 @@
 
 U_BOOT_DRIVER(ahci_ivybridge_drv) = {
 	.name		= "ahci_ivybridge",
-	.id		= UCLASS_DISK,
+	.id		= UCLASS_AHCI,
 	.of_match	= bd82x6x_ahci_ids,
 	.probe		= bd82x6x_sata_probe,
 };
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index e35e543..9d9f63d 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -201,11 +201,6 @@
 	return false;
 }
 
-int reserve_arch(void)
-{
-	return mrccache_reserve();
-}
-
 static int copy_spd(struct udevice *dev, struct pei_data *peid)
 {
 	const void *data;
diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c
index 30d2313..fbea2d1 100644
--- a/arch/x86/cpu/lapic.c
+++ b/arch/x86/cpu/lapic.c
@@ -65,23 +65,27 @@
 
 void enable_lapic(void)
 {
-	msr_t msr;
+	if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
+		msr_t msr;
 
-	msr = msr_read(MSR_IA32_APICBASE);
-	msr.hi &= 0xffffff00;
-	msr.lo |= MSR_IA32_APICBASE_ENABLE;
-	msr.lo &= ~MSR_IA32_APICBASE_BASE;
-	msr.lo |= LAPIC_DEFAULT_BASE;
-	msr_write(MSR_IA32_APICBASE, msr);
+		msr = msr_read(MSR_IA32_APICBASE);
+		msr.hi &= 0xffffff00;
+		msr.lo |= MSR_IA32_APICBASE_ENABLE;
+		msr.lo &= ~MSR_IA32_APICBASE_BASE;
+		msr.lo |= LAPIC_DEFAULT_BASE;
+		msr_write(MSR_IA32_APICBASE, msr);
+	}
 }
 
 void disable_lapic(void)
 {
-	msr_t msr;
+	if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
+		msr_t msr;
 
-	msr = msr_read(MSR_IA32_APICBASE);
-	msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
-	msr_write(MSR_IA32_APICBASE, msr);
+		msr = msr_read(MSR_IA32_APICBASE);
+		msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
+		msr_write(MSR_IA32_APICBASE, msr);
+	}
 }
 
 unsigned long lapicid(void)
@@ -120,7 +124,6 @@
 
 void lapic_setup(void)
 {
-#ifdef CONFIG_SMP
 	/* Only Pentium Pro and later have those MSR stuff */
 	debug("Setting up local apic: ");
 
@@ -150,11 +153,7 @@
 		    LAPIC_DELIVERY_MODE_NMI));
 
 	debug("apic_id: 0x%02lx, ", lapicid());
-#else /* !CONFIG_SMP */
-	/* Only Pentium Pro and later have those MSR stuff */
-	debug("Disabling local apic: ");
-	disable_lapic();
-#endif /* CONFIG_SMP */
+
 	debug("done.\n");
 	post_code(POST_LAPIC);
 }
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 2604a68..2b6b3bd 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -11,6 +11,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
+#include <qfw.h>
 #include <asm/atomic.h>
 #include <asm/cpu.h>
 #include <asm/interrupt.h>
@@ -21,7 +22,6 @@
 #include <asm/mtrr.h>
 #include <asm/processor.h>
 #include <asm/sipi.h>
-#include <asm/fw_cfg.h>
 #include <dm/device-internal.h>
 #include <dm/uclass-internal.h>
 #include <dm/lists.h>
@@ -408,8 +408,6 @@
 	cpu_get_name(processor_name);
 	debug("CPU: %s\n", processor_name);
 
-	lapic_setup();
-
 	apic_id = lapicid();
 	ret = find_cpu_by_apic_id(apic_id, devp);
 	if (ret) {
@@ -420,7 +418,7 @@
 	return 0;
 }
 
-#ifdef CONFIG_QEMU
+#ifdef CONFIG_QFW
 static int qemu_cpu_fixup(void)
 {
 	int ret;
@@ -496,7 +494,7 @@
 	if (ret)
 		return ret;
 
-#ifdef CONFIG_QEMU
+#ifdef CONFIG_QFW
 	ret = qemu_cpu_fixup();
 	if (ret)
 		return ret;
diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile
index 6eeddf1..a080c5e 100644
--- a/arch/x86/cpu/qemu/Makefile
+++ b/arch/x86/cpu/qemu/Makefile
@@ -7,4 +7,5 @@
 ifndef CONFIG_EFI_STUB
 obj-y += car.o dram.o
 endif
-obj-y += cpu.o fw_cfg.o qemu.o
+obj-y += qemu.o
+obj-$(CONFIG_QFW) += cpu.o e820.o
diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c
index a1b70c6..b1a965e 100644
--- a/arch/x86/cpu/qemu/cpu.c
+++ b/arch/x86/cpu/qemu/cpu.c
@@ -8,8 +8,8 @@
 #include <cpu.h>
 #include <dm.h>
 #include <errno.h>
+#include <qfw.h>
 #include <asm/cpu.h>
-#include <asm/fw_cfg.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c
new file mode 100644
index 0000000..63853e4
--- /dev/null
+++ b/arch/x86/cpu/qemu/e820.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/e820.h>
+
+unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
+{
+	entries[0].addr = 0;
+	entries[0].size = ISA_START_ADDRESS;
+	entries[0].type = E820_RAM;
+
+	entries[1].addr = ISA_START_ADDRESS;
+	entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
+	entries[1].type = E820_RESERVED;
+
+	/*
+	 * since we use memalign(malloc) to allocate high memory for
+	 * storing ACPI tables, we need to reserve them in e820 tables,
+	 * otherwise kernel will reclaim them and data will be corrupted
+	 */
+	entries[2].addr = ISA_END_ADDRESS;
+	entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
+	entries[2].type = E820_RAM;
+
+	/* for simplicity, reserve entire malloc space */
+	entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
+	entries[3].size = TOTAL_MALLOC_LEN;
+	entries[3].type = E820_RESERVED;
+
+	entries[4].addr = gd->relocaddr;
+	entries[4].size = gd->ram_size - gd->relocaddr;
+	entries[4].type = E820_RESERVED;
+
+	entries[5].addr = CONFIG_PCIE_ECAM_BASE;
+	entries[5].size = CONFIG_PCIE_ECAM_SIZE;
+	entries[5].type = E820_RESERVED;
+
+	return 6;
+}
diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c
deleted file mode 100644
index 2e2794e..0000000
--- a/arch/x86/cpu/qemu/fw_cfg.c
+++ /dev/null
@@ -1,570 +0,0 @@
-/*
- * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <errno.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/fw_cfg.h>
-#include <asm/tables.h>
-#include <asm/e820.h>
-#include <linux/list.h>
-#include <memalign.h>
-
-static bool fwcfg_present;
-static bool fwcfg_dma_present;
-
-static LIST_HEAD(fw_list);
-
-/* Read configuration item using fw_cfg PIO interface */
-static void qemu_fwcfg_read_entry_pio(uint16_t entry,
-		uint32_t size, void *address)
-{
-	uint32_t i = 0;
-	uint8_t *data = address;
-
-	/*
-	 * writting FW_CFG_INVALID will cause read operation to resume at
-	 * last offset, otherwise read will start at offset 0
-	 */
-	if (entry != FW_CFG_INVALID)
-		outw(entry, FW_CONTROL_PORT);
-	while (size--)
-		data[i++] = inb(FW_DATA_PORT);
-}
-
-/* Read configuration item using fw_cfg DMA interface */
-static void qemu_fwcfg_read_entry_dma(uint16_t entry,
-		uint32_t size, void *address)
-{
-	struct fw_cfg_dma_access dma;
-
-	dma.length = cpu_to_be32(size);
-	dma.address = cpu_to_be64((uintptr_t)address);
-	dma.control = cpu_to_be32(FW_CFG_DMA_READ);
-
-	/*
-	 * writting FW_CFG_INVALID will cause read operation to resume at
-	 * last offset, otherwise read will start at offset 0
-	 */
-	if (entry != FW_CFG_INVALID)
-		dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
-
-	barrier();
-
-	debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n",
-	      address, size, be32_to_cpu(dma.control));
-
-	outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH);
-
-	while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR)
-		__asm__ __volatile__ ("pause");
-}
-
-static bool qemu_fwcfg_present(void)
-{
-	uint32_t qemu;
-
-	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
-	return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE;
-}
-
-static bool qemu_fwcfg_dma_present(void)
-{
-	uint8_t dma_enabled;
-
-	qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
-	if (dma_enabled & FW_CFG_DMA_ENABLED)
-		return true;
-
-	return false;
-}
-
-static void qemu_fwcfg_read_entry(uint16_t entry,
-		uint32_t length, void *address)
-{
-	if (fwcfg_dma_present)
-		qemu_fwcfg_read_entry_dma(entry, length, address);
-	else
-		qemu_fwcfg_read_entry_pio(entry, length, address);
-}
-
-int qemu_fwcfg_online_cpus(void)
-{
-	uint16_t nb_cpus;
-
-	if (!fwcfg_present)
-		return -ENODEV;
-
-	qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
-
-	return le16_to_cpu(nb_cpus);
-}
-
-/*
- * This function prepares kernel for zboot. It loads kernel data
- * to 'load_addr', initrd to 'initrd_addr' and kernel command
- * line using qemu fw_cfg interface.
- */
-static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
-{
-	char *data_addr;
-	uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
-
-	qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
-	qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
-
-	if (setup_size == 0 || kernel_size == 0) {
-		printf("warning: no kernel available\n");
-		return -1;
-	}
-
-	data_addr = load_addr;
-	qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
-			      le32_to_cpu(setup_size), data_addr);
-	data_addr += le32_to_cpu(setup_size);
-
-	qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
-			      le32_to_cpu(kernel_size), data_addr);
-	data_addr += le32_to_cpu(kernel_size);
-
-	data_addr = initrd_addr;
-	qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
-	if (initrd_size == 0) {
-		printf("warning: no initrd available\n");
-	} else {
-		qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
-				      le32_to_cpu(initrd_size), data_addr);
-		data_addr += le32_to_cpu(initrd_size);
-	}
-
-	qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
-	if (cmdline_size) {
-		qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
-				      le32_to_cpu(cmdline_size), data_addr);
-		/*
-		 * if kernel cmdline only contains '\0', (e.g. no -append
-		 * when invoking qemu), do not update bootargs
-		 */
-		if (*data_addr != '\0') {
-			if (setenv("bootargs", data_addr) < 0)
-				printf("warning: unable to change bootargs\n");
-		}
-	}
-
-	printf("loading kernel to address %p size %x", load_addr,
-	       le32_to_cpu(kernel_size));
-	if (initrd_size)
-		printf(" initrd %p size %x\n",
-		       initrd_addr,
-		       le32_to_cpu(initrd_size));
-	else
-		printf("\n");
-
-	return 0;
-}
-
-static int qemu_fwcfg_read_firmware_list(void)
-{
-	int i;
-	uint32_t count;
-	struct fw_file *file;
-	struct list_head *entry;
-
-	/* don't read it twice */
-	if (!list_empty(&fw_list))
-		return 0;
-
-	qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
-	if (!count)
-		return 0;
-
-	count = be32_to_cpu(count);
-	for (i = 0; i < count; i++) {
-		file = malloc(sizeof(*file));
-		if (!file) {
-			printf("error: allocating resource\n");
-			goto err;
-		}
-		qemu_fwcfg_read_entry(FW_CFG_INVALID,
-				      sizeof(struct fw_cfg_file), &file->cfg);
-		file->addr = 0;
-		list_add_tail(&file->list, &fw_list);
-	}
-
-	return 0;
-
-err:
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		free(file);
-	}
-
-	return -ENOMEM;
-}
-
-#ifdef CONFIG_QEMU_ACPI_TABLE
-static struct fw_file *qemu_fwcfg_find_file(const char *name)
-{
-	struct list_head *entry;
-	struct fw_file *file;
-
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		if (!strcmp(file->cfg.name, name))
-			return file;
-	}
-
-	return NULL;
-}
-
-/*
- * This function allocates memory for ACPI tables
- *
- * @entry : BIOS linker command entry which tells where to allocate memory
- *          (either high memory or low memory)
- * @addr  : The address that should be used for low memory allcation. If the
- *          memory allocation request is 'ZONE_HIGH' then this parameter will
- *          be ignored.
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr)
-{
-	uint32_t size, align;
-	struct fw_file *file;
-	unsigned long aligned_addr;
-
-	align = le32_to_cpu(entry->alloc.align);
-	/* align must be power of 2 */
-	if (align & (align - 1)) {
-		printf("error: wrong alignment %u\n", align);
-		return -EINVAL;
-	}
-
-	file = qemu_fwcfg_find_file(entry->alloc.file);
-	if (!file) {
-		printf("error: can't find file %s\n", entry->alloc.file);
-		return -ENOENT;
-	}
-
-	size = be32_to_cpu(file->cfg.size);
-
-	/*
-	 * ZONE_HIGH means we need to allocate from high memory, since
-	 * malloc space is already at the end of RAM, so we directly use it.
-	 * If allocation zone is ZONE_FSEG, then we use the 'addr' passed
-	 * in which is low memory
-	 */
-	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
-		aligned_addr = (unsigned long)memalign(align, size);
-		if (!aligned_addr) {
-			printf("error: allocating resource\n");
-			return -ENOMEM;
-		}
-	} else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
-		aligned_addr = ALIGN(*addr, align);
-	} else {
-		printf("error: invalid allocation zone\n");
-		return -EINVAL;
-	}
-
-	debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n",
-	      file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
-
-	qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
-			      size, (void *)aligned_addr);
-	file->addr = aligned_addr;
-
-	/* adjust address for low memory allocation */
-	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
-		*addr = (aligned_addr + size);
-
-	return 0;
-}
-
-/*
- * This function patches ACPI tables previously loaded
- * by bios_linker_allocate()
- *
- * @entry : BIOS linker command entry which tells how to patch
- *          ACPI tables
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_add_pointer(struct bios_linker_entry *entry)
-{
-	struct fw_file *dest, *src;
-	uint32_t offset = le32_to_cpu(entry->pointer.offset);
-	uint64_t pointer = 0;
-
-	dest = qemu_fwcfg_find_file(entry->pointer.dest_file);
-	if (!dest || !dest->addr)
-		return -ENOENT;
-	src = qemu_fwcfg_find_file(entry->pointer.src_file);
-	if (!src || !src->addr)
-		return -ENOENT;
-
-	debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n",
-	      dest->addr, src->addr, offset, entry->pointer.size, pointer);
-
-	memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size);
-	pointer	= le64_to_cpu(pointer);
-	pointer += (unsigned long)src->addr;
-	pointer	= cpu_to_le64(pointer);
-	memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size);
-
-	return 0;
-}
-
-/*
- * This function updates checksum fields of ACPI tables previously loaded
- * by bios_linker_allocate()
- *
- * @entry : BIOS linker command entry which tells where to update ACPI table
- *          checksums
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_add_checksum(struct bios_linker_entry *entry)
-{
-	struct fw_file *file;
-	uint8_t *data, cksum = 0;
-	uint8_t *cksum_start;
-
-	file = qemu_fwcfg_find_file(entry->cksum.file);
-	if (!file || !file->addr)
-		return -ENOENT;
-
-	data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset));
-	cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start));
-	cksum = table_compute_checksum(cksum_start,
-				       le32_to_cpu(entry->cksum.length));
-	*data = cksum;
-
-	return 0;
-}
-
-unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
-{
-	entries[0].addr = 0;
-	entries[0].size = ISA_START_ADDRESS;
-	entries[0].type = E820_RAM;
-
-	entries[1].addr = ISA_START_ADDRESS;
-	entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
-	entries[1].type = E820_RESERVED;
-
-	/*
-	 * since we use memalign(malloc) to allocate high memory for
-	 * storing ACPI tables, we need to reserve them in e820 tables,
-	 * otherwise kernel will reclaim them and data will be corrupted
-	 */
-	entries[2].addr = ISA_END_ADDRESS;
-	entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
-	entries[2].type = E820_RAM;
-
-	/* for simplicity, reserve entire malloc space */
-	entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
-	entries[3].size = TOTAL_MALLOC_LEN;
-	entries[3].type = E820_RESERVED;
-
-	entries[4].addr = gd->relocaddr;
-	entries[4].size = gd->ram_size - gd->relocaddr;
-	entries[4].type = E820_RESERVED;
-
-	entries[5].addr = CONFIG_PCIE_ECAM_BASE;
-	entries[5].size = CONFIG_PCIE_ECAM_SIZE;
-	entries[5].type = E820_RESERVED;
-
-	return 6;
-}
-
-/* This function loads and patches ACPI tables provided by QEMU */
-u32 write_acpi_tables(u32 addr)
-{
-	int i, ret = 0;
-	struct fw_file *file;
-	struct bios_linker_entry *table_loader;
-	struct bios_linker_entry *entry;
-	uint32_t size;
-	struct list_head *list;
-
-	/* make sure fw_list is loaded */
-	ret = qemu_fwcfg_read_firmware_list();
-	if (ret) {
-		printf("error: can't read firmware file list\n");
-		return addr;
-	}
-
-	file = qemu_fwcfg_find_file("etc/table-loader");
-	if (!file) {
-		printf("error: can't find etc/table-loader\n");
-		return addr;
-	}
-
-	size = be32_to_cpu(file->cfg.size);
-	if ((size % sizeof(*entry)) != 0) {
-		printf("error: table-loader maybe corrupted\n");
-		return addr;
-	}
-
-	table_loader = malloc(size);
-	if (!table_loader) {
-		printf("error: no memory for table-loader\n");
-		return addr;
-	}
-
-	qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
-			      size, table_loader);
-
-	for (i = 0; i < (size / sizeof(*entry)); i++) {
-		entry = table_loader + i;
-		switch (le32_to_cpu(entry->command)) {
-		case BIOS_LINKER_LOADER_COMMAND_ALLOCATE:
-			ret = bios_linker_allocate(entry, &addr);
-			if (ret)
-				goto out;
-			break;
-		case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER:
-			ret = bios_linker_add_pointer(entry);
-			if (ret)
-				goto out;
-			break;
-		case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM:
-			ret = bios_linker_add_checksum(entry);
-			if (ret)
-				goto out;
-			break;
-		default:
-			break;
-		}
-	}
-
-out:
-	if (ret) {
-		list_for_each(list, &fw_list) {
-			file = list_entry(list, struct fw_file, list);
-			if (file->addr)
-				free((void *)file->addr);
-		}
-	}
-
-	free(table_loader);
-	return addr;
-}
-#endif
-
-static int qemu_fwcfg_list_firmware(void)
-{
-	int ret;
-	struct list_head *entry;
-	struct fw_file *file;
-
-	/* make sure fw_list is loaded */
-	ret = qemu_fwcfg_read_firmware_list();
-	if (ret)
-		return ret;
-
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		printf("%-56s\n", file->cfg.name);
-	}
-
-	return 0;
-}
-
-void qemu_fwcfg_init(void)
-{
-	fwcfg_present = qemu_fwcfg_present();
-	if (fwcfg_present)
-		fwcfg_dma_present = qemu_fwcfg_dma_present();
-}
-
-static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
-{
-	if (qemu_fwcfg_list_firmware() < 0)
-		return CMD_RET_FAILURE;
-
-	return 0;
-}
-
-static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
-{
-	int ret = qemu_fwcfg_online_cpus();
-	if (ret < 0) {
-		printf("QEMU fw_cfg interface not found\n");
-		return CMD_RET_FAILURE;
-	}
-
-	printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
-
-	return 0;
-}
-
-static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
-{
-	char *env;
-	void *load_addr;
-	void *initrd_addr;
-
-	env = getenv("loadaddr");
-	load_addr = env ?
-		(void *)simple_strtoul(env, NULL, 16) :
-		(void *)CONFIG_LOADADDR;
-
-	env = getenv("ramdiskaddr");
-	initrd_addr = env ?
-		(void *)simple_strtoul(env, NULL, 16) :
-		(void *)CONFIG_RAMDISK_ADDR;
-
-	if (argc == 2) {
-		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
-		initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
-	} else if (argc == 1) {
-		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
-	}
-
-	return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
-}
-
-static cmd_tbl_t fwcfg_commands[] = {
-	U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
-	U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
-	U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
-};
-
-static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int ret;
-	cmd_tbl_t *fwcfg_cmd;
-
-	if (!fwcfg_present) {
-		printf("QEMU fw_cfg interface not found\n");
-		return CMD_RET_USAGE;
-	}
-
-	fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
-				 ARRAY_SIZE(fwcfg_commands));
-	argc -= 2;
-	argv += 2;
-	if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
-		return CMD_RET_USAGE;
-
-	ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
-
-	return cmd_process_error(fwcfg_cmd, ret);
-}
-
-U_BOOT_CMD(
-	qfw,	4,	1,	do_qemu_fw,
-	"QEMU firmware interface",
-	"<command>\n"
-	"    - list                             : print firmware(s) currently loaded\n"
-	"    - cpus                             : print online cpu number\n"
-	"    - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
-)
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 7ad0ee4..680e558 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -6,15 +6,59 @@
 
 #include <common.h>
 #include <pci.h>
+#include <qfw.h>
 #include <asm/irq.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/arch/device.h>
 #include <asm/arch/qemu.h>
-#include <asm/fw_cfg.h>
 
 static bool i440fx;
 
+#ifdef CONFIG_QFW
+
+/* on x86, the qfw registers are all IO ports */
+#define FW_CONTROL_PORT	0x510
+#define FW_DATA_PORT		0x511
+#define FW_DMA_PORT_LOW	0x514
+#define FW_DMA_PORT_HIGH	0x518
+
+static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
+		uint32_t size, void *address)
+{
+	uint32_t i = 0;
+	uint8_t *data = address;
+
+	/*
+	 * writting FW_CFG_INVALID will cause read operation to resume at
+	 * last offset, otherwise read will start at offset 0
+	 *
+	 * Note: on platform where the control register is IO port, the
+	 * endianness is little endian.
+	 */
+	if (entry != FW_CFG_INVALID)
+		outw(cpu_to_le16(entry), FW_CONTROL_PORT);
+
+	/* the endianness of data register is string-preserving */
+	while (size--)
+		data[i++] = inb(FW_DATA_PORT);
+}
+
+static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
+{
+	/* the DMA address register is big endian */
+	outl(cpu_to_be32((uint32_t)dma), FW_DMA_PORT_HIGH);
+
+	while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
+		__asm__ __volatile__ ("pause");
+}
+
+static struct fw_cfg_arch_ops fwcfg_x86_ops = {
+	.arch_read_pio = qemu_x86_fwcfg_read_entry_pio,
+	.arch_read_dma = qemu_x86_fwcfg_read_entry_dma
+};
+#endif
+
 static void enable_pm_piix(void)
 {
 	u8 en;
@@ -88,7 +132,9 @@
 		enable_pm_ich9();
 	}
 
-	qemu_fwcfg_init();
+#ifdef CONFIG_QFW
+	qemu_fwcfg_init(&fwcfg_x86_ops);
+#endif
 }
 
 int arch_cpu_init(void)
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index afb3463..bdd360a 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <mmc.h>
 #include <asm/io.h>
+#include <asm/ioapic.h>
 #include <asm/mrccache.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
@@ -338,6 +339,9 @@
 	mrccache_save();
 #endif
 
+	/* Assign a unique I/O APIC ID */
+	io_apic_set_id(1);
+
 	return 0;
 }
 
@@ -360,12 +364,3 @@
 
 	return;
 }
-
-int reserve_arch(void)
-{
-#ifdef CONFIG_ENABLE_MRC_CACHE
-	return mrccache_reserve();
-#else
-	return 0;
-#endif
-}
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 4ea9262..4a50d86 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -84,6 +84,7 @@
 				compatible = "intel,irq-router";
 				intel,pirq-config = "ibase";
 				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
 				intel,pirq-link = <8 8>;
 				intel,pirq-mask = <0xdee0>;
 				intel,pirq-routing = <
@@ -249,10 +250,10 @@
 #include "microcode/m0230671117.dtsi"
 		};
 		update@1 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
 		};
 		update@2 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
 		};
 	};
 
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 478dece..1a4ecaa 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -88,6 +88,7 @@
 				compatible = "intel,irq-router";
 				intel,pirq-config = "ibase";
 				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
 				intel,pirq-link = <8 8>;
 				intel,pirq-mask = <0xdee0>;
 				intel,pirq-routing = <
@@ -269,10 +270,10 @@
 
 	microcode {
 		update@0 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
 		};
 		update@1 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
 		};
 	};
 };
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 337513b..78a1ef4 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -154,6 +154,7 @@
 			irq-router {
 				compatible = "intel,queensbay-irq-router";
 				intel,pirq-config = "pci";
+				intel,actl-addr = <0x58>;
 				intel,pirq-link = <0x60 8>;
 				intel,pirq-mask = <0xcee0>;
 				intel,pirq-routing = <
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 21c3641..da3cbff 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -29,6 +29,18 @@
 		stdout-path = &pciuart0;
 	};
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "cpu-x86";
+			reg = <0>;
+			intel,apic-id = <0>;
+		};
+	};
+
 	tsc-timer {
 		clock-frequency = <400000000>;
 	};
@@ -88,6 +100,7 @@
 			irq-router {
 				compatible = "intel,quark-irq-router";
 				intel,pirq-config = "pci";
+				intel,actl-addr = <0x58>;
 				intel,pirq-link = <0x60 8>;
 				intel,pirq-mask = <0xdef8>;
 				intel,pirq-routing = <
diff --git a/arch/x86/dts/microcode/m0130673322.dtsi b/arch/x86/dts/microcode/m0130673322.dtsi
deleted file mode 100644
index 90bf2fb..0000000
--- a/arch/x86/dts/microcode/m0130673322.dtsi
+++ /dev/null
@@ -1,3284 +0,0 @@
-/*
- * ---
- * This is a device tree fragment. Use #include to add these properties to a
- * node.
- *
- * Date:
- */
-
-compatible = "intel,microcode";
-intel,header-version = <1>;
-intel,update-revision = <0x322>;
-intel,date-code = <0x4012014>;
-intel,processor-signature = <0x30673>;
-intel,checksum = <0x17b0d914>;
-intel,loader-revision = <1>;
-intel,processor-flags = <0x1>;
-
-/* The first 48-bytes are the public header which repeats the above data */
-data = <
-	0x01000000	0x22030000	0x14200104	0x73060300
-	0x14d9b017	0x01000000	0x01000000	0xd0cb0000
-	0x00cc0000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xa1000000	0x01000200	0x22030000
-	0x00000000	0x00000000	0x31031420	0x11320000
-	0x01000000	0x73060300	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xf4320000	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x0ae10178	0x7c98f9d1	0x41962d85	0x19391270
-	0xcf3c0336	0xc1f13d6f	0xe46abaf6	0x3b65ca6b
-	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
-	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
-	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
-	0xc928c400	0x3add156d	0x531946f9	0x92a03216
-	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
-	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
-	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
-	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
-	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
-	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
-	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
-	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
-	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
-	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
-	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
-	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
-	0x11000000	0x8514b971	0x40df7b4a	0x6a6b7285
-	0x7978ef59	0x319bddf5	0x04c68e5a	0xe1c28b10
-	0x172f63dc	0x306fb95d	0x31d881e8	0x69f8e08d
-	0x617a99e1	0x1ab6b574	0x2951fa5b	0xcc7e3e94
-	0xff379d19	0x5c035dec	0xe28ed726	0x22b8a5ac
-	0xd08b3ac5	0x45c03b9e	0xcea4083c	0xc26758aa
-	0xbe7cf81e	0x43d898f3	0x5c45a635	0xc9cac095
-	0xb89aea20	0x2c02b40e	0xe3a8b48d	0xeabfb60e
-	0x776ed2a9	0x080ae6d5	0x7f64b1df	0x00e40ee6
-	0x0f1c10f4	0x792e5423	0x787f5459	0x63a8b02c
-	0x3fd6a255	0x049cae26	0x0949f5ff	0x9aebb236
-	0xecc01775	0x91b57b84	0xe0e45ea3	0x5a8bf79e
-	0x356a843a	0x2406795f	0x8aaae5d8	0x6a8c877c
-	0xa8b2b8f4	0x04cf8f49	0x422d9e2c	0xf09f9896
-	0xe9b92215	0x9c98fb44	0x88556b7f	0x519d6f4c
-	0x9e8a016b	0xcb18d16c	0x419b4ee7	0x080b49c8
-	0xc51b875e	0x46aabc9c	0x262d27eb	0x93ea189d
-	0xdd0da69d	0x3e5b17e8	0xcc78509a	0x00b07e6e
-	0x363d5a70	0x64572070	0x8a84abc4	0x1cb03838
-	0x965fd76a	0x540aafc9	0x83a91654	0x1a722e67
-	0x4bf98ce1	0x2b3c2ff9	0x972cebd4	0xf3a68395
-	0x2613e422	0xf8d031d7	0xb1c79a0f	0xfd44f65b
-	0xa7012a9b	0xd9a15a60	0xc311fc0c	0x6f52f878
-	0x3d68381d	0xd2a035d7	0xb790c50e	0x9f1e5010
-	0x41877064	0xa9d1e4ae	0xfe9abbd5	0x60c2c748
-	0x8167e5ad	0x022dbfb3	0x75abe483	0x51c37170
-	0x09b8590d	0xc1bb323d	0x2c7336b1	0xd4d0d49b
-	0xc7f6152b	0x7919d596	0x1e1ff62e	0xc49604a0
-	0x33857369	0xeaa3f382	0x98b8cd86	0x176e1bf3
-	0x1a68867b	0x6af0a11c	0x69a82b25	0x48c72525
-	0xa00aae2d	0xb09f67f4	0x1a99f83d	0x7266cca3
-	0x8d03a7da	0x2e1d7c49	0x01ac68ae	0x93188770
-	0x0609e769	0x982ed28d	0xe40999e0	0x8932ebab
-	0x5637ad5a	0x2725e8ad	0x56d7caaf	0xc351faa2
-	0x09dbd737	0x0d2f3bf0	0x0623330d	0xdd547489
-	0xcca7e722	0xa9096d13	0x95b17818	0xc092cb81
-	0x72c6eefc	0x1811c37e	0x78161497	0x8be0c4c6
-	0xd63aeb19	0x91ab68df	0x8f2e5e4d	0xf4c74566
-	0x7677a553	0x19698ac3	0xedca0620	0x77f32470
-	0x031e011b	0x751f6696	0xb277d06e	0x3eae2742
-	0x133e621a	0x38fa3172	0x9398cc1c	0xf42a507b
-	0x4547d933	0x63a91eb0	0xf5bcf6a4	0x926ba056
-	0x0adf5bce	0x140f53e4	0x7ff6bb5c	0x87dd79ba
-	0xbba240ac	0x694f743d	0x709cdb20	0x5b4d4401
-	0xc9693610	0x55f9f268	0x1142bc3f	0xf8fe3689
-	0x04a93c4c	0x33dedc46	0xdc73c725	0x2f5ba264
-	0x5b7a6a69	0x024b64f5	0x6e8bfa12	0x62bf2aa7
-	0x520f5a07	0x3c7c4292	0xb7ad2613	0x1f78fc87
-	0xd5284e4e	0x2c730f33	0x8861e947	0x8bacef7d
-	0xbafa2608	0x14ed0b5b	0x3b9bfb02	0x24ced271
-	0x002b2941	0x22d4431c	0x855f4248	0x5ec46e29
-	0x6f1f42fb	0x5dd24fe0	0x290961f6	0xf392dbaf
-	0xa1a8d9c2	0x61e18f4e	0xfda59a70	0x5498daa5
-	0x5ae7ea6f	0xf058c635	0x6817ebee	0x8e30dc8b
-	0x7c8d79be	0x5fb15b9b	0xeed64741	0xe2642a94
-	0x680d7e6e	0x3cbad7aa	0x808c415f	0xe9323aa2
-	0xaadf5b25	0xf60abf13	0xd5c47967	0xc248d0b3
-	0x0f232cbd	0x84092449	0x5744384b	0x5e153ded
-	0x8bb19817	0x34430271	0x917d2315	0x1fc790c7
-	0xc21b5db6	0xec578b1f	0x903a286e	0xca0c59bc
-	0x03e95c7a	0x8c659e99	0x7b09da0a	0xd61e7517
-	0x90b1c519	0x8deac92c	0xf99c7bec	0xb6257d92
-	0x3d61c16e	0xebd58be0	0xb470e655	0xa44bbf4f
-	0xfebe5313	0x4662110a	0x5d42ccd9	0x140845ec
-	0xc80329a9	0x915ca966	0x71e33828	0xe46c870a
-	0x7da9a490	0x255544da	0xa20fb8df	0xf94062b3
-	0xb2df5870	0xebf31e88	0x6e723e2f	0xe6ba9cf1
-	0x7e7084c2	0x1782ac71	0x0a0b0127	0xe9234e38
-	0x881356d6	0xb27a54b6	0x5594730e	0x9a14bd8f
-	0x6dba7da9	0x1069e285	0x02a52798	0x61ea7d86
-	0x665b2572	0x29d41eb5	0x1d211169	0x1218b345
-	0xbfbd264c	0x5b8b0625	0xbbfdcf39	0x6768dfce
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-	0x89774a91	0xde67c55f	0x1f9816dc	0x1469a4c2
-	0x28240be2	0x5fd0ad14	0x0949db3a	0x451b94d3
-	0x637e6d49	0x8a4771c8	0xf65104b7	0xc3058c40
-	0x592fe4d0	0xe26129f0	0xe66e6ce9	0x26ab39b8
-	0x308da532	0x205afe77	0x6dc78664	0x84d4890f
-	0x9d49fcb0	0xcac8f2ed	0xe713d798	0xfed7c75b
-	0xe441a0d4	0xdf60df37	0xc2eed2f5	0x2d68b20e
-	0x7827c89a	0x9d4cb9f2	0xb8912cce	0x07516335
-	0x976ffbb6	0x5cd0de48	0xed716f54	0x6f3c9f7f
-	0x34cf42d1	0xc1027cbb	0xde67c065	0xe0a229af
-	0xfc8bd2e8	0xd62ca176	0x8bfb76b2	0x54a1388f
-	0xe0650bb6	0x6d60682b	0xe16cf130	0xbd7c3ca2
-	0xea642814	0xa25f4d44	0x27013786	0x7316aa38
-	0x571511c8	0xf1b6b789	0xb7bfe72b	0x8fd2652c
-	0xbfc7771a	0x51a2e551	0x3bd738c2	0x2698b495
-	0xec69a196	0xd5ecb5c4	0x9bd3224c	0x6d9ab4cf
-	0x326c9942	0x4d711191	0xde9be50a	0xa980ca0b
-	0xe8e59dd0	0x4439e4ae	0x35de914d	0xee499a84
-	0xd1ca0c9d	0xfe6ee96d	0x5b1f4fd0	0xabf0621a
-	0x0c8220c7	0xcb6dbb1e	0xa5116036	0xe858d3c3
-	0x728e3a56	0x3b33e818	0xbe2643c1	0x497bbcc7
-	0xeb369828	0x9a4a01be	0x8c7e72a6	0xaf052f25
-	0x8d3ca85b	0x4703e55e	0x45647d4c	0x86d1e3e8
-	0x40ab59f9	0x3259b195	0xf979a147	0xb8961870
-	0x88b024f9	0x366e26bc	0xd6811525	0x252910c2
-	0x4223a20e	0x7fc971a3	0x4a639bf3	0xb6550c3b
-	0xfe05e552	0xbdc98897	0x509923ff	0xf51a5abc
-	0xc6cc0891	0x61cdac05	0x03a68664	0x1b80cc76
-	0xe18d8ee1	0x798bb4d2	0xd7769bf9	0x9ab4c02d
-	0x7484774b	0xa9ee2c8b	0x87d34c85	0x15697682
-	0x9f6a4a55	0x9d7a731c	0x10014d6a	0xb9798070
-	0xd42f79cb	0x89db59b3	0xd5b0a0b6	0xf60864a5
-	0x2d6fb084	0x1cb607b2	0x48232701	0x9310cbc6
-	0x5bc81c98	0x6b25016c	0x2014b99d	0x0836e60b
-	0x0addbc4c	0x3b8bac7c	0x8d95ac77	0x1d56c3c7
-	0x58333104	0x3d6eb719	0x676eb951	0xd5c2d1a3
-	0x239dae86	0x92181ab8	0xbdde9741	0x7995d452
-	0xe0020661	0x2f80c8b7	0xeedcd4fc	0xe4bde175
-	0xb98fdf78	0x84b9228f	0x78ecb4f3	0xe99e5d46
-	0xa33b9b96	0xe2cbc71c	0xc19e2146	0xdc0ee758
-	0x2d8f8767	0x2036685b	0x149df155	0x2e7ab376
-	0xb13b4266	0xf5c8a3b0	0x02ca1e19	0x1badd81b
-	0xb9c1832a	0x73b31f75	0x69979b55	0x567070a2
-	0x2edeb3dc	0x26b55921	0x461df49f	0xc1aba883
-	0x25d6faec	0x5260e9bf	0xa8ccdd4c	0x04291961
-	0xfaf7a1b8	0xbc2d36e3	0xd6c86385	0x2757fbb9
-	0x62c7107c	0x87dac461	0x0c006454	0x0e971e49
-	0x4749afca	0x7f1fb389	0xdc0b69d3	0xc69fab09
-	0x12c372c9	0x78480a51	0x8ab03a94	0xb37022ca
-	0x1d00e893	0x0989de45	0x8c819503	0x8e0e1c06
-	0x11cfef86	0x3c2386a6	0x66c0e6c8	0x1befa478
-	0xd2e7a4a7	0x9a8b5917	0x2cfa1816	0xaf7e6c7a
-	0xd6c9f0ff	0x1aada3e0	0xbe36a471	0x5a91f3c7
-	0x6c61ea95	0x5246ef7c	0x20bc86c4	0xcfd87abd
-	0xdc61f595	0x8310a684	0x0477e35c	0xe59e776f
-	0xfa403863	0xdaf7bcb1	0xd6084825	0xb90bb047
-	0xeb9ff684	0x7223fbca	0x6b4af987	0x6b2553f8
-	0xdaabc6d2	0x82e2ebc3	0xa7c1c054	0x667eb0a7
-	0x53a0c7d4	0x3fcba743	0x38170187	0x2a2e5830
-	0xee134608	0xcd6e0112	0xac0831f9	0x9537d532
-	0x1e176b9c	0xe3fcb69f	0x17a2eee9	0xa9e6467f
-	0xbf6b0246	0x6a08c0fb	0x7fb943b6	0xb8f67c0e
-	0x2b3b4ffc	0xb155d20c	0x4eb5de53	0xf078715b
-	>;
diff --git a/arch/x86/dts/microcode/m0130673325.dtsi b/arch/x86/dts/microcode/m0130673325.dtsi
new file mode 100644
index 0000000..8063a75
--- /dev/null
+++ b/arch/x86/dts/microcode/m0130673325.dtsi
@@ -0,0 +1,3284 @@
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x325>;
+intel,date-code = <0x11192014>;
+intel,processor-signature = <0x30673>;
+intel,checksum = <0x5edcd570>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x25030000	0x14201911	0x73060300
+	0x70d5dc5e	0x01000000	0x01000000	0xd0cb0000
+	0x00cc0000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x25030000
+	0x00000000	0x00000000	0x19111420	0x11320000
+	0x01000000	0x73060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xf4320000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0xfff634fa	0x937ca2ab	0xb28d19b6	0xdefc54a7
+	0xd8df0b32	0x13e9a2a8	0x7b7cb24d	0xd588d3a7
+	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
+	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
+	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
+	0xc928c400	0x3add156d	0x531946f9	0x92a03216
+	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
+	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
+	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
+	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
+	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
+	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
+	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
+	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
+	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
+	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
+	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
+	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
+	0x11000000	0x1f504653	0xe21b5652	0xe97686b4
+	0x5f67c59f	0xa9b26fd4	0x9dc84f1a	0x0f02451e
+	0x0a821675	0x12547714	0xefe1084e	0x91260f23
+	0x17e46cf5	0x3dad6dd8	0x4e16210b	0x0472bd56
+	0xd3fca8a6	0xfa3f5184	0x87d91976	0xa7b008eb
+	0x17bad553	0x89835b41	0x32e7d87c	0xdfcf298a
+	0x6a740196	0x0405a296	0x4f830df5	0xfcf047f1
+	0xca0e7a10	0x8d0afa7b	0x08facdae	0xcf7bbe22
+	0x8e08e283	0x6b51333b	0x452cf734	0x03da5390
+	0x7075365b	0x402e71ba	0x4a8d4547	0x0da62d39
+	0x3fcae342	0xe8cb1437	0x6ddc21bd	0xe22b5edb
+	0x319decc1	0x6c558ad3	0x3b44648a	0x8cdf8642
+	0x5a3a8cdf	0x6aae06b2	0x7360d1a5	0x774351c9
+	0x88681d42	0x466d3573	0x6d8538cb	0xa3350f1e
+	0x7b431d3c	0x21074f32	0x6955a68f	0xa3988611
+	0xad1c79d3	0xe00884c6	0x12e5baa8	0x7dad4109
+	0x61d16a48	0xd2074a23	0x58611da6	0xad7b774e
+	0x90a80987	0x05aca95d	0x482b51ca	0xbb8fe27d
+	0x2abe5e48	0x590c8b98	0xef745dbf	0xce17a591
+	0x6607216b	0xbefec476	0x7a8b08a9	0xb281bfc4
+	0x76f7dc81	0xaacd78a8	0x38cd6888	0x9636aa2e
+	0x7035053d	0x069305f5	0x0da92823	0x46d344df
+	0xce46f308	0x1fcca5d0	0xf4b0daa0	0xed8ecd8e
+	0xdae9e33d	0x69be5bef	0xc545c95b	0xadeaeeb8
+	0xdd903783	0x5a2f3287	0x73865fd0	0x865d709d
+	0x1ed58537	0xe44c821a	0xc9ad0d97	0xe81b9851
+	0x552cf1e7	0x03a3b2dc	0x219194a0	0xd8875c82
+	0xe39b25b7	0x61149b84	0x79a99812	0x287eada3
+	0x057cc940	0x0ed85405	0xf4cbb20d	0x8d87a099
+	0x2018b6ae	0xd14f3646	0x35bf5bd8	0x82931be1
+	0x52234bd1	0x9143a967	0xd9d1a3d4	0x869c266c
+	0xcaff55f0	0x64ad39c2	0x02435da4	0x32e2907c
+	0xbc2682a9	0x60863cea	0x163028c0	0x007fc9fd
+	0x6553eb56	0xab00c11c	0x3aa77e22	0x87f722d4
+	0x004850a6	0x5460e040	0x9e91042c	0x46dd43c7
+	0x3b05c92f	0x060ce074	0x62730a12	0xc6d47872
+	0x03d26f06	0xf7b3d04f	0x92adc672	0xc31d8130
+	0xd40eab22	0x616b7f8f	0x56b2c742	0xde6015c3
+	0xc10c0d02	0x3ab28f97	0xa091494f	0x1fa0c28b
+	0xc76c5661	0x27effd8f	0x3de80c1e	0x5713a42c
+	0xd9114db2	0x17ab3314	0x0e3aea42	0x60712f1f
+	0x4a7d4389	0x9db1857c	0x1103baa8	0x579462a6
+	0x82ac5a7e	0xda8d9f67	0x835bed5a	0x08705479
+	0xbf4bd494	0x082d8b22	0x408878b0	0xa698e9d8
+	0x27fba6da	0x2308fb71	0xcc1b9c9c	0x5200bd18
+	0xf1baf601	0xe67b1d1b	0xf3c95153	0xf8fb4f22
+	0x2859e330	0x3e7bc864	0x02c88201	0xf835c5f7
+	0xcefd31e1	0x4c430b43	0xce13d99c	0xf9aa01ab
+	0x9f5c0d3a	0xbf06696f	0xc834c22c	0x145cf026
+	0xb45e1f1b	0x97302dd5	0x5b5d108a	0xffde5401
+	0xffbd2caf	0x8eb5c823	0x3f113711	0x144ec354
+	0xab3864a7	0xeee70354	0x208ea79c	0x1b2c7364
+	0xc3cb82d0	0x21d9b3bc	0x27846121	0x50bd8910
+	0x43a2616a	0xface9686	0xe12195b9	0xde4639d9
+	0x0b88b493	0x32b1685e	0xbd782bea	0xc674188e
+	0x23425d26	0x9d2d3c81	0x33b3a260	0x4ebebf2f
+	0x6a634d1f	0xb977b1c1	0x476223c5	0x654c5461
+	0xbeaa9c98	0x75242b30	0x26061148	0x69889154
+	0x910a2132	0x07df3136	0x372a7cf0	0x58541d8f
+	0x65ce78aa	0x0c6e4ff7	0xab8c31b6	0xbe39960d
+	0x63bc072d	0x53872b7c	0x959f3049	0xc13ba7a0
+	0xd7111cd7	0x5e68763f	0x923dc674	0xdb2e8a4d
+	0x5c2cd5e0	0xd93be0e2	0x1bccff32	0xbbdffc8a
+	0x1641ff1b	0xeab24fc7	0x70aff37e	0xc87fe4f8
+	0x32afd630	0x060dbdf9	0x6e119a8c	0x987e51c5
+	0x57abb8f6	0x15b3755b	0x938f709a	0x7c4b5522
+	0xfd376691	0xd909457d	0x58656778	0x3bdee518
+	0xaf65afd2	0xe1cd74ec	0xd2bc8a3a	0x9aa30f8b
+	0x6e1f183f	0xc2fa7bf8	0xa60385fd	0xe0320d46
+	0x2e5bc0df	0xf95b8c37	0xfa760bc7	0xc8960509
+	0xdebed2f2	0x560ac9de	0xb3ac0e62	0xefe328dc
+	0x358d5330	0x72c31526	0x5932780a	0xb3b824b4
+	0xda37daae	0x69dd74c1	0x41c91b5c	0x8180b956
+	0xc69574b5	0x1830993b	0x0d5ef14b	0xa8dec45f
+	0x5c4019ed	0x559e7b51	0xd07a3c14	0x49208a2b
+	0x5265dad8	0x1b9826c0	0xb8cc3edf	0x63ccaf33
+	0xdfdfb78b	0x3292f976	0x9f1ddbc1	0x2e3bfa8f
+	0xc4b5a941	0xd8b1fcea	0x68764a2c	0xbec828e1
+	0x07db4118	0x2022cfd1	0x6be82389	0x7ecb046a
+	0xd31a639f	0xa0f50a18	0xbb4dc035	0x765a6e5f
+	0x59fe51c8	0xd2138643	0xccfeebae	0x234c0440
+	0x49bcdabd	0x88e86cb6	0x48760e88	0xcc34f20c
+	0x0977dead	0xf3f0d324	0x736f4df6	0x0a94f658
+	0x0bbb01cb	0xe962549c	0x6a1c39c6	0xbec25a26
+	0x4cb71dd7	0xf1043105	0xba0f3726	0xc97645e3
+	0x23d4b508	0x7c0827ae	0x097f96f0	0x0a054e0a
+	0x79e7a543	0xbedbd7d1	0x52d2b51f	0xebabfee4
+	0x1f0e76e2	0xa07922a8	0x3a630243	0x41b8b460
+	0x11f8e1be	0x97ab45cf	0xd952588f	0x70461a90
+	0xdf62afd8	0x169cd499	0xc9a38028	0xe2d36ebf
+	0xa86477c5	0x1890d4fb	0xb78c189e	0x6002b07d
+	0x346599a1	0x998b8687	0xa073f3ff	0x561c2a62
+	0xc4904bcd	0x59a5194c	0x6b2d285d	0x3c7208dd
+	0x1a2e9b5e	0x7a7732a8	0x2c803c45	0xb307e8fe
+	0x9a402093	0x521740de	0xb25a372e	0x1abeec65
+	0xd9f84a17	0xed465fd4	0xfcc2e034	0xdc9bc727
+	0x9607ab7b	0xe0bd62d8	0x8630873a	0x361b3b75
+	0x603255fa	0xd815876b	0x32d0e705	0x5f99a520
+	0xf15a63b3	0x83f3009f	0x7ad4b916	0x1ba9093c
+	0x824dc86d	0xcd792af9	0x8d1e623d	0xad4877c1
+	0x2c09f508	0xab062540	0x242c5f5e	0xb46796bd
+	0x0bbc1a5d	0x02be8545	0x4ad68f23	0x370b4b1b
+	0xc16c7ebf	0x8b65ef74	0x11b64ded	0xc00f5586
+	0x41d6033a	0x0f79c8e9	0x356094c0	0xff3ec289
+	0x11a0d26f	0x347ebbef	0x23f2b11a	0xb6b15aca
+	0xe6856320	0xacecde47	0x513fbdea	0x7d7ac026
+	0xb72b0011	0x7d8cac25	0x222704f3	0xabc6b166
+	0x60995d26	0x95ccf438	0xce21d44f	0x27e15e98
+	0x9e229da5	0x929009b0	0xe79afdb0	0xf91bcab4
+	0xe5894312	0xe98d7607	0xb2bd2408	0x5abc5003
+	0x532b2c0a	0xb41dbdf7	0x248d6b00	0x7b811187
+	0xff7afcb3	0x818c2c38	0xacc7a704	0xaa14713a
+	0xeed076d3	0xcca8d4aa	0xd90177c0	0x9fcc01ae
+	0x8edd4189	0x1c896cfe	0xc4856a25	0xbeeb2217
+	0x52249b24	0xad45ff42	0xb43ae3a7	0x4bf0df57
+	0x91e369cf	0xcfafc488	0x6c218f44	0x0aab7b09
+	0x5f9c2410	0x87cdac03	0x986e83cd	0x56a7bba7
+	0xc7d2270b	0x467b995a	0x4b398fc4	0x64f04f87
+	0x30334708	0x8d0c7e49	0x69c792c2	0x725eba77
+	0x6870df0c	0x84d8a30c	0x0c5c6ac2	0xd9bc43cb
+	0xc52ab350	0x64878641	0xef306551	0xcfe54739
+	0x1aa176e8	0x6f1a7e1a	0x965be809	0x21e345f9
+	0x9ad41590	0x5e5de630	0x82cc1207	0x6120734f
+	0x846449fb	0x9d822218	0x2c8e025f	0x747f180c
+	0x90a64365	0xec79c646	0xaf2a29b0	0xb5a4cfa3
+	0x4f5b82de	0x0b7ad494	0x3b02b3e0	0xe5d96463
+	0x241aa4f3	0xefeeed3d	0x6e6d49ff	0x2d45821c
+	0x4598f881	0x7de00efb	0x25509321	0xc64ceb14
+	0x218dde9d	0x59c3cf6b	0xf8f702e6	0x3e0cf0c0
+	0x178f8a4a	0xc8aa3338	0xdcb7989d	0x297f30a0
+	0x270b7ea6	0xceff00a3	0x22ec287d	0x50673360
+	0x1fccbc8f	0x66c3805a	0x8a327234	0x52e1978f
+	0x538b121c	0x1f2fa957	0xeada2b4e	0x29423125
+	0x81d3a179	0x968b4097	0x3522324d	0x5cccf20c
+	0xa6adfc16	0x3d1cb3b9	0xbaefea60	0x57978720
+	0xf5eb4b9c	0x5a8b3acf	0x4f3ac467	0x94a7e4ca
+	0xb4100044	0x54fc2e4c	0x16ec9a22	0x3aecc34a
+	0x6df7f52a	0xe1279f5c	0xaa25ad1a	0x907baa13
+	0x51c19956	0x35987a2e	0x1adbb651	0xaf0a5285
+	0x83ce12f0	0xcbabf9e6	0xfaa1cbff	0x73139922
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+	0xebbd3208	0x89322dfb	0x925f82c7	0xebeef669
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+	0x30bd2849	0x252235cd	0xae7b84e6	0xb894640f
+	0x5b84fc6c	0x23f8cca0	0xd5a506ad	0x5605e837
+	>;
diff --git a/arch/x86/dts/microcode/m0130679901.dtsi b/arch/x86/dts/microcode/m0130679901.dtsi
deleted file mode 100644
index 11aaaa0..0000000
--- a/arch/x86/dts/microcode/m0130679901.dtsi
+++ /dev/null
@@ -1,3284 +0,0 @@
-/*
- * ---
- * This is a device tree fragment. Use #include to add these properties to a
- * node.
- *
- * Date:
- */
-
-compatible = "intel,microcode";
-intel,header-version = <1>;
-intel,update-revision = <0x901>;
-intel,date-code = <0x4212014>;
-intel,processor-signature = <0x30679>;
-intel,checksum = <0x69c4e6f1>;
-intel,loader-revision = <1>;
-intel,processor-flags = <0x1>;
-
-/* The first 48-bytes are the public header which repeats the above data */
-data = <
-	0x01000000	0x01090000	0x14202104	0x79060300
-	0xf1e6c469	0x01000000	0x01000000	0xd0cb0000
-	0x00cc0000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xa1000000	0x01000200	0x01090000
-	0x00000000	0x00000000	0x18041420	0x01320000
-	0x01000000	0x79060300	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xf4320000	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x3b6ec6fe	0xc0fda75e	0xb4ea6a9f	0x8fd6ed15
-	0xd537f374	0x669bf3bb	0xebedec72	0xb4cbc889
-	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
-	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
-	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
-	0xc928c400	0x3add156d	0x531946f9	0x92a03216
-	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
-	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
-	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
-	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
-	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
-	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
-	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
-	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
-	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
-	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
-	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
-	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
-	0x11000000	0xf03f27bc	0x3ed2262b	0xe1f8f63d
-	0xc164c68f	0x92e5df39	0x46108645	0x99a9968f
-	0x1dfa58a4	0xd1ebfd99	0xca4dae70	0xe466a06a
-	0x49575333	0xe30f49f0	0x814e5961	0xfa4bb7bd
-	0x2e212282	0x31912456	0x7d722c47	0x9cda0657
-	0x111985e9	0xd28d3b0b	0xec52f0c2	0x956b5b95
-	0x0806f491	0xa8096786	0x1e4c1248	0x42ea1ecf
-	0xea09d662	0xa821f68e	0x4b84d60a	0xa6f61348
-	0xfc95c139	0xebcebc32	0xd68ffe3e	0xa9aefabe
-	0xf653aafc	0x2a9f10e4	0xdaf3d51d	0x5f25aaa5
-	0xdedacabe	0xf2e08b12	0x6fb9f444	0x31b13d4e
-	0x13074cd3	0x68905491	0x08ce3a00	0xb3e5a3dc
-	0x9554ca97	0x5955c3a4	0x2e9951fd	0x5d708c9f
-	0xf3abe824	0xcb9105a1	0x3f51122e	0xd2152f23
-	0x2873cd28	0x463c0ff3	0x7bb81500	0xaa360665
-	0xbe69bdf9	0xa32415d6	0x111af68c	0xd129eaf6
-	0xdd102779	0x098a2b08	0x90363b85	0xdb5d3420
-	0xd1d116e3	0x9e5dd54e	0xb4a93d32	0xb5ee99fe
-	0x409f0bca	0x40302319	0xe175ddaa	0xfd7c8d00
-	0x2c28edb9	0x698d27f4	0x2e7945f1	0xc0150485
-	0xf9c599fc	0x139824cb	0x1571f70e	0x222565e8
-	0x3377eb7a	0x70fdee6f	0xd409f0a6	0xc875d05f
-	0x70d6a86b	0x66201d61	0xf8fcb733	0x14279707
-	0xc204e0e4	0x124c89be	0x8b298d1d	0x79bfe168
-	0xdbf7fe94	0x0358af09	0x8291ef8a	0x3e74a2ea
-	0xb7780782	0x0194d445	0x0bab231d	0xd76f85b2
-	0xc7510861	0x4b9a5c80	0x6c9c8583	0x4e18d7db
-	0x7dfeaea8	0x59be4d17	0x8e96f5b7	0x51bcb2da
-	0x5f3afeed	0xd3f46ecd	0x10da04eb	0x29dd87db
-	0xb7df24c5	0xd58dc2dc	0xede0603f	0xadf00cf7
-	0x50090b9f	0xc9130c82	0x854fc603	0x13b8b4be
-	0x10e2e41f	0x5c1d2246	0x0ee11843	0x6d38356d
-	0xd3bd47ae	0xb419f115	0xb118cac7	0x9c61aa7d
-	0xca22cf8a	0xd41af2f1	0x0b5ebfab	0xc0889746
-	0x078c705f	0x9e5b2b7a	0xb886ff49	0x1ab413e4
-	0x085cebc5	0xe3a44ab5	0x8844df92	0x075a79cf
-	0xb8fdc33b	0x1766265c	0x9340a734	0x4af860c9
-	0xa933586e	0x3e8a9a5c	0xf6419a1b	0xa70a1556
-	0xf930240e	0xe294fb1f	0x9bba35c5	0x4051819b
-	0x6799015f	0x7eb725ad	0x3953fe03	0xb8760679
-	0x54c7978c	0x3dfd36c2	0x631212bb	0xdeaca312
-	0x56d994dc	0x3a1696d1	0x214451fd	0x6dc505f7
-	0x7bbf210f	0xa266b569	0x8fb5eb6f	0xa6b76bf8
-	0xc9e782a1	0x8456765d	0x0a9eb223	0xa67e533f
-	0x211016f4	0xd8783c3e	0xc35574b8	0xd97e9b52
-	0x28ad2911	0xbffc5dad	0xd807d783	0x3050f3d1
-	0xcc33efa8	0xb9cf97c2	0xee5dfc8c	0x2adad5bb
-	0x4011c50b	0xa16f5d93	0x5e2ac188	0x521c977f
-	0x6af1b858	0xcd7e4b4c	0xfc988f66	0xc0e4cee9
-	0x82ac99ea	0x54353832	0x2308e02f	0xd084d198
-	0x03574ad5	0xbe4b698f	0xe1d7d294	0xd772d08d
-	0xb7a4fb2a	0xf7c93bb8	0x42fb2f4b	0x98cb1a11
-	0xf564f28e	0xd6ace35f	0xc43f6639	0x85be741d
-	0x079b8c1f	0xb5b45522	0xfedab918	0xf7fa7494
-	0x32204c16	0x1c8d5434	0xc39e58e4	0x99c7a2c4
-	0x3ccfbc3a	0x3f5ba9ef	0xf919921b	0xcffbeb79
-	0xd2927d86	0x5a50486d	0x62bdb218	0x22731dcd
-	0xbad1db2c	0x2f4af4a5	0x8f7eded6	0xeca3dcca
-	0x0bb5ecf7	0x05e6f3c6	0xa38cddff	0xc7cae177
-	0x1d115485	0x711ea542	0x33729cf9	0x59000680
-	0xcaf26070	0xd2647235	0x4ce354fc	0x76d9bdbe
-	0x53e39ec2	0x2d8acfb3	0x193c03b9	0xb3cef3ba
-	0x1da26bd5	0x8dfeeaa5	0xc199d90d	0xcfc8ee2d
-	0x4cb1bd52	0x521d197c	0x008bf34b	0xb6ff25ca
-	0xf4922b7c	0xa91893a8	0xbd3d7874	0x32865e72
-	0xca72c49d	0x02733201	0x6156051d	0x47464b81
-	0x353a3c14	0xa87475c8	0x9681a015	0x4b58832d
-	0xea65c6a2	0xfefef1fb	0xd5fa7dbf	0x13aeee80
-	0x2915b47b	0xe4a54fca	0x31615326	0xbad80f83
-	0x21eedfcc	0x2a2787da	0x6eaa2c9c	0x9de76356
-	0x8a34d823	0x2e7641b8	0xef16714d	0x8267bad4
-	0xacdfff45	0x09a93862	0xf63863de	0x7eec7d8b
-	0x70b4cf72	0xc7a8118c	0x4ed89774	0xc12a5e0d
-	0xe77cc023	0xcdee8fd8	0x20ffe6d9	0x88bcfaa0
-	0xd945e4fb	0xf496fccc	0xe7587e99	0x42252ec4
-	0xcc47d738	0xcc549ca3	0xd5059657	0xfbf502a5
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-	0xfe0e1e6a	0x46678478	0x230c0ef0	0x3add3053
-	0xa6a158c1	0x22c589d3	0x3b728538	0x5f78bfe8
-	0xab0bb3ab	0xb39e20b7	0xbb913a69	0xdf8bb73c
-	0xc2d5bb32	0xbd3e928c	0x30374965	0x9accaf18
-	0x60bb410e	0xa7786a6d	0xd368444d	0xc5eda57d
-	0x7a835abd	0x9f5f74e9	0x33b14a30	0xc0129833
-	0xc5d2e117	0x5f884f0f	0xae6fd2f7	0x3ef71ba2
-	0x0f0b944c	0x1a8dd932	0x2448f0ed	0xfb8ca949
-	0x9d08756f	0x7914384d	0xdd70f795	0x8cf8daff
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-	0x9f7d26db	0xd00816cd	0xec6e7b8b	0x0392bd20
-	0xfe4b6e2f	0x87795026	0xf9e4eef8	0x06cd2ec8
-	0x91670e6a	0x17aad6af	0x399050d1	0x043d05f8
-	0x5dd8e105	0xa2938113	0x2c47ea5e	0x64a062f8
-	0x14dd01cf	0x6773f479	0xf2b4a773	0xeefe3b89
-	0x8cf35404	0x0f02b236	0x430023ff	0x04ecae31
-	0x6949cdfb	0x65b63ba6	0x86c5a7c6	0xd53cc1b5
-	0xdc1ee770	0x30ebc654	0x67a95215	0x2e4508a9
-	0x9df37690	0x33baf9e5	0x9a58d5c0	0xe99baa0c
-	0x4b7446eb	0xfc7c8340	0xfa5ee60a	0xd1d873b4
-	0x302f882f	0xcff8ac83	0x56d809d2	0xcab281e6
-	0xadca5551	0x50691975	0x7766b753	0xdb7adecd
-	0x131c83af	0x1b09ee46	0x87fdd3ef	0xfe3037c2
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-	0x131a6a20	0x0fc1adf5	0x3707f20b	0x5d37ba20
-	0x6c8448e6	0x76f721a4	0x348b0456	0x608453ed
-	0xb1185c8a	0x18bbdaa1	0x7c1c6e05	0x46fa7cdf
-	0x390cf9b7	0xe9c825bf	0xf77554c5	0x7dd5a47c
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-	0xaabda9b0	0xe7ac02e7	0x0a1eb844	0x225686b2
-	0x7852c1cf	0x3912115d	0x89d65081	0xc3f4faee
-	0xfedeba97	0x073395d9	0x33d20ce3	0x56c6c126
-	0x378f822e	0xf575b487	0x043da151	0x1ccae8c2
-	0x5fa2279b	0x0608f618	0x4c90662b	0x30591d0c
-	0xcf217166	0xacdbf6fe	0x1a653b17	0x6fa76090
-	0xc804480e	0x44c5b06b	0x1ebb8a6d	0x2f6f6f08
-	0x6bbeb75c	0x21c5c48d	0xd4c4cc2d	0xfdeab68f
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-	0x9cfd1d10	0x81dbc61d	0x51702e45	0x8f80e492
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-	0xbd3e7a14	0xee191486	0xb0077d2e	0x7345adcf
-	0xce36b2ea	0xc73aec7d	0x9278ac37	0xe07c6d96
-	0xf90f78a5	0x38f5584c	0x4941da80	0x67ff3048
-	0x3c263914	0x49656179	0x22f066a5	0x1f5a5e3e
-	0xce9ce83f	0x8e7446a2	0x85473d62	0xd7622673
-	0x3941bc22	0xf879d494	0x0936a517	0x2bba925e
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-	0x60c0f0d5	0x63f7f157	0xb23dd4f9	0x5a4fd86c
-	0x3851d435	0x483b98c7	0x71c55b1d	0x1931d219
-	0x7bd54621	0x108bb4af	0xa72c8b97	0x51d985e2
-	0x598a521e	0x7efcf984	0x69b02671	0x5746157d
-	0x60cfc339	0x629567fe	0x2236a93a	0x520d0094
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-	0xce0d1c02	0xdebd6473	0x580f141b	0xcd5a5e57
-	0x1c64cc23	0x53f8f9c7	0xcfb5b464	0xa4939b05
-	0xc0bb3066	0x37923d76	0xe5e9b428	0x6f4f2894
-	0xe5144757	0xa9cfdc46	0xe3448b78	0x7e0bac3a
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-	0x4355a93f	0x54dfcade	0x1a918a74	0x88eff191
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-	0x1d73de18	0x6417f141	0x9fdce4cd	0x8f72ccdd
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-	0xe5bdf477	0xd2dd9e46	0x1270838f	0x557f3bd2
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-	0xbc3a2d64	0x6523583c	0x70db0cf9	0xebdba06e
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-	0xed0fdf3b	0x279fc3ca	0x5a01f65c	0xc4ad1598
-	0x7a1fa09f	0xd12f97bf	0x34d99bad	0xfcecf69c
-	0x2b5567af	0x57a93cb3	0xfcf93005	0x3a403789
-	0xecaad383	0xc63fe190	0x5b8de563	0xbd9b876d
-	0xa20b875b	0x79db86f9	0x1917cad6	0xe925d5e9
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-	0x23fd2e08	0x7c2fceb7	0x119bfd3a	0x029faaba
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-	0x042c1237	0xcb1c852c	0x546f4d72	0x01b37ce2
-	0x20e30817	0x3fbd20d1	0x2ca11cc3	0x63cf6770
-	0xa65064ac	0x32d2cbab	0x9c1fb334	0x37c097ea
-	0x63ea10fd	0x7db8fc2f	0x8a4425dc	0x752ca318
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-	0xd804a9b7	0x18b7efa2	0x6daabb80	0xf098566e
-	0xb5df2af6	0x8f23ef8d	0xed7dac93	0x4fbed0de
-	0x929b870e	0x60b5c69b	0x5589cc4d	0x588914af
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-	0x95ac1b10	0x871261dd	0x79f33a8a	0x77383224
-	0x98b2480f	0x2df139d4	0xd753e53b	0xbad87b53
-	0x977cc17f	0xacc4bb71	0xbde6b5f2	0x206562ae
-	0xe0319086	0xcf903501	0x56ed1506	0x64f4556c
-	0xb90bbe0f	0x2def02e5	0x9b625a9b	0x96086cce
-	0x39d1d0ab	0x8c85c5d6	0xa8199040	0x23c770e2
-	0xf5303bd0	0x51a83607	0x5afa1989	0x8a81b4ff
-	0x1b24e6a4	0x4cb58014	0xbbee7d31	0x758271fd
-	0x259bc3f5	0xb3f9c6eb	0xbd8c4f86	0x66c27a35
-	0xa41c2904	0xc9848ce3	0x9ba21676	0x18f65508
-	0xe5637556	0x031e21c0	0xc09e3c77	0x5f10856f
-	0x9b3ea697	0xd8afe20b	0x447f5be1	0x5c4b1668
-	0x71f44cc1	0x8637d0c6	0xbd182081	0x1e4221b4
-	0xd312a403	0xf49d2c96	0x686ff9e1	0xa3f9b746
-	0x3caeae90	0xf2bfb131	0x5823eb37	0xcd4edc6d
-	0x3a7f65d8	0xbb4be9d3	0xd7939b2e	0x71d03a37
-	0xa30ff63a	0xde7ccb57	0x8ea031ba	0xbcb3994d
-	0x8018d6fb	0x1c7a3610	0xac900573	0x9ad05089
-	0xe2d17d5e	0x7816b9a7	0xffcca5c1	0x9faa9a0c
-	0xadbe99e6	0x06de7ee1	0xe4ac8981	0x29ef423c
-	0x32219ad2	0x806642b8	0x412ab076	0xfe4c5196
-	0x82c2507c	0xd58c7b7c	0xfe9edc9a	0x89e4c6e9
-	0x4f122269	0xf0aeb2f1	0x77f4fbc0	0xe6692464
-	0x6e64c198	0xaf79a455	0x01e2ed98	0x897ec1b0
-	0xf7a0dd35	0x92baec5e	0x93f17b7e	0xfbf82b90
-	0x168d32c5	0x741b61c0	0xb0f5b9b5	0x0557fb71
-	0xca937e89	0xad652a2b	0x9a2121c8	0x34d189ca
-	0x037dd1a3	0x3e650192	0x4defbaa7	0x06763750
-	0x48d4d1b4	0xda2af400	0x7df71d63	0x3e0b4c46
-	0x28c645bc	0x29b15428	0x34e10558	0x1166cdd6
-	0xc259a364	0xdc7e0f21	0xb02cee35	0x3055f39b
-	0xb77a50d2	0x2c143c84	0x7903e30c	0x018e20a8
-	0xf95b4a26	0x38c84311	0x1f0c3098	0x535a95e7
-	0x730214dd	0xb0f90f53	0x625fc5d1	0x2c1f2d76
-	0x7c9b5351	0x5cc285f4	0x0f63b5f4	0x90d59d57
-	0x140213fc	0xd21a74b7	0xf85fd83b	0xd9f21e94
-	0xbbefcd30	0x5091f90f	0x8d5c47fc	0x9455364a
-	0xef89f274	0x901af041	0x782cd03a	0x086f1f81
-	0xe09eb4db	0xf7a8146c	0x41898271	0xe8be480c
-	0xdfbac329	0x5fb899cd	0xfdca25e8	0xe994b3d8
-	0x2299ede3	0xc0341512	0x0128eb87	0xd5cff619
-	0x779bba38	0x1e986657	0xc22ac15c	0x919af309
-	0xd3cd1df4	0xb4b22d9a	0x210c0617	0x5723f9e0
-	0xb7b79328	0x613e738d	0x39057942	0x48d48958
-	0xf9d80cc0	0x16f69a5c	0x6d517734	0x012f07fa
-	0x7a8329e1	0x586b22c3	0xdd0d96b9	0x0c56d5f9
-	0x60410aa3	0xd1975446	0xd2c142fa	0xb13ba75b
-	0x0b046c21	0x03afb4e0	0x346f5dce	0xd108fa96
-	0xd1ca963c	0x73f5838a	0x4b4f734f	0xa1d430a7
-	0xd0cda381	0x64fecfee	0xc5048480	0xd3bfb251
-	0x088982f9	0x2383aaee	0x9b9c8f48	0x623f2132
-	0x0f5ae663	0x3c32959a	0xa1fd9ecc	0xf62d0e4c
-	0xe690d930	0x6be7a286	0x825d0066	0xe51094ca
-	0xc99affb8	0x832222ea	0xe7296513	0x2c040c86
-	0x35f62e4f	0x6f46ba84	0x25cdb0a3	0xe8b6ec22
-	0x5b6cf8d0	0xcfd85f8a	0xf0181633	0x5362c0b7
-	0x58955c60	0xc5a36973	0x874d04eb	0xa42a42df
-	0x4bd5d994	0xee6114f3	0x671ccecb	0xf0ae2422
-	0x70c98042	0xf9ed2a1a	0x6b60f0c9	0x04b13374
-	0x96fba002	0x8b481645	0x315198a2	0x65c80b9a
-	0x31475dd9	0xe95c5c3a	0xe3c22d43	0x12659565
-	0xabec6f96	0x9446e315	0xa6552f83	0x295e2596
-	0x8b6a2d9f	0x71efb10e	0x2d309912	0xe3dd2879
-	0xabd39f50	0xcfa94a90	0x61d282b7	0x062b246f
-	0x617b7162	0x3628fffd	0x93c8c8a5	0xaa44c72a
-	0x11b78bff	0x8259874a	0x186bbcfd	0x37bf7395
-	0x6f8582a7	0x65fdd21b	0x53106cb5	0xbfbe1e4a
-	0x1ed99eac	0x670b3763	0x245db7b2	0x7584d9be
-	0xc3472009	0x572bddab	0x17e7406c	0x79e0ea4e
-	0x74779fd3	0x92d0c51a	0x1808d006	0x46c1e76b
-	0x40e48bf4	0x61e17325	0x1d437ab2	0xacf51c38
-	0xc19eab2c	0x02957308	0x0bcc40bb	0xf603815f
-	0x9c666571	0x6a7d539f	0x57f3941b	0x7af81d5c
-	0xad1427b0	0xc188d623	0xac010003	0x1ff4cdf6
-	0xfa504446	0x6425ba6c	0x27ff69fa	0x26da5613
-	0xb6fc0a69	0x1155853e	0xbab81c6e	0x3dc17909
-	0x07b209d9	0x8b269554	0x73fc8781	0xfc1c2c82
-	0x572df087	0xb71bb5e5	0x55f9d202	0x6f525daf
-	0x117755f9	0x52cce1bb	0xa789ed0e	0x1313ca47
-	0xe8bdd878	0xc37e8dcb	0x53b971fc	0x43540a80
-	0x3d2384a7	0x25ac992d	0x7aef31c8	0xb1294afd
-	0xb0a34878	0x96e9ca1d	0x82a19bcd	0x08cd2bdf
-	0xd2681e35	0x2d32fa5f	0xc7c0c8b2	0xeecd089d
-	0x97404355	0x0b34539d	0x37ce4df3	0x599352dc
-	0x06734f29	0xf47ab5d8	0xb15ea9a4	0xfd92ed2f
-	0x9510bdbd	0xb740d34b	0xbac3e94a	0x52efbc03
-	0x40bd7acb	0x1bf83a4f	0x3d76c698	0x7e691383
-	0xec85e4ae	0x55e9a446	0x1fc3ab3b	0x6aea12fe
-	0x8fab4a84	0x69cd7328	0x935a7236	0xc3f59437
-	0xb73a7d8b	0xba0f54e0	0xe8e7aafc	0x6f82ade6
-	0xed6ccaf0	0xdfddc46c	0x0763fc3e	0x778e488f
-	0x0bcc4dce	0x8f919858	0xa7bc7d1a	0xd4954eea
-	0x517b5458	0x6c3f5835	0xd960f76d	0xf5be65a7
-	0x133666d9	0x4431f94f	0xccedf47d	0x6eb21ff8
-	0xb858dfef	0x15beefef	0x9a1b6b6a	0x64890eda
-	0x2a381329	0x660302bb	0xc65c001c	0x049a4be4
-	0xfca1b112	0xb081a099	0x3a2217f8	0xeea9a2ef
-	0x7719129c	0x7c915047	0xb3fe3e16	0xf1c31548
-	0xfa84a76b	0xd7af5b51	0x0de24c14	0x89a7263d
-	0x5a9dbffe	0x7ea90ae3	0xc21a2a1d	0x65ef3a3e
-	0x90fd1fa0	0x69aa0d9b	0xb44a5778	0x5ded34b3
-	0xa0d78617	0x91817661	0xf9541869	0xa0960273
-	0x024d891a	0xbc9f6d7a	0x630bac04	0xd186ffe5
-	0x0d60d640	0xc05e4701	0xba72d775	0xacec7c0c
-	0x1680e76d	0x6b153d69	0xbcbd60c1	0x3e1ed6c6
-	0x9705975b	0xaa3cc082	0xbdd723d0	0x7c0bbdd9
-	0x2bcf8414	0x787b2dea	0xaf923561	0xe4ad94a2
-	0xa85f83a1	0x1de0ddcf	0xd96f918b	0x617b1461
-	0xb1d3e386	0xe8d80b5d	0x40dad53e	0xcd8fb285
-	0x46fb4bae	0x2845c456	0x8b261251	0xf4923055
-	0x99d0db1e	0x0d7cc781	0x9bb20af6	0x7116d81c
-	0xd7f54821	0xba4eb2d0	0xaef6b275	0x3ca796cf
-	0x8807360c	0xd887484b	0x7066ec38	0xf7262152
-	0x5ede9cc5	0x6b8eb00c	0x5564b7af	0x4726dfd1
-	0x9421fe95	0xcc0ff9e5	0x10ca7e89	0xb76760e6
-	0x3da3a50a	0xf9cd3f82	0x1eb01d3c	0x13ae6371
-	0x129747e6	0xab223504	0x9978c7e9	0x1f7ce259
-	0xb17fb162	0xd1ac0e80	0xe04bfd17	0x197d9eac
-	0x59586a32	0x7436e8ef	0xc28b1ec5	0x83af0dc7
-	0x8382692e	0x17f04148	0x31ee5ad3	0xfe89b973
-	0x0148467a	0x1a6a16ef	0xb6400bcd	0x53ae7036
-	0x6b258693	0xb6edbeca	0x2ff0b686	0xe6f0c346
-	0x0e0ff99c	0x8d369a6e	0x7d10411d	0x2ebccabc
-	0xa67435d3	0xf9901563	0x363f164f	0xf01a1b15
-	0x93b6a10f	0x81f0c068	0x89b8423d	0x60eb711a
-	0x4e45bf98	0x24845e1e	0xda91d7f7	0x561e7ab1
-	0x51a183de	0x73bf29a6	0xcdb20f84	0x46d5ab3d
-	0xce01efbc	0x8d09be04	0xbf4aee2e	0xadf03a7b
-	0xbc454c61	0x83647148	0xec9e834a	0x11527826
-	0x2c7eb009	0xc6d7e3f4	0xbe8befd2	0xd3cc42a8
-	0x0442b41e	0x89643506	0xfd1dc572	0x74b340bc
-	0x686f6f6c	0x48b92189	0xe8f88be6	0xfc591dbf
-	0x8b453678	0xea1fd8cc	0x659d57d9	0xb501f90c
-	0xa6d6b031	0x182d8378	0xd6a8d690	0x6419c2b6
-	0x523d3089	0xc23c971c	0x43994015	0xa4b23066
-	0x831e6ca5	0x03c18610	0xd6d1f4b5	0x28978a3d
-	0xdc620eba	0xc1f86faa	0xf6c4d906	0xf06f85f3
-	0x232fa1bf	0xcf80cc2a	0x6599a5b2	0xc2d4cdad
-	0x0287eb92	0x5cdc4dd6	0x34a9b6d4	0x6d4b1324
-	0x6d21a837	0x00026037	0x80a225a8	0xad75b226
-	0x414a3741	0xb74d0962	0x363b24b5	0xb5044295
-	0x0a01c1a1	0x90a110c8	0x53bdeee5	0xad31aa53
-	0xfb85cc5f	0xdf80b0f3	0x7ad3cb0f	0xb5c68bd6
-	0x89185ff8	0x41544629	0xad5adfe7	0x39061752
-	0x2e9c106c	0xbf52a0df	0x9d2cef79	0x99eba49d
-	0x4459b32c	0xdc98fd7b	0xd81f2f74	0x8aa59f53
-	0x1817857f	0x5f79e3bf	0xc4b7c810	0x9e3a9ddc
-	0x724af115	0x121239e3	0x3c33c849	0xd8abb44d
-	0x600d67b7	0xeaa06b4c	0x20fe7ba6	0x502c684b
-	0xf212d37d	0x413d883a	0x5abc83ec	0x3112bb6e
-	0x27e1b3e0	0xf6dc8508	0xfe602c4f	0xa5b34bce
-	0x4d03d689	0xdacb23c2	0xa00fb513	0x78606ea8
-	0x8fd43ecf	0x90072d2a	0xfcc7b1b9	0x7ffec951
-	0x684bbc25	0xc21a0374	0x8f06a016	0x0e28dfea
-	0x40da3a00	0x8c73a059	0xc0d565ef	0x13bb6c81
-	0x6e27c2ec	0x2f4c9a43	0xae1b4513	0x9738b38a
-	0x5557c3e1	0xa292c6ab	0xd0f78cea	0xb96402f7
-	0x6c281a04	0x948787f9	0xe59f0714	0x6f130446
-	0x4b12e263	0xcae5e073	0x00f0e279	0x9b03c647
-	0x2a141b72	0x19d1e112	0x97b3b6df	0x3c2b6c82
-	0x5b119136	0x57e2084c	0xe954bc0d	0xcdfbfa78
-	0xadc6b571	0x010b9122	0x236676d6	0x2458c822
-	0xcbb8384a	0x662cfd01	0x096c50d2	0x4959676b
-	0xf8b59f31	0xad912a4d	0x2e87fa6e	0x30182092
-	0xc0bf2c01	0x02b4bfa7	0xdd208dac	0x4c174da2
-	>;
diff --git a/arch/x86/dts/microcode/m0130679907.dtsi b/arch/x86/dts/microcode/m0130679907.dtsi
new file mode 100644
index 0000000..30e2f9e
--- /dev/null
+++ b/arch/x86/dts/microcode/m0130679907.dtsi
@@ -0,0 +1,3284 @@
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x907>;
+intel,date-code = <0x11142015>;
+intel,processor-signature = <0x30679>;
+intel,checksum = <0x1bb67b21>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x07090000	0x15201411	0x79060300
+	0x217bb61b	0x01000000	0x01000000	0xd0cb0000
+	0x00cc0000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x07090000
+	0x00000000	0x00000000	0x13111520	0x01320000
+	0x01000000	0x79060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xf4320000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x9703f29f	0x1c68d65c	0x1f15f858	0x114237f4
+	0xfef8d172	0x363b5a9d	0x4c3d9e71	0x13ff68a0
+	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
+	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
+	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
+	0xc928c400	0x3add156d	0x531946f9	0x92a03216
+	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
+	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
+	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
+	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
+	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
+	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
+	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
+	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
+	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
+	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
+	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
+	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
+	0x11000000	0x46e87267	0x7c9db265	0x4ac824e5
+	0x94ed53c5	0x4b1bbf81	0x241a4da8	0xc3c5d866
+	0x186d6eed	0xba1e5092	0x3d19677c	0x82b56f7d
+	0x95d4d506	0xdccbbfb2	0xdc6be978	0x416dbe64
+	0xe591ce22	0x02987636	0x44858276	0xfbe3729a
+	0xee42767f	0xb415639f	0xbc959b72	0xa6919bec
+	0xb9e2d0c5	0x2fb1e39c	0x1ebae20a	0x9a3ce21a
+	0xebf72206	0x4020d73c	0x92674cff	0xbc607b8d
+	0x488d8dc0	0xd1d6f435	0x39e3ee1c	0x1ed65078
+	0x967d7a88	0xaa1b9f3b	0x38248bfe	0xb8a0aeb2
+	0x3b8e34fb	0x86dd48e5	0x887d7432	0x3a3a3faf
+	0xec556202	0x50ebe457	0x7676b9bf	0xe84604b0
+	0xcb26a17e	0x52c94055	0x6b39d618	0xa82d63dc
+	0xf583cafd	0x32107d4e	0x71d5aee8	0xad5956f2
+	0xad58e817	0xb6da62b3	0x66d63e32	0x00a13bc7
+	0x71233e63	0x326ef79d	0x2e3cf966	0x92b08830
+	0x42be3b3e	0xd49905d5	0x638b6a72	0xbeaa8cbf
+	0x5f28a0f8	0xff10578d	0x59a2d213	0x2919bc00
+	0x61398c7c	0x2a0865e3	0xf1a42982	0xa1e24984
+	0x2234d6c6	0xd6a9a013	0x79740c47	0x56cd5120
+	0xc4bb279e	0x707d1519	0x33b0445d	0xae3be614
+	0x3c3d5c9c	0x6eb115a9	0x4a2d5cbd	0x58718272
+	0xea01ac92	0x8a6e8d3e	0xadc4315a	0xc6ba0145
+	0x52363aac	0x4960bc5e	0x56a66f82	0xdb06eae9
+	0xbcf5c135	0xd59539a8	0x7b68c56f	0xe298be9c
+	0x8ac3c19a	0x3928fbea	0x4a72f2ab	0xbe32ec72
+	0x5928b934	0x6b56ff28	0xc8f2c78e	0x97d168ee
+	0x43381910	0xa592424e	0xb14ae0a8	0x46f724a8
+	0xded8973b	0x9f9100a2	0xd7cbb2b6	0x2db57173
+	0x217fd7ff	0xa85f3087	0x9e23192e	0xff8a0f31
+	0x86f1ddbf	0xcae0ea2d	0xcd0591a1	0x10733827
+	0x1758f010	0x38bfb48d	0xc0ec80d4	0x3a497694
+	0xe82c7b4a	0xf21a8a2a	0xc4ba866f	0xc88fbed8
+	0xe0e9a0f8	0x60ba6708	0x73fe95cf	0x46fab51f
+	0xab34c80f	0xcd06bd33	0xdee23ab5	0xbb405653
+	0x7948d7e8	0x88713e19	0xf3507645	0xc6cf938e
+	0xa690f2ed	0xa1603eaf	0x71688d1a	0x2fc9a057
+	0x3488d635	0x5f8eaa82	0x5c3ac4be	0xe15a8f69
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+	0x89ebde2f	0xd7b4e71c	0x6a1c8bb3	0xb9392201
+	0xc7a2191f	0xf180c19a	0xc3446d78	0x7f5f61c8
+	0xc6a251da	0xa27c507f	0x329133a1	0x0c951593
+	0x344ca56a	0x329dea98	0x73112997	0x32bc47a4
+	0xbeb18227	0xd3347aaf	0x1c481ab4	0x62606e69
+	0xe18da26b	0x8243c025	0xfe05b066	0xc1b0c590
+	0xd8c107ba	0x235b8c6a	0xac4fe894	0xa012810b
+	0x5470e6de	0x6f1217ae	0xcb099ad1	0x2b03655e
+	0x91f0b417	0xc21a1af4	0xb4a8c50e	0xa5988ed2
+	0x7f03fa1e	0xa0658a65	0x5532c4b3	0x1fdcfcec
+	0x17f41c26	0xd6b29efb	0x3411f331	0x1b774029
+	0x2ee2d094	0x9f5edaab	0xc644a9f3	0xdc4cf7b1
+	0xb6304748	0xb064cfca	0x89e4dbee	0xb1563a5e
+	0xd370bca8	0xe6cb17d8	0xbfcacc87	0x76940250
+	0xf2456a18	0x3c1873e4	0x0a3d7d0e	0xeb145eb9
+	0xe88a48fb	0x9413f290	0x626e4e00	0xb234a13b
+	0xcbf49379	0xcf600cee	0xc78891b8	0x799f8e80
+	0xdbf4e604	0x89860862	0x04fb77db	0x0fb1bf13
+	0x3b1aa906	0xadaf9a45	0x48526bf7	0x09d8ffb3
+	0xce751581	0x00e35b8d	0x0549e629	0x6d3cc316
+	0x3d8f300a	0xdcd790b5	0xde1ca316	0x737d5f31
+	0x171b2646	0x4798a85d	0xea36f650	0xcf889098
+	0xe4ec65b8	0x944637d3	0x019c8103	0x5fbdc21c
+	0xa61ebe77	0x74ea95a5	0x258eb8d1	0xf8c8c4d6
+	0x9a1edc66	0x9118b309	0x639ae9b5	0xd0c40735
+	0xc6ddec32	0x36d26a75	0x86018c99	0xe8bf66df
+	0xf345dba0	0x780670a3	0xe34e60fd	0x733ad4ba
+	0x2ef04d54	0xb1b9c41f	0x84cca1c2	0xaa09279b
+	0x34797d41	0xb93d4c70	0x919ce970	0xd0d6ec5e
+	0xdc70cc95	0xd89f4680	0x458cfd33	0xc257784b
+	0x29ec9364	0x8e717417	0x6d9732df	0xa3658440
+	0x8574b5c6	0xa58ebb8c	0x81bc4dea	0x1f396663
+	0x361dfd98	0x20b35a46	0x886a7e4c	0x69f0a1c5
+	0xd0b7de5f	0xbbc08761	0xa1cef991	0x084a8ea2
+	0x4df68c5b	0xb84b4b2e	0xd4bf1770	0x94b4f7c7
+	0x9906a752	0x878c7f1f	0x385b5a5e	0x99147c87
+	0x97c54a35	0xbacb57d4	0xf85f9733	0xb5d2c83f
+	0x4405f9f5	0x020260b5	0x5c0a8556	0xb623ad79
+	0x8d42a6a3	0x35ae5806	0x2c28a60d	0xa0200ee8
+	0xed9e0ece	0xb7e0442a	0x1ddf0e2b	0x26ceec5d
+	0xda397b2c	0xb073d9a2	0x9d856bbd	0x06e35ca8
+	0x6296193e	0x292dee18	0xf5a9bd7a	0xb62fe73f
+	0x95a8775f	0x1efc0fd0	0xf3338af4	0x06ccbe78
+	0xafb3f669	0xd9f7fe16	0x09beed63	0xa2f0bb3e
+	0x02f5c52f	0x24aee650	0xf715039b	0x3f566d89
+	0xd575429b	0x9d40207d	0xa89c7de9	0xde5157f0
+	0xd79025ae	0x4259c4b6	0x61e86217	0x6d2e3273
+	0x57b5c99d	0xa18edb02	0xf5f314be	0xfa58bf5f
+	0x581e95bb	0x04967c03	0x9187d903	0xdaf34bc3
+	0xa18e49f0	0xb7973963	0x2984967f	0x7332f94f
+	0x57e5a8b5	0xe6e0a6f8	0xbc08c39f	0xc9e73ad8
+	0x0ea113d8	0xa9cfdb06	0xfda1ebbb	0x1a30e9f9
+	0x69a9029a	0x44b43320	0x04182d93	0x00220972
+	0xa7f984c5	0xb4eeae8a	0x11718517	0x06e70840
+	0xb3091fe5	0x099ccb1a	0xac3df88c	0xa8bd0ca3
+	0xa202bbc0	0x19979cf1	0x8656c385	0x139abf7b
+	0xae298ea4	0xab9481ae	0xe08e2c38	0x27967dab
+	0x1108054c	0x1ba0d3c5	0x8a0fb923	0x9c54f682
+	0x5f363a46	0xec564b34	0x8d53c918	0x47f39642
+	0x3fd68743	0x197f16cc	0x2b03d11c	0xcc574d53
+	0x8b2d1aa3	0xd403c5b0	0xce21d3a6	0x57c88abe
+	0x56d6b12b	0x204f9ac8	0xfd44c338	0x18417de6
+	0x5582f0bf	0x7ea9d04f	0x7bdee65d	0x9fe3f5b5
+	0xa14edd82	0x8301f6ba	0x24bc737a	0x5c6e71a8
+	0xdb0d7fc2	0x243b6e99	0x3941f113	0xcaaa3674
+	0x1b25b686	0xfb219a33	0x1b122757	0x27298223
+	0x44cbb8ad	0xed4e6ef9	0xae338c2d	0xa8d231ee
+	0x9bc2d8f3	0xcecd4d27	0xe8ba9908	0x9a106344
+	0xbdf27147	0x0c547009	0x46b16833	0xd89b0690
+	0x4b742f40	0x733d4cd5	0x1abb6f77	0x803f40df
+	0xf8d909bb	0x8fa6a921	0x08966531	0xdf093174
+	0xc7ee92c8	0x4272612d	0x149f8242	0xf8c07ec3
+	0x99259781	0x8bf3f9c0	0x09d6b679	0x19a1968f
+	0x735b197e	0xa98c913f	0x3e208a56	0x59b2b40b
+	0x0ed212ed	0xfc92d02a	0xe9b1b441	0x1429fc3c
+	0x8a6fb38c	0x6235d73e	0x82f5aca8	0x9ebb490a
+	0x718fed05	0xee355cdc	0xf34bbc8e	0xcfde74ac
+	0x5c267a70	0x30b66c7f	0x9a655781	0x1d354268
+	0xd0debf01	0x71798948	0x4542b707	0x66c02ecf
+	0x49763e11	0xa02f170b	0xbcf30ee9	0xba9bbfec
+	0x6d915d18	0xcadd484f	0x8eadbd10	0x91463818
+	0xe8add34f	0x55620c30	0x14d47fa5	0x63c2a25f
+	0x7213f2f4	0x6d96a516	0xf10f4ed1	0x9825aeac
+	0xe9ca9b8a	0x4bb0e2aa	0x957f8851	0x1a41de29
+	0xa0039e6c	0x3ec63393	0x66b6ac8a	0x2992d983
+	0x2d73caa4	0xb0ae06c2	0xa4008915	0x2ba7050d
+	0x6d9e01e6	0x908f316f	0x3f17dabb	0x8c86b0e3
+	0x89fcebf8	0xbada4307	0x0f6e9f6f	0x07f36992
+	0x1a82520e	0x728f11a9	0x418aa9b7	0xc57f51d7
+	0xcffa1cd0	0xf9f6d902	0xdf22329a	0x4ac48293
+	0x37326e23	0xbb39c187	0xc9086dfe	0x1347e4f8
+	0x7ae88ecb	0xc280a07f	0x7f0a6b0a	0x57cff37d
+	0x2dfd629d	0x5a8a444d	0x934bcafb	0x593b6a3a
+	0x9c62c1ca	0x0ecdb2dc	0xb4c2fd82	0x2c19c0ab
+	0x26acf079	0x71aa1041	0x8aeb2595	0xed90f704
+	0x7d68f5c5	0x624429d5	0xefd0d147	0xc8682f79
+	0xfe7e9cc0	0xaee6c970	0x33e9231e	0x4720df4d
+	0x6a3f6428	0x463b676f	0x71960ee6	0xc684d974
+	0x9f01a6d2	0x728cbec7	0x2e20d715	0x172a4a11
+	0x4153ad1e	0xb1f36e53	0xc277f818	0x94ac6d39
+	0x502f91d8	0x3028b1ee	0x48390347	0x45a8b5af
+	0x2cb8095f	0x063cbe4a	0x07a53b3b	0xcfd08c80
+	0x81679803	0x9fa4726a	0xa682f4c8	0x4d90e8bf
+	>;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 60bd05a..936455b 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -117,6 +117,7 @@
 				compatible = "intel,irq-router";
 				intel,pirq-config = "ibase";
 				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
 				intel,pirq-link = <8 8>;
 				intel,pirq-mask = <0xdee0>;
 				intel,pirq-routing = <
@@ -297,10 +298,10 @@
 
 	microcode {
 		update@0 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
 		};
 		update@1 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
 		};
 	};
 
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 5d601b3..0d462a9 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -69,6 +69,8 @@
 			irq-router {
 				compatible = "intel,irq-router";
 				intel,pirq-config = "pci";
+				intel,actl-8bit;
+				intel,actl-addr = <0x44>;
 				intel,pirq-link = <0x60 8>;
 				intel,pirq-mask = <0x0e40>;
 				intel,pirq-routing = <
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
deleted file mode 100644
index 4872b92..0000000
--- a/arch/x86/include/asm/acpi.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * From coreboot
- *
- * Copyright (C) 2004 SUSE LINUX AG
- * Copyright (C) 2004 Nick Barker
- * Copyright (C) 2008-2009 coresystems GmbH
- * (Written by Stefan Reinauer <stepan@coresystems.de>)
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef __ASM_ACPI_H
-#define __ASM_ACPI_H
-
-#define RSDP_SIG		"RSD PTR "  /* RSDT pointer signature */
-#define ACPI_TABLE_CREATOR	"U-BootAC"  /* Must be exactly 8 bytes long! */
-#define OEM_ID			"U-Boot"    /* Must be exactly 6 bytes long! */
-#define ASLC			"U-Bo"      /* Must be exactly 4 bytes long! */
-
-/* 0 = S0, 1 = S1 ...*/
-int acpi_get_slp_type(void);
-void apci_set_slp_type(int type);
-
-#endif
diff --git a/arch/x86/include/asm/acpi/debug.asl b/arch/x86/include/asm/acpi/debug.asl
new file mode 100644
index 0000000..8e7b603
--- /dev/null
+++ b/arch/x86/include/asm/acpi/debug.asl
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/debug.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* POST register region */
+OperationRegion(X80, SystemIO, 0x80, 1)
+Field(X80, ByteAcc, NoLock, Preserve)
+{
+	P80, 8
+}
+
+/* Legacy serial port register region */
+OperationRegion(CREG, SystemIO, 0x3F8, 8)
+Field(CREG, ByteAcc, NoLock, Preserve)
+{
+	CDAT, 8,
+	CDLM, 8,
+	    , 8,
+	CLCR, 8,
+	CMCR, 8,
+	CLSR, 8
+}
+
+/* DINI - Initialize the serial port to 115200 8-N-1 */
+Method(DINI)
+{
+	Store(0x83, CLCR)
+	Store(0x01, CDAT)	/* 115200 baud (low) */
+	Store(0x00, CDLM)	/* 115200 baud (high) */
+	Store(0x03, CLCR)	/* word=8 stop=1 parity=none */
+	Store(0x03, CMCR)	/* DTR=1 RTS=1 out1/2=Off loop=Off */
+	Store(0x00, CDLM)	/* turn off interrupts */
+}
+
+/* THRE - Wait for serial port transmitter holding register to go empty */
+Method(THRE)
+{
+	And(CLSR, 0x20, Local0)
+	While (LEqual(Local0, Zero)) {
+		And(CLSR, 0x20, Local0)
+	}
+}
+
+/* OUTX - Send a single raw character */
+Method(OUTX, 1)
+{
+	THRE()
+	Store(Arg0, CDAT)
+}
+
+/* OUTC - Send a single character, expanding LF into CR/LF */
+Method(OUTC, 1)
+{
+	If (LEqual(Arg0, 0x0a)) {
+		OUTX(0x0d)
+	}
+	OUTX(Arg0)
+}
+
+/* DBGN - Send a single hex nibble */
+Method(DBGN, 1)
+{
+	And(Arg0, 0x0f, Local0)
+	If (LLess(Local0, 10)) {
+		Add(Local0, 0x30, Local0)
+	} Else {
+		Add(Local0, 0x37, Local0)
+	}
+	OUTC(Local0)
+}
+
+/* DBGB - Send a hex byte */
+Method(DBGB, 1)
+{
+	ShiftRight(Arg0, 4, Local0)
+	DBGN(Local0)
+	DBGN(Arg0)
+}
+
+/* DBGW - Send a hex word */
+Method(DBGW, 1)
+{
+	ShiftRight(Arg0, 8, Local0)
+	DBGB(Local0)
+	DBGB(Arg0)
+}
+
+/* DBGD - Send a hex dword */
+Method(DBGD, 1)
+{
+	ShiftRight(Arg0, 16, Local0)
+	DBGW(Local0)
+	DBGW(Arg0)
+}
+
+/* Get a char from a string */
+Method(GETC, 2)
+{
+	CreateByteField(Arg0, Arg1, DBGC)
+	Return (DBGC)
+}
+
+/* DBGO - Send either a string or an integer */
+Method(DBGO, 1, Serialized)
+{
+	If (LEqual(ObjectType(Arg0), 1)) {
+		If (LGreater(Arg0, 0xffff)) {
+			DBGD(Arg0)
+		} Else {
+			If (LGreater(Arg0, 0xff)) {
+				DBGW(Arg0)
+			} Else {
+				DBGB(Arg0)
+			}
+		}
+	} Else {
+		Name(BDBG, Buffer(80) {})
+		Store(Arg0, BDBG)
+		Store(0, Local1)
+		While (One) {
+			Store(GETC(BDBG, Local1), Local0)
+			If (LEqual(Local0, 0)) {
+				Return (Zero)
+			}
+			OUTC(Local0)
+			Increment(Local1)
+		}
+	}
+
+	Return (Zero)
+}
diff --git a/arch/x86/include/asm/acpi/globutil.asl b/arch/x86/include/asm/acpi/globutil.asl
new file mode 100644
index 0000000..46381b6
--- /dev/null
+++ b/arch/x86/include/asm/acpi/globutil.asl
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/globutil.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Method(MIN, 2)
+{
+	If (LLess(Arg0, Arg1)) {
+		Return (Arg0)
+	} Else {
+		Return (Arg1)
+	}
+}
+
+Method(SLEN, 1)
+{
+	Store(Arg0, Local0)
+	Return (Sizeof(Local0))
+}
+
+Method(S2BF, 1, Serialized)
+{
+	Add(SLEN(Arg0), One, Local0)
+	Name(BUFF, Buffer(Local0) {})
+	Store(Arg0, BUFF)
+	Return (BUFF)
+}
+
+/*
+ * SCMP - Strong string compare
+ *
+ * Checks both length and content
+ */
+Method(SCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	Store(Zero, Local4)
+	Store(SLEN(Arg0), Local5)
+	Store(SLEN(Arg1), Local6)
+	Store(MIN(Local5, Local6), Local7)
+
+	While (LLess(Local4, Local7)) {
+		Store(Derefof(Index(Local0, Local4)), Local2)
+		Store(Derefof(Index(Local1, Local4)), Local3)
+		If (LGreater(Local2, Local3)) {
+			Return (One)
+		} Else {
+			If (LLess(Local2, Local3)) {
+				Return (Ones)
+			}
+		}
+		Increment(Local4)
+	}
+
+	If (LLess(Local4, Local5)) {
+		Return (One)
+	} Else {
+		If (LLess(Local4, Local6)) {
+			Return (Ones)
+		} Else {
+			Return (Zero)
+		}
+	}
+}
+
+/*
+ * WCMP - Weak string compare
+ *
+ * Checks to find Arg1 at beginning of Arg0.
+ * Fails if length(Arg0) < length(Arg1).
+ * Returns 0 on fail, 1 on pass.
+ */
+Method(WCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	If (LLess(SLEN(Arg0), SLEN(Arg1))) {
+		Return (Zero)
+	}
+	Store(Zero, Local2)
+	Store(SLEN(Arg1), Local3)
+
+	While (LLess(Local2, Local3)) {
+		If (LNotEqual(Derefof(Index(Local0, Local2)),
+			Derefof(Index(Local1, Local2)))) {
+			Return (Zero)
+		}
+		Increment(Local2)
+	}
+
+	Return (One)
+}
+
+/*
+ * I2BM - Returns Bit Map
+ *
+ * Arg0 = IRQ Number (0-15)
+ */
+Method(I2BM, 1)
+{
+	Store(0, Local0)
+	If (LNotEqual(Arg0, 0)) {
+		Store(1, Local1)
+		ShiftLeft(Local1, Arg0, Local0)
+	}
+
+	Return (Local0)
+}
diff --git a/arch/x86/include/asm/acpi/statdef.asl b/arch/x86/include/asm/acpi/statdef.asl
new file mode 100644
index 0000000..e8cff10
--- /dev/null
+++ b/arch/x86/include/asm/acpi/statdef.asl
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/statdef.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Status and notification definitions */
+
+#define STA_MISSING		0x00
+#define STA_PRESENT		0x01
+#define STA_ENABLED		0x03
+#define STA_DISABLED		0x09
+#define STA_INVISIBLE		0x0b
+#define STA_UNAVAILABLE		0x0d
+#define STA_VISIBLE		0x0f
+
+/* SMBus status codes */
+#define SMB_OK			0x00
+#define SMB_UNKNOWN_FAIL	0x07
+#define SMB_DEV_ADDR_NAK	0x10
+#define SMB_DEVICE_ERROR	0x11
+#define SMB_DEV_CMD_DENIED	0x12
+#define SMB_UNKNOWN_ERR		0x13
+#define SMB_DEV_ACC_DENIED	0x17
+#define SMB_TIMEOUT		0x18
+#define SMB_HST_UNSUPP_PROTOCOL	0x19
+#define SMB_BUSY		0x1a
+#define SMB_PKT_CHK_ERROR	0x1f
+
+/* Device Object Notification Values */
+#define NOTIFY_BUS_CHECK	0x00
+#define NOTIFY_DEVICE_CHECK	0x01
+#define NOTIFY_DEVICE_WAKE	0x02
+#define NOTIFY_EJECT_REQUEST	0x03
+#define NOTIFY_DEVICE_CHECK_JR	0x04
+#define NOTIFY_FREQUENCY_ERROR	0x05
+#define NOTIFY_BUS_MODE		0x06
+#define NOTIFY_POWER_FAULT	0x07
+#define NOTIFY_CAPABILITIES	0x08
+#define NOTIFY_PLD_CHECK	0x09
+#define NOTIFY_SLIT_UPDATE	0x0b
+#define NOTIFY_SRA_UPDATE	0x0d
+
+/* Battery Device Notification Values */
+#define NOTIFY_BAT_STATUSCHG	0x80
+#define NOTIFY_BAT_INFOCHG	0x81
+#define NOTIFY_BAT_MAINTDATA	0x82
+
+/* Power Source Object Notification Values */
+#define NOTIFY_PWR_STATUSCHG	0x80
+#define NOTIFY_PWR_INFOCHG	0x81
+
+/* Thermal Zone Object Notification Values */
+#define NOTIFY_TZ_STATUSCHG	0x80
+#define NOTIFY_TZ_TRIPPTCHG	0x81
+#define NOTIFY_TZ_DEVLISTCHG	0x82
+#define NOTIFY_TZ_RELTBLCHG	0x83
+
+/* Power Button Notification Values */
+#define NOTIFY_POWER_BUTTON	0x80
+
+/* Sleep Button Notification Values */
+#define NOTIFY_SLEEP_BUTTON	0x80
+
+/* Lid Notification Values */
+#define NOTIFY_LID_STATUSCHG	0x80
+
+/* Processor Device Notification Values */
+#define NOTIFY_CPU_PPCCHG	0x80
+#define NOTIFY_CPU_CSTATECHG	0x81
+#define NOTIFY_CPU_THROTLCHG	0x82
+
+/* User Presence Device Notification Values */
+#define NOTIFY_USR_PRESNCECHG	0x80
+
+/* Ambient Light Sensor Notification Values */
+#define NOTIFY_ALS_ILLUMCHG	0x80
+#define NOTIFY_ALS_COLORTMPCHG	0x81
+#define NOTIFY_ALS_RESPCHG	0x82
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 9856fa6..56aa282 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -2,83 +2,19 @@
  * Based on acpi.c from coreboot
  *
  * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
 
-#include <common.h>
-#include <malloc.h>
-#include <asm/post.h>
-#include <linux/string.h>
-
-#define RSDP_SIG		"RSD PTR "	/* RSDT pointer signature */
-#define ACPI_TABLE_CREATOR	"UBOOT   "	/* Must be 8 bytes long! */
-#define OEM_ID			"UBOOT "	/* Must be 6 bytes long! */
-#define ASLC			"INTL"		/* Must be 4 bytes long! */
-
-#define OEM_REVISION	42
-#define ASL_COMPILER_REVISION	42
-
-/* IO ports to generate SMIs */
-#define APM_CNT			0xb2
-#define APM_CNT_CST_CONTROL	0x85
-#define APM_CNT_PST_CONTROL	0x80
-#define APM_CNT_ACPI_DISABLE	0x1e
-#define APM_CNT_ACPI_ENABLE	0xe1
-#define APM_CNT_MBI_UPDATE	0xeb
-#define APM_CNT_GNVS_UPDATE	0xea
-#define APM_CNT_FINALIZE	0xcb
-#define APM_CNT_LEGACY		0xcc
-#define APM_ST			0xb3
-
-/* Multiple Processor Interrupts */
-#define MP_IRQ_POLARITY_DEFAULT	0x0
-#define MP_IRQ_POLARITY_HIGH	0x1
-#define MP_IRQ_POLARITY_LOW	0x3
-#define MP_IRQ_POLARITY_MASK	0x3
-#define MP_IRQ_TRIGGER_DEFAULT	0x0
-#define MP_IRQ_TRIGGER_EDGE	0x4
-#define MP_IRQ_TRIGGER_LEVEL	0xc
-#define MP_IRQ_TRIGGER_MASK	0xc
-
-/*
- * Interrupt assigned for SCI in order to
- * create the ACPI MADT IRQ override entry
- */
-#define ACTL		0x00
-#define SCIS_MASK	0x07
-#define SCIS_IRQ9	0x00
-#define SCIS_IRQ10	0x01
-#define SCIS_IRQ11	0x02
-#define SCIS_IRQ20	0x04
-#define SCIS_IRQ21	0x05
-#define SCIS_IRQ22	0x06
-#define SCIS_IRQ23	0x07
-
-#define ACPI_REV_ACPI_1_0	1
-#define ACPI_REV_ACPI_2_0	1
-#define ACPI_REV_ACPI_3_0	2
-#define ACPI_REV_ACPI_4_0	3
-#define ACPI_REV_ACPI_5_0	5
+#define RSDP_SIG		"RSD PTR "	/* RSDP pointer signature */
+#define OEM_ID			"U-BOOT"	/* U-Boot */
+#define OEM_TABLE_ID		"U-BOOTBL"	/* U-Boot Table */
+#define ASLC_ID			"INTL"		/* Intel ASL Compiler */
 
 #define ACPI_RSDP_REV_ACPI_1_0	0
 #define ACPI_RSDP_REV_ACPI_2_0	2
 
-typedef struct acpi_gen_regaddr {
-	u8  space_id;	/* Address space ID */
-	u8  bit_width;	/* Register size in bits */
-	u8  bit_offset;	/* Register bit offset */
-	union {
-		/* Reserved in ACPI 2.0 - 2.0b */
-		u8  resv;
-		/* Access size in ACPI 2.0c/3.0/4.0/5.0 */
-		u8  access_size;
-	};
-	u32 addrl;	/* Register address, low 32 bits */
-	u32 addrh;	/* Register address, high 32 bits */
-} acpi_addr_t;
-
-
 /*
  * RSDP (Root System Description Pointer)
  * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum
@@ -87,7 +23,7 @@
 	char signature[8];	/* RSDP signature */
 	u8 checksum;		/* Checksum of the first 20 bytes */
 	char oem_id[6];		/* OEM ID */
-	u8 revision;		/* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0 */
+	u8 revision;		/* 0 for ACPI 1.0, others 2 */
 	u32 rsdt_address;	/* Physical address of RSDT (32 bits) */
 	u32 length;		/* Total RSDP length (incl. extended part) */
 	u64 xsdt_address;	/* Physical address of XSDT (64 bits) */
@@ -95,35 +31,8 @@
 	u8 reserved[3];
 };
 
-enum acpi_address_space_type {
-	ACPI_ADDRESS_SPACE_MEMORY = 0,	/* System memory */
-	ACPI_ADDRESS_SPACE_IO,		/* System I/O */
-	ACPI_ADDRESS_SPACE_PCI,		/* PCI config space */
-	ACPI_ADDRESS_SPACE_EC,		/* Embedded controller */
-	ACPI_ADDRESS_SPACE_SMBUS,	/* SMBus */
-	ACPI_ADDRESS_SPACE_PCC = 0x0a,	/* Platform Comm. Channel */
-	ACPI_ADDRESS_SPACE_FIXED = 0x7f	/* Functional fixed hardware */
-};
-
-/* functional fixed hardware */
-#define ACPI_FFIXEDHW_VENDOR_INTEL	1	/* Intel */
-#define ACPI_FFIXEDHW_CLASS_HLT		0	/* C1 Halt */
-#define ACPI_FFIXEDHW_CLASS_IO_HLT	1	/* C1 I/O then Halt */
-#define ACPI_FFIXEDHW_CLASS_MWAIT	2	/* MWAIT Native C-state */
-#define ACPI_FFIXEDHW_FLAG_HW_COORD	1	/* Hardware Coordination bit */
-#define ACPI_FFIXEDHW_FLAG_BM_STS	2	/* BM_STS avoidance bit */
-
-/* Access size definitions for Generic address structure */
-enum acpi_address_space_size {
-	ACPI_ACCESS_SIZE_UNDEFINED = 0,	/* Undefined (legacy reasons) */
-	ACPI_ACCESS_SIZE_BYTE_ACCESS = 1,
-	ACPI_ACCESS_SIZE_WORD_ACCESS = 2,
-	ACPI_ACCESS_SIZE_DWORD_ACCESS = 3,
-	ACPI_ACCESS_SIZE_QWORD_ACCESS = 4
-};
-
 /* Generic ACPI header, provided by (almost) all tables */
-typedef struct acpi_table_header {
+struct acpi_table_header {
 	char signature[4];	/* ACPI signature (4 ASCII characters) */
 	u32 length;		/* Table length in bytes (incl. header) */
 	u8 revision;		/* Table version (not ACPI version!) */
@@ -131,12 +40,12 @@
 	char oem_id[6];		/* OEM identification */
 	char oem_table_id[8];	/* OEM table identification */
 	u32 oem_revision;	/* OEM revision number */
-	char asl_compiler_id[4]; /* ASL compiler vendor ID */
-	u32 asl_compiler_revision; /* ASL compiler revision number */
-} acpi_header_t;
+	char aslc_id[4];	/* ASL compiler vendor ID */
+	u32 aslc_revision;	/* ASL compiler revision number */
+};
 
 /* A maximum number of 32 ACPI tables ought to be enough for now */
-#define MAX_ACPI_TABLES	32
+#define MAX_ACPI_TABLES		32
 
 /* RSDT (Root System Description Table) */
 struct acpi_rsdt {
@@ -150,103 +59,80 @@
 	u64 entry[MAX_ACPI_TABLES];
 };
 
-/* MCFG (PCI Express MMIO config space BAR description table) */
-struct acpi_mcfg {
-	struct acpi_table_header header;
-	u8 reserved[8];
+/* FADT Preferred Power Management Profile */
+enum acpi_pm_profile {
+	ACPI_PM_UNSPECIFIED = 0,
+	ACPI_PM_DESKTOP,
+	ACPI_PM_MOBILE,
+	ACPI_PM_WORKSTATION,
+	ACPI_PM_ENTERPRISE_SERVER,
+	ACPI_PM_SOHO_SERVER,
+	ACPI_PM_APPLIANCE_PC,
+	ACPI_PM_PERFORMANCE_SERVER,
+	ACPI_PM_TABLET
 };
 
-struct acpi_mcfg_mmconfig {
-	u32 base_address;
-	u32 base_reserved;
-	u16 pci_segment_group_number;
-	u8 start_bus_number;
-	u8 end_bus_number;
-	u8 reserved[4];
+/* FADT flags for p_lvl2_lat and p_lvl3_lat */
+#define ACPI_FADT_C2_NOT_SUPPORTED	101
+#define ACPI_FADT_C3_NOT_SUPPORTED	1001
+
+/* FADT Boot Architecture Flags */
+#define ACPI_FADT_LEGACY_FREE		0x00
+#define ACPI_FADT_LEGACY_DEVICES	(1 << 0)
+#define ACPI_FADT_8042			(1 << 1)
+#define ACPI_FADT_VGA_NOT_PRESENT	(1 << 2)
+#define ACPI_FADT_MSI_NOT_SUPPORTED	(1 << 3)
+#define ACPI_FADT_NO_PCIE_ASPM_CONTROL	(1 << 4)
+
+/* FADT Feature Flags */
+#define ACPI_FADT_WBINVD		(1 << 0)
+#define ACPI_FADT_WBINVD_FLUSH		(1 << 1)
+#define ACPI_FADT_C1_SUPPORTED		(1 << 2)
+#define ACPI_FADT_C2_MP_SUPPORTED	(1 << 3)
+#define ACPI_FADT_POWER_BUTTON		(1 << 4)
+#define ACPI_FADT_SLEEP_BUTTON		(1 << 5)
+#define ACPI_FADT_FIXED_RTC		(1 << 6)
+#define ACPI_FADT_S4_RTC_WAKE		(1 << 7)
+#define ACPI_FADT_32BIT_TIMER		(1 << 8)
+#define ACPI_FADT_DOCKING_SUPPORTED	(1 << 9)
+#define ACPI_FADT_RESET_REGISTER	(1 << 10)
+#define ACPI_FADT_SEALED_CASE		(1 << 11)
+#define ACPI_FADT_HEADLESS		(1 << 12)
+#define ACPI_FADT_SLEEP_TYPE		(1 << 13)
+#define ACPI_FADT_PCI_EXPRESS_WAKE	(1 << 14)
+#define ACPI_FADT_PLATFORM_CLOCK	(1 << 15)
+#define ACPI_FADT_S4_RTC_VALID		(1 << 16)
+#define ACPI_FADT_REMOTE_POWER_ON	(1 << 17)
+#define ACPI_FADT_APIC_CLUSTER		(1 << 18)
+#define ACPI_FADT_APIC_PHYSICAL		(1 << 19)
+#define ACPI_FADT_HW_REDUCED_ACPI	(1 << 20)
+#define ACPI_FADT_LOW_PWR_IDLE_S0	(1 << 21)
+
+enum acpi_address_space_type {
+	ACPI_ADDRESS_SPACE_MEMORY = 0,	/* System memory */
+	ACPI_ADDRESS_SPACE_IO,		/* System I/O */
+	ACPI_ADDRESS_SPACE_PCI,		/* PCI config space */
+	ACPI_ADDRESS_SPACE_EC,		/* Embedded controller */
+	ACPI_ADDRESS_SPACE_SMBUS,	/* SMBus */
+	ACPI_ADDRESS_SPACE_PCC = 0x0a,	/* Platform Comm. Channel */
+	ACPI_ADDRESS_SPACE_FIXED = 0x7f	/* Functional fixed hardware */
 };
 
-/* MADT (Multiple APIC Description Table) */
-struct acpi_madt {
-	struct acpi_table_header header;
-	u32 lapic_addr;			/* Local APIC address */
-	u32 flags;			/* Multiple APIC flags */
-} acpi_madt_t;
-
-enum dev_scope_type {
-	SCOPE_PCI_ENDPOINT = 1,
-	SCOPE_PCI_SUB = 2,
-	SCOPE_IOAPIC = 3,
-	SCOPE_MSI_HPET = 4
+enum acpi_address_space_size {
+	ACPI_ACCESS_SIZE_UNDEFINED = 0,
+	ACPI_ACCESS_SIZE_BYTE_ACCESS,
+	ACPI_ACCESS_SIZE_WORD_ACCESS,
+	ACPI_ACCESS_SIZE_DWORD_ACCESS,
+	ACPI_ACCESS_SIZE_QWORD_ACCESS
 };
 
-typedef struct dev_scope {
-	u8 type;
-	u8 length;
-	u8 reserved[2];
-	u8 enumeration;
-	u8 start_bus;
-	struct {
-		u8 dev;
-		u8 fn;
-	} path[0];
-} __packed dev_scope_t;
-
-/* MADT: APIC Structure Type*/
-enum acpi_apic_types {
-	LOCALAPIC	= 0,	/* Processor local APIC */
-	IOAPIC,			/* I/O APIC */
-	IRQSOURCEOVERRIDE,	/* Interrupt source override */
-	NMITYPE,		/* NMI source */
-	LOCALNMITYPE, 		/* Local APIC NMI */
-	LAPICADDRESSOVERRIDE,	/* Local APIC address override */
-	IOSAPIC,		/* I/O SAPIC */
-	LOCALSAPIC,		/* Local SAPIC */
-	PLATFORMIRQSOURCES,	/* Platform interrupt sources */
-	LOCALX2SAPIC,		/* Processor local x2APIC */
-	LOCALX2APICNMI,		/* Local x2APIC NMI */
-};
-
-/* MADT: Processor Local APIC Structure */
-struct acpi_madt_lapic {
-	u8 type;		/* Type (0) */
-	u8 length;		/* Length in bytes (8) */
-	u8 processor_id;	/* ACPI processor ID */
-	u8 apic_id;		/* Local APIC ID */
-	u32 flags;		/* Local APIC flags */
-};
-
-#define LOCAL_APIC_FLAG_ENABLED	(1 << 0)
-/* bits 1-31: reserved */
-#define PCAT_COMPAT		(1 << 0)
-/* bits 1-31: reserved */
-
-/* MADT: Local APIC NMI Structure */
-struct acpi_madt_lapic_nmi {
-	u8 type;		/* Type (4) */
-	u8 length;		/* Length in bytes (6) */
-	u8 processor_id;	/* ACPI processor ID */
-	u16 flags;		/* MPS INTI flags */
-	u8 lint;		/* Local APIC LINT# */
-};
-
-/* MADT: I/O APIC Structure */
-struct acpi_madt_ioapic {
-	u8 type;		/* Type (1) */
-	u8 length;		/* Length in bytes (12) */
-	u8 ioapic_id;		/* I/O APIC ID */
-	u8 reserved;
-	u32 ioapic_addr;	/* I/O APIC address */
-	u32 gsi_base;		/* Global system interrupt base */
-};
-
-/* MADT: Interrupt Source Override Structure */
-struct acpi_madt_irqoverride {
-	u8 type;		/* Type (2) */
-	u8 length;		/* Length in bytes (10) */
-	u8 bus;			/* ISA (0) */
-	u8 source;		/* Bus-relative int. source (IRQ) */
-	u32 gsirq;		/* Global system interrupt */
-	u16 flags;		/* MPS INTI flags */
+struct acpi_gen_regaddr {
+	u8 space_id;	/* Address space ID */
+	u8 bit_width;	/* Register size in bits */
+	u8 bit_offset;	/* Register bit offset */
+	u8 access_size;	/* Access size */
+	u32 addrl;	/* Register address, low 32 bits */
+	u32 addrh;	/* Register address, high 32 bits */
 };
 
 /* FADT (Fixed ACPI Description Table) */
@@ -254,7 +140,7 @@
 	struct acpi_table_header header;
 	u32 firmware_ctrl;
 	u32 dsdt;
-	u8 model;
+	u8 res1;
 	u8 preferred_pm_profile;
 	u16 sci_int;
 	u32 smi_cmd;
@@ -309,85 +195,121 @@
 	struct acpi_gen_regaddr x_gpe1_blk;
 };
 
-/* Flags for p_lvl2_lat and p_lvl3_lat */
-#define ACPI_FADT_C2_NOT_SUPPORTED	101
-#define ACPI_FADT_C3_NOT_SUPPORTED	1001
-
-/* FADT Feature Flags */
-#define ACPI_FADT_WBINVD		(1 << 0)
-#define ACPI_FADT_WBINVD_FLUSH		(1 << 1)
-#define ACPI_FADT_C1_SUPPORTED		(1 << 2)
-#define ACPI_FADT_C2_MP_SUPPORTED	(1 << 3)
-#define ACPI_FADT_POWER_BUTTON		(1 << 4)
-#define ACPI_FADT_SLEEP_BUTTON		(1 << 5)
-#define ACPI_FADT_FIXED_RTC		(1 << 6)
-#define ACPI_FADT_S4_RTC_WAKE		(1 << 7)
-#define ACPI_FADT_32BIT_TIMER		(1 << 8)
-#define ACPI_FADT_DOCKING_SUPPORTED	(1 << 9)
-#define ACPI_FADT_RESET_REGISTER	(1 << 10)
-#define ACPI_FADT_SEALED_CASE		(1 << 11)
-#define ACPI_FADT_HEADLESS		(1 << 12)
-#define ACPI_FADT_SLEEP_TYPE		(1 << 13)
-#define ACPI_FADT_PCI_EXPRESS_WAKE	(1 << 14)
-#define ACPI_FADT_PLATFORM_CLOCK	(1 << 15)
-#define ACPI_FADT_S4_RTC_VALID		(1 << 16)
-#define ACPI_FADT_REMOTE_POWER_ON	(1 << 17)
-#define ACPI_FADT_APIC_CLUSTER		(1 << 18)
-#define ACPI_FADT_APIC_PHYSICAL		(1 << 19)
-/* Bits 20-31: reserved ACPI 3.0 & 4.0 */
-#define ACPI_FADT_HW_REDUCED_ACPI	(1 << 20)
-#define ACPI_FADT_LOW_PWR_IDLE_S0	(1 << 21)
-/* bits 22-31: reserved ACPI 5.0 */
-
-/* FADT Boot Architecture Flags */
-#define ACPI_FADT_LEGACY_DEVICES	(1 << 0)
-#define ACPI_FADT_8042			(1 << 1)
-#define ACPI_FADT_VGA_NOT_PRESENT	(1 << 2)
-#define ACPI_FADT_MSI_NOT_SUPPORTED	(1 << 3)
-#define ACPI_FADT_NO_PCIE_ASPM_CONTROL	(1 << 4)
-/* No legacy devices (including 8042) */
-#define ACPI_FADT_LEGACY_FREE		0x00
-
-/* FADT Preferred Power Management Profile */
-#define PM_UNSPECIFIED		0
-#define PM_DESKTOP		1
-#define PM_MOBILE		2
-#define PM_WORKSTATION		3
-#define PM_ENTERPRISE_SERVER	4
-#define PM_SOHO_SERVER		5
-#define PM_APPLIANCE_PC		6
-#define PM_PERFORMANCE_SERVER	7
-#define PM_TABLET		8	/* ACPI 5.0 */
-
-/* FACS (Firmware ACPI Control Structure) */
-struct acpi_facs {
-	char signature[4];			/* "FACS" */
-	u32 length;				/* Length in bytes (>= 64) */
-	u32 hardware_signature;			/* Hardware signature */
-	u32 firmware_waking_vector;		/* Firmware waking vector */
-	u32 global_lock;			/* Global lock */
-	u32 flags;				/* FACS flags */
-	u32 x_firmware_waking_vector_l;		/* X FW waking vector, low */
-	u32 x_firmware_waking_vector_h;		/* X FW waking vector, high */
-	u8 version;				/* ACPI 4.0: 2 */
-	u8 resv[31];				/* FIXME: 4.0: ospm_flags */
-};
-
 /* FACS flags */
 #define ACPI_FACS_S4BIOS_F	(1 << 0)
 #define ACPI_FACS_64BIT_WAKE_F	(1 << 1)
-/* Bits 31..2: reserved */
+
+/* FACS (Firmware ACPI Control Structure) */
+struct acpi_facs {
+	char signature[4];		/* "FACS" */
+	u32 length;			/* Length in bytes (>= 64) */
+	u32 hardware_signature;		/* Hardware signature */
+	u32 firmware_waking_vector;	/* Firmware waking vector */
+	u32 global_lock;		/* Global lock */
+	u32 flags;			/* FACS flags */
+	u32 x_firmware_waking_vector_l;	/* X FW waking vector, low */
+	u32 x_firmware_waking_vector_h;	/* X FW waking vector, high */
+	u8 version;			/* Version 2 */
+	u8 res1[3];
+	u32 ospm_flags;			/* OSPM enabled flags */
+	u8 res2[24];
+};
+
+/* MADT flags */
+#define ACPI_MADT_PCAT_COMPAT	(1 << 0)
+
+/* MADT (Multiple APIC Description Table) */
+struct acpi_madt {
+	struct acpi_table_header header;
+	u32 lapic_addr;			/* Local APIC address */
+	u32 flags;			/* Multiple APIC flags */
+};
+
+/* MADT: APIC Structure Type*/
+enum acpi_apic_types {
+	ACPI_APIC_LAPIC	= 0,		/* Processor local APIC */
+	ACPI_APIC_IOAPIC,		/* I/O APIC */
+	ACPI_APIC_IRQ_SRC_OVERRIDE,	/* Interrupt source override */
+	ACPI_APIC_NMI_SRC,		/* NMI source */
+	ACPI_APIC_LAPIC_NMI,		/* Local APIC NMI */
+	ACPI_APIC_LAPIC_ADDR_OVERRIDE,	/* Local APIC address override */
+	ACPI_APIC_IOSAPIC,		/* I/O SAPIC */
+	ACPI_APIC_LSAPIC,		/* Local SAPIC */
+	ACPI_APIC_PLATFORM_IRQ_SRC,	/* Platform interrupt sources */
+	ACPI_APIC_LX2APIC,		/* Processor local x2APIC */
+	ACPI_APIC_LX2APIC_NMI,		/* Local x2APIC NMI */
+};
+
+/* MADT: Processor Local APIC Structure */
+
+#define LOCAL_APIC_FLAG_ENABLED	(1 << 0)
+
+struct acpi_madt_lapic {
+	u8 type;		/* Type (0) */
+	u8 length;		/* Length in bytes (8) */
+	u8 processor_id;	/* ACPI processor ID */
+	u8 apic_id;		/* Local APIC ID */
+	u32 flags;		/* Local APIC flags */
+};
+
+/* MADT: I/O APIC Structure */
+struct acpi_madt_ioapic {
+	u8 type;		/* Type (1) */
+	u8 length;		/* Length in bytes (12) */
+	u8 ioapic_id;		/* I/O APIC ID */
+	u8 reserved;
+	u32 ioapic_addr;	/* I/O APIC address */
+	u32 gsi_base;		/* Global system interrupt base */
+};
+
+/* MADT: Interrupt Source Override Structure */
+struct __packed acpi_madt_irqoverride {
+	u8 type;		/* Type (2) */
+	u8 length;		/* Length in bytes (10) */
+	u8 bus;			/* ISA (0) */
+	u8 source;		/* Bus-relative int. source (IRQ) */
+	u32 gsirq;		/* Global system interrupt */
+	u16 flags;		/* MPS INTI flags */
+};
+
+/* MADT: Local APIC NMI Structure */
+struct __packed acpi_madt_lapic_nmi {
+	u8 type;		/* Type (4) */
+	u8 length;		/* Length in bytes (6) */
+	u8 processor_id;	/* ACPI processor ID */
+	u16 flags;		/* MPS INTI flags */
+	u8 lint;		/* Local APIC LINT# */
+};
+
+/* MCFG (PCI Express MMIO config space BAR description table) */
+struct acpi_mcfg {
+	struct acpi_table_header header;
+	u8 reserved[8];
+};
+
+struct acpi_mcfg_mmconfig {
+	u32 base_address_l;
+	u32 base_address_h;
+	u16 pci_segment_group_number;
+	u8 start_bus_number;
+	u8 end_bus_number;
+	u8 reserved[4];
+};
+
+/* PM1_CNT bit defines */
+#define PM1_CNT_SCI_EN		(1 << 0)
 
 /* These can be used by the target port */
 
-unsigned long acpi_create_madt_lapics(unsigned long current);
-int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
-			 u32 gsi_base);
-int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
-			 u8 bus, u8 source, u32 gsirq, u16 flags);
-unsigned long acpi_fill_madt(unsigned long current);
+void acpi_fill_header(struct acpi_table_header *header, char *signature);
 void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
-			 void *dsdt);
-int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu,
-			 u16 flags, u8 lint);
+		      void *dsdt);
+int acpi_create_madt_lapics(u32 current);
+int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
+			    u32 addr, u32 gsi_base);
+int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
+				 u8 bus, u8 source, u32 gsirq, u16 flags);
+int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
+			       u8 cpu, u16 flags, u8 lint);
+u32 acpi_fill_madt(u32 current);
 u32 write_acpi_tables(u32 start);
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
new file mode 100644
index 0000000..ef340f3
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* SouthCluster GPIO */
+Device (GPSC)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 1)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_SC_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
+
+/* NorthCluster GPIO */
+Device (GPNC)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 2)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_NC_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
+
+/* SUS GPIO */
+Device (GPSS)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 3)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_SUS_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h b/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
new file mode 100644
index 0000000..2c3585a
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronics Engineering, LLC.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file intentionally gets included multiple times, to set pic and apic
+ * modes, so should not have guard statements added.
+ */
+
+/*
+ * This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ
+ * routing for the platform being compiled.
+ *
+ * This method uses #defines in irqroute.h along with the macros contained
+ * in this file to generate an IRQ routing for each PCI device in the system.
+ */
+
+#undef PCI_DEV_PIRQ_ROUTES
+#undef PCI_DEV_PIRQ_ROUTE
+#undef ACPI_DEV_IRQ
+#undef PCIE_BRIDGE_DEV
+#undef RP_IRQ_ROUTES
+#undef ROOTPORT_METHODS
+#undef ROOTPORT_IRQ_ROUTES
+#undef RP_METHOD
+
+#if defined(PIC_MODE)
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+	Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## P, Package() \
+{ \
+	ACPI_DEV_IRQ(0x0000, 0, a_), \
+	ACPI_DEV_IRQ(0x0000, 1, b_), \
+	ACPI_DEV_IRQ(0x0000, 2, c_), \
+	ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+/* define as blank so ROOTPORT_METHODS only gets inserted once */
+#define ROOTPORT_METHODS(prefix_, dev_)
+
+#else /* defined(PIC_MODE) */
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+	Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## A, Package() \
+{ \
+	ACPI_DEV_IRQ(0x0000, 0, a_), \
+	ACPI_DEV_IRQ(0x0000, 1, b_), \
+	ACPI_DEV_IRQ(0x0000, 2, c_), \
+	ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+#define ROOTPORT_METHODS(prefix_, dev_) \
+	RP_METHOD(prefix_, dev_, 0) \
+	RP_METHOD(prefix_, dev_, 1) \
+	RP_METHOD(prefix_, dev_, 2) \
+	RP_METHOD(prefix_, dev_, 3) \
+	RP_METHOD(prefix_, dev_, 4) \
+	RP_METHOD(prefix_, dev_, 5) \
+	RP_METHOD(prefix_, dev_, 6) \
+	RP_METHOD(prefix_, dev_, 7)
+
+#endif /* defined(PIC_MODE) */
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+	ACPI_DEV_IRQ(dev_, 0, a_), \
+	ACPI_DEV_IRQ(dev_, 1, b_), \
+	ACPI_DEV_IRQ(dev_, 2, c_), \
+	ACPI_DEV_IRQ(dev_, 3, d_)
+
+#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
+	ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+	ROOTPORT_METHODS(prefix_, dev_)
+
+#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
+	RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
+	RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
+	RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
+	RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
+	RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
+
+#define RP_METHOD(prefix_, dev_, func_)\
+Device (prefix_ ## 0 ## func_) \
+{ \
+	Name(_ADR, dev_ ## 000 ## func_) \
+	Name(_PRW, Package() { 0, 0 }) \
+	Method(_PRT) { \
+		If (PICM) { \
+			Return (prefix_ ## func_ ## A) \
+		} Else { \
+			Return (prefix_ ## func_ ## P) \
+		} \
+	} \
+}
+
+/* SoC specific PIRQ route configuration */
+#include "irqroute.h"
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
new file mode 100644
index 0000000..0affa23
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
@@ -0,0 +1,493 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Scope (\)
+{
+	/* Intel Legacy Block */
+	OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+	Field(ILBS, AnyAcc, NoLock, Preserve) {
+		Offset (0x8),
+		PRTA, 8,
+		PRTB, 8,
+		PRTC, 8,
+		PRTD, 8,
+		PRTE, 8,
+		PRTF, 8,
+		PRTG, 8,
+		PRTH, 8,
+		Offset (0x88),
+		    , 3,
+		UI3E, 1,
+		UI4E, 1
+	}
+}
+
+Device (LNKA)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 1)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTA)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLA, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLA, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTA */
+		ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+		Return (RTLA)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTA)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTA, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKB)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 2)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTB)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLB, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLB, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTB */
+		ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+		Return (RTLB)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTB)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTB, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKC)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 3)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTC)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLC, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLC, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTC */
+		ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+		Return (RTLC)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTC)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTC, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKD)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 4)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTD)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLD, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLD, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTD */
+		ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+		Return (RTLD)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTD)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTD, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKE)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 5)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTE)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLE, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLE, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTE */
+		ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
+
+		Return (RTLE)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTE)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTE, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKF)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 6)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTF)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLF, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLF, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTF */
+		ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
+
+		Return (RTLF)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTF)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTF, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKG)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 7)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTG)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLG, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLG, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTG */
+		ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
+
+		Return (RTLG)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTG)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTG, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKH)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 8)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTH)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLH, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLH, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTH */
+		ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
+
+		Return (RTLH)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTH)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTH, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl
new file mode 100644
index 0000000..64d3820
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Name(\PICM, 0)
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local APIC/IOAPIC configuration.
+ */
+Method(\_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice */
+	Store(Arg0, PICM)
+}
+
+/* PCI interrupt routing */
+Method(_PRT) {
+	If (PICM) {
+		Return (Package() {
+			#undef PIC_MODE
+			#include "irq_helper.h"
+			PCI_DEV_PIRQ_ROUTES
+		})
+	} Else {
+		Return (Package() {
+			#define PIC_MODE
+			#include "irq_helper.h"
+			PCI_DEV_PIRQ_ROUTES
+		})
+	}
+
+}
+
+/* PCIe downstream ports interrupt routing */
+PCIE_BRIDGE_IRQ_ROUTES
+#undef PIC_MODE
+#include "irq_helper.h"
+PCIE_BRIDGE_IRQ_ROUTES
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h
new file mode 100644
index 0000000..d746314
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(GFX_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(EMMC_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SDIO_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SD_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SATA_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(XHCI_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(LPE_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(MMC45_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SIO1_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(TXE_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(HDA_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(PCIE_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(EHCI_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SIO2_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(PCU_DEV,	A, B, C, D)
+
+#define PCIE_BRIDGE_IRQ_ROUTES \
+	PCIE_BRIDGE_DEV(RP, PCIE_DEV,	A, B, C, D)
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
new file mode 100644
index 0000000..385671c
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPCB)
+{
+	Name(_ADR, 0x001f0000)
+
+	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
+	Field(LPC0, AnyAcc, NoLock, Preserve) {
+		Offset(0x08),
+		SRID, 8,
+		Offset(0x80),
+		C1EN, 1,
+		Offset(0x84)
+	}
+
+	#include "irqlinks.asl"
+
+	/* Firmware Hub */
+	Device (FWH)
+	{
+		Name(_HID, EISAID("INT0800"))
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+		})
+	}
+
+	/* 8259 Interrupt Controller */
+	Device (PIC)
+	{
+		Name(_HID, EISAID("PNP0000"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x20, 0x20, 0x01, 0x02)
+			IO(Decode16, 0x24, 0x24, 0x01, 0x02)
+			IO(Decode16, 0x28, 0x28, 0x01, 0x02)
+			IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
+			IO(Decode16, 0x30, 0x30, 0x01, 0x02)
+			IO(Decode16, 0x34, 0x34, 0x01, 0x02)
+			IO(Decode16, 0x38, 0x38, 0x01, 0x02)
+			IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
+			IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
+			IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
+			IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
+			IO(Decode16, 0xac, 0xac, 0x01, 0x02)
+			IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
+			IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
+			IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
+			IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
+			IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+			IRQNoFlags () { 2 }
+		})
+	}
+
+	/* 8254 timer */
+	Device (TIMR)
+	{
+		Name(_HID, EISAID("PNP0100"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x40, 0x40, 0x01, 0x04)
+			IO(Decode16, 0x50, 0x50, 0x10, 0x04)
+			IRQNoFlags() { 0 }
+		})
+	}
+
+	/* HPET */
+	Device (HPET)
+	{
+		Name(_HID, EISAID("PNP0103"))
+		Name(_CID, 0x010CD041)
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
+		})
+
+		Method(_STA)
+		{
+			Return (STA_VISIBLE)
+		}
+	}
+
+	/* Internal UART */
+	Device (IURT)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 1)
+
+		Method(_STA, 0, Serialized)
+		{
+			/*
+			 * TODO:
+			 *
+			 * Need to hide the internal UART depending on whether
+			 * internal UART is enabled or not so that external
+			 * SuperIO UART can be exposed to system.
+			 */
+			Store(1, UI3E)
+			Store(1, UI4E)
+			Store(1, C1EN)
+			Return (STA_VISIBLE)
+
+		}
+
+		Method(_DIS, 0, Serialized)
+		{
+			Store(0, UI3E)
+			Store(0, UI4E)
+			Store(0, C1EN)
+		}
+
+		Method(_CRS, 0, Serialized)
+		{
+			Name(BUF0, ResourceTemplate()
+			{
+				IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+				IRQNoFlags() { 3 }
+			})
+
+			Name(BUF1, ResourceTemplate()
+			{
+				IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+				IRQNoFlags() { 4 }
+			})
+
+			If (LLessEqual(SRID, 0x04)) {
+				Return (BUF0)
+			} Else {
+				Return (BUF1)
+			}
+		}
+	}
+
+	/* Real Time Clock */
+	Device (RTC)
+	{
+		Name(_HID, EISAID("PNP0B00"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x70, 0x70, 1, 8)
+			/*
+			 * Disable as Windows doesn't like it, and systems
+			 * don't seem to use it
+			 */
+			/* IRQNoFlags() { 8 } */
+		})
+	}
+
+	/* LPC device: Resource consumption */
+	Device (LDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 2)
+
+		Name(RBUF, ResourceTemplate()
+		{
+			IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+			IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+			IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+		})
+
+		Method(_CRS, 0, NotSerialized)
+		{
+			Return (RBUF)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
new file mode 100644
index 0000000..6bc82ec
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+	Return (Package() {0, 0})
+}
+
+/* TODO: add CPU ASL support */
+
+Scope (\_SB)
+{
+	#include "southcluster.asl"
+
+	/* ACPI devices */
+	#include "gpio.asl"
+}
+
+/* Chipset specific sleep states */
+#include "sleepstates.asl"
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl
new file mode 100644
index 0000000..eb5ae76
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
+Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
+Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
new file mode 100644
index 0000000..34d3951
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Device (PCI0)
+{
+	Name(_HID, EISAID("PNP0A08"))	/* PCIe */
+	Name(_CID, EISAID("PNP0A03"))	/* PCI */
+
+	Name(_ADR, 0)
+	Name(_BBN, 0)
+
+	Name(MCRS, ResourceTemplate()
+	{
+		/* Bus Numbers */
+		WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+		/* IO Region 0 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+		/* PCI Config Space */
+		IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		/* IO Region 1 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+		/* VGA memory (0xa0000-0xbffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000, , , ASEG)
+
+		/* OPROM reserved (0xc0000-0xc3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000, , , OPR0)
+
+		/* OPROM reserved (0xc4000-0xc7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000, , , OPR1)
+
+		/* OPROM reserved (0xc8000-0xcbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000, , , OPR2)
+
+		/* OPROM reserved (0xcc000-0xcffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000, , , OPR3)
+
+		/* OPROM reserved (0xd0000-0xd3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000, , , OPR4)
+
+		/* OPROM reserved (0xd4000-0xd7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000, , , OPR5)
+
+		/* OPROM reserved (0xd8000-0xdbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000, , , OPR6)
+
+		/* OPROM reserved (0xdc000-0xdffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000, , , OPR7)
+
+		/* BIOS Extension (0xe0000-0xe3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000, , , ESG0)
+
+		/* BIOS Extension (0xe4000-0xe7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000, , , ESG1)
+
+		/* BIOS Extension (0xe8000-0xebfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000, , , ESG2)
+
+		/* BIOS Extension (0xec000-0xeffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000, , , ESG3)
+
+		/* System BIOS (0xf0000-0xfffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000, , , FSEG)
+
+		/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000, , , PMEM)
+
+		/* High PCI Memory Region */
+		QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000, , , UMEM)
+	})
+
+	Method(_CRS, 0, Serialized)
+	{
+		/* Update PCI resource area */
+		CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+		CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+		CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+		/*
+		 * Hardcode TOLM to 2GB for now as BayTrail FSP uses this value.
+		 *
+		 * TODO: for generic usage, read TOLM value from register, or
+		 * from global NVS (not implemented by U-Boot yet).
+		 */
+		Store(0x80000000, PMIN)
+		Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
+		Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+		/* Update High PCI resource area */
+		CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
+		CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
+		CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
+
+		/* Set base address to 48GB and allocate 16GB for PCI space */
+		Store(0xc00000000, UMIN)
+		Store(0x400000000, ULEN)
+		Add(UMIN, Subtract(ULEN, 1), UMAX)
+
+		Return (MCRS)
+	}
+
+	/* Device Resource Consumption */
+	Device (PDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 1)
+
+		Name(PDRS, ResourceTemplate() {
+			Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+			Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
+			Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
+			Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
+			Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
+			Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+			Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+			Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0, Serialized)
+		{
+			Return (PDRS)
+		}
+	}
+
+	Method(_OSC, 4)
+	{
+		/* Check for proper GUID */
+		If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+			/* Let OS control everything */
+			Return (Arg3)
+		} Else {
+			/* Unrecognized UUID */
+			CreateDWordField(Arg3, 0, CDW1)
+			Or(CDW1, 4, CDW1)
+			Return (Arg3)
+		}
+	}
+
+	/* LPC Bridge 0:1f.0 */
+	#include "lpc.asl"
+
+	/* USB EHCI 0:1d.0 */
+	#include "usb.asl"
+
+	/* USB XHCI 0:14.0 */
+	#include "xhci.asl"
+
+	/* IRQ routing for each PCI device */
+	#include "irqroute.asl"
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/usb.asl b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl
new file mode 100644
index 0000000..311f471
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* EHCI Controller 0:1d.0 */
+
+Device (EHC1)
+{
+	Name(_ADR, 0x001d0000)
+
+	/* Power Resources for Wake */
+	Name(_PRW, Package() { 13, 4 })
+
+	/* Highest D state in S3 state */
+	Name(_S3D, 2)
+
+	/* Highest D state in S4 state */
+	Name(_S4D, 2)
+
+	Device (HUB7)
+	{
+		Name(_ADR, 0x00000000)
+
+		Device(PRT1) { Name(_ADR, 1) }	/* USB Port 0 */
+		Device(PRT2) { Name(_ADR, 2) }	/* USB Port 1 */
+		Device(PRT3) { Name(_ADR, 3) }	/* USB Port 2 */
+		Device(PRT4) { Name(_ADR, 4) }	/* USB Port 3 */
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl
new file mode 100644
index 0000000..a5a4404
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+	Name(_ADR, 0x00140000)
+
+	/* Power Resources for Wake */
+	Name(_PRW, Package() { 13, 3 })
+
+	/* Highest D state in S3 state */
+	Name(_S3D, 3)
+
+	Device (RHUB)
+	{
+		Name(_ADR, 0x00000000)
+
+		Device (PRT1) { Name(_ADR, 1) }	/* USB Port 0 */
+		Device (PRT2) { Name(_ADR, 2) }	/* USB Port 1 */
+		Device (PRT3) { Name(_ADR, 3) }	/* USB Port 2 */
+		Device (PRT4) { Name(_ADR, 4) }	/* USB Port 3 */
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/device.h b/arch/x86/include/asm/arch-baytrail/device.h
new file mode 100644
index 0000000..798d35b
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/device.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DEVICE_H_
+#define _DEVICE_H_
+
+/*
+ * Internal PCI device numbers within the SoC.
+ *
+ * Note it must start with 0x_ prefix, as the device number macro will be
+ * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
+ */
+
+/* SoC transaction router */
+#define SOC_DEV		0x00
+
+/* Graphics and Display */
+#define GFX_DEV		0x02
+
+/* MIPI */
+#define MIPI_DEV	0x03
+
+/* EMMC Port */
+#define EMMC_DEV	0x10
+
+/* SDIO Port */
+#define SDIO_DEV	0x11
+
+/* SD Port */
+#define SD_DEV		0x12
+
+/* SATA */
+#define SATA_DEV	0x13
+
+/* xHCI */
+#define XHCI_DEV	0x14
+
+/* LPE Audio */
+#define LPE_DEV		0x15
+
+/* OTG */
+#define OTG_DEV		0x16
+
+/* MMC45 Port */
+#define MMC45_DEV	0x17
+
+/* Serial IO 1 */
+#define SIO1_DEV	0x18
+
+/* Trusted Execution Engine */
+#define TXE_DEV		0x1a
+
+/* HD Audio */
+#define HDA_DEV		0x1b
+
+/* PCIe Ports */
+#define PCIE_DEV	0x1c
+
+/* EHCI */
+#define EHCI_DEV	0x1d
+
+/* Serial IO 2 */
+#define SIO2_DEV	0x1e
+
+/* Platform Controller Unit */
+#define PCU_DEV		0x1f
+
+#endif /* _DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/iomap.h b/arch/x86/include/asm/arch-baytrail/iomap.h
new file mode 100644
index 0000000..62a9105
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/iomap.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BAYTRAIL_IOMAP_H_
+#define _BAYTRAIL_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS		CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE			0x10000000
+
+/* Temporary Base Address */
+#define TEMP_BASE_ADDRESS		0xfd000000
+
+/* Transactions in this range will abort */
+#define ABORT_BASE_ADDRESS		0xfeb00000
+#define ABORT_BASE_SIZE			0x00100000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS		0xfed00000
+#define HPET_BASE_SIZE			0x400
+
+/* SPI Bus */
+#define SPI_BASE_ADDRESS		0xfed01000
+#define SPI_BASE_SIZE			0x400
+
+/* Power Management Controller */
+#define PMC_BASE_ADDRESS		0xfed03000
+#define PMC_BASE_SIZE			0x400
+
+/* Power Management Unit */
+#define PUNIT_BASE_ADDRESS		0xfed05000
+#define PUNIT_BASE_SIZE			0x800
+
+/* Intel Legacy Block */
+#define ILB_BASE_ADDRESS		0xfed08000
+#define ILB_BASE_SIZE			0x400
+
+/* IO Memory */
+#define IO_BASE_ADDRESS			0xfed0c000
+#define  IO_BASE_OFFSET_GPSCORE		0x0000
+#define  IO_BASE_OFFSET_GPNCORE		0x1000
+#define  IO_BASE_OFFSET_GPSSUS		0x2000
+#define IO_BASE_SIZE			0x4000
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS		0xfed1c000
+#define RCBA_BASE_SIZE			0x400
+
+/* MODPHY */
+#define MPHY_BASE_ADDRESS		0xfef00000
+#define MPHY_BASE_SIZE			0x100000
+
+/* IO Port bases */
+#define ACPI_BASE_ADDRESS		0x0400
+#define ACPI_BASE_SIZE			0x80
+
+#define GPIO_BASE_ADDRESS		0x0500
+#define GPIO_BASE_SIZE			0x100
+
+#define SMBUS_BASE_ADDRESS		0xefa0
+
+#endif /* _BAYTRAIL_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/irq.h b/arch/x86/include/asm/arch-baytrail/irq.h
new file mode 100644
index 0000000..cd66f83
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/irq.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BAYTRAIL_IRQ_H_
+#define _BAYTRAIL_IRQ_H_
+
+#define PIRQA_APIC_IRQ			16
+#define PIRQB_APIC_IRQ			17
+#define PIRQC_APIC_IRQ			18
+#define PIRQD_APIC_IRQ			19
+#define PIRQE_APIC_IRQ			20
+#define PIRQF_APIC_IRQ			21
+#define PIRQG_APIC_IRQ			22
+#define PIRQH_APIC_IRQ			23
+
+/* The below IRQs are for when devices are in ACPI mode */
+#define LPE_DMA0_IRQ			24
+#define LPE_DMA1_IRQ			25
+#define LPE_SSP0_IRQ			26
+#define LPE_SSP1_IRQ			27
+#define LPE_SSP2_IRQ			28
+#define LPE_IPC2HOST_IRQ		29
+#define LPSS_I2C1_IRQ			32
+#define LPSS_I2C2_IRQ			33
+#define LPSS_I2C3_IRQ			34
+#define LPSS_I2C4_IRQ			35
+#define LPSS_I2C5_IRQ			36
+#define LPSS_I2C6_IRQ			37
+#define LPSS_I2C7_IRQ			38
+#define LPSS_HSUART1_IRQ		39
+#define LPSS_HSUART2_IRQ		40
+#define LPSS_SPI_IRQ			41
+#define LPSS_DMA1_IRQ			42
+#define LPSS_DMA2_IRQ			43
+#define SCC_EMMC_IRQ			44
+#define SCC_SDIO_IRQ			46
+#define SCC_SD_IRQ			47
+#define GPIO_NC_IRQ			48
+#define GPIO_SC_IRQ			49
+#define GPIO_SUS_IRQ			50
+/* GPIO direct / dedicated IRQs */
+#define GPIO_S0_DED_IRQ_0		51
+#define GPIO_S0_DED_IRQ_1		52
+#define GPIO_S0_DED_IRQ_2		53
+#define GPIO_S0_DED_IRQ_3		54
+#define GPIO_S0_DED_IRQ_4		55
+#define GPIO_S0_DED_IRQ_5		56
+#define GPIO_S0_DED_IRQ_6		57
+#define GPIO_S0_DED_IRQ_7		58
+#define GPIO_S0_DED_IRQ_8		59
+#define GPIO_S0_DED_IRQ_9		60
+#define GPIO_S0_DED_IRQ_10		61
+#define GPIO_S0_DED_IRQ_11		62
+#define GPIO_S0_DED_IRQ_12		63
+#define GPIO_S0_DED_IRQ_13		64
+#define GPIO_S0_DED_IRQ_14		65
+#define GPIO_S0_DED_IRQ_15		66
+#define GPIO_S5_DED_IRQ_0		67
+#define GPIO_S5_DED_IRQ_1		68
+#define GPIO_S5_DED_IRQ_2		69
+#define GPIO_S5_DED_IRQ_3		70
+#define GPIO_S5_DED_IRQ_4		71
+#define GPIO_S5_DED_IRQ_5		72
+#define GPIO_S5_DED_IRQ_6		73
+#define GPIO_S5_DED_IRQ_7		74
+#define GPIO_S5_DED_IRQ_8		75
+#define GPIO_S5_DED_IRQ_9		76
+#define GPIO_S5_DED_IRQ_10		77
+#define GPIO_S5_DED_IRQ_11		78
+#define GPIO_S5_DED_IRQ_12		79
+#define GPIO_S5_DED_IRQ_13		80
+#define GPIO_S5_DED_IRQ_14		81
+#define GPIO_S5_DED_IRQ_15		82
+/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */
+#define _GPIO_S0_DED_IRQ(slot)		GPIO_S0_DED_IRQ_##slot
+#define _GPIO_S5_DED_IRQ(slot)		GPIO_S5_DED_IRQ_##slot
+#define GPIO_S0_DED_IRQ(slot)		_GPIO_S0_DED_IRQ(slot)
+#define GPIO_S5_DED_IRQ(slot)		_GPIO_S5_DED_IRQ(slot)
+
+#endif /* _BAYTRAIL_IRQ_H_ */
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
index 15ccf9b..e036f74 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -295,6 +295,25 @@
 #define CBMEM_ID_NONE			0x00000000
 
 /**
+ * high_table_reserve() - reserve configuration table in high memory
+ *
+ * This reserves configuration table in high memory.
+ *
+ * @return:	always 0
+ */
+int high_table_reserve(void);
+
+/**
+ * high_table_malloc() - allocate configuration table in high memory
+ *
+ * This allocates configuration table in high memory.
+ *
+ * @bytes:	size of configuration table to be allocated
+ * @return:	pointer to configuration table in high memory
+ */
+void *high_table_malloc(size_t bytes);
+
+/**
  * write_coreboot_table() - write coreboot table
  *
  * This writes coreboot table at a given address.
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 3bc2ac2..7434f77 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -93,6 +93,10 @@
 	char *mrc_output;
 	unsigned int mrc_output_len;
 	ulong table;			/* Table pointer from previous loader */
+#ifdef CONFIG_SEABIOS
+	u32 high_table_ptr;
+	u32 high_table_limit;
+#endif
 };
 
 #endif
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 5b9e673..ddb529e 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -34,6 +34,8 @@
  *		IRQ N is available to be routed
  * @lb_bdf:	irq router's PCI bus/device/function number encoding
  * @ibase:	IBASE register block base address
+ * @actl_8bit:	ACTL register width is 8-bit (for ICH series chipset)
+ * @actl_addr:	ACTL register offset
  */
 struct irq_router {
 	int config;
@@ -41,6 +43,8 @@
 	u16 irq_mask;
 	u32 bdf;
 	u32 ibase;
+	bool actl_8bit;
+	int actl_addr;
 };
 
 struct pirq_routing {
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index dc90df2..e17f0bb 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -10,7 +10,7 @@
 obj-y += bios_interrupts.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= cmd_boot.o
-obj-y	+= coreboot_table.o
+obj-$(CONFIG_SEABIOS) += coreboot_table.o
 obj-$(CONFIG_EFI) += efi/
 obj-y	+= e820.o
 obj-y	+= gcc.o
@@ -31,7 +31,7 @@
 obj-y += sfi.o
 obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o
 obj-y	+= string.o
-ifndef CONFIG_QEMU_ACPI_TABLE
+ifndef CONFIG_QEMU
 obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
 endif
 obj-y	+= tables.o
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 790f6fb..ffb4678 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -2,6 +2,7 @@
  * Based on acpi.c from coreboot
  *
  * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
@@ -10,25 +11,92 @@
 #include <cpu.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
-#include <dm/lists.h>
 #include <asm/acpi_table.h>
-#include <asm/cpu.h>
-#include <asm/ioapic.h>
+#include <asm/io.h>
 #include <asm/lapic.h>
 #include <asm/tables.h>
-#include <asm/pci.h>
 
 /*
- * IASL compiles the dsdt entries and
- * writes the hex values to AmlCode array.
- * CamelCase cannot be handled here.
+ * IASL compiles the dsdt entries and writes the hex values
+ * to a C array AmlCode[] (see dsdt.c).
  */
 extern const unsigned char AmlCode[];
 
+static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
+			    struct acpi_xsdt *xsdt)
+{
+	memset(rsdp, 0, sizeof(struct acpi_rsdp));
+
+	memcpy(rsdp->signature, RSDP_SIG, 8);
+	memcpy(rsdp->oem_id, OEM_ID, 6);
+
+	rsdp->length = sizeof(struct acpi_rsdp);
+	rsdp->rsdt_address = (u32)rsdt;
+
+	/*
+	 * Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2
+	 *
+	 * Some OSes expect an XSDT to be present for RSD PTR revisions >= 2.
+	 * If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR
+	 * revision 0)
+	 */
+	if (xsdt == NULL) {
+		rsdp->revision = ACPI_RSDP_REV_ACPI_1_0;
+	} else {
+		rsdp->xsdt_address = (u64)(u32)xsdt;
+		rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
+	}
+
+	/* Calculate checksums */
+	rsdp->checksum = table_compute_checksum((void *)rsdp, 20);
+	rsdp->ext_checksum = table_compute_checksum((void *)rsdp,
+			sizeof(struct acpi_rsdp));
+}
+
+void acpi_fill_header(struct acpi_table_header *header, char *signature)
+{
+	memcpy(header->signature, signature, 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
+	memcpy(header->aslc_id, ASLC_ID, 4);
+}
+
+static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
+{
+	struct acpi_table_header *header = &(rsdt->header);
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "RSDT");
+	header->length = sizeof(struct acpi_rsdt);
+	header->revision = 1;
+
+	/* Entries are filled in later, we come with an empty set */
+
+	/* Fix checksum */
+	header->checksum = table_compute_checksum((void *)rsdt,
+			sizeof(struct acpi_rsdt));
+}
+
+static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
+{
+	struct acpi_table_header *header = &(xsdt->header);
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "XSDT");
+	header->length = sizeof(struct acpi_xsdt);
+	header->revision = 1;
+
+	/* Entries are filled in later, we come with an empty set */
+
+	/* Fix checksum */
+	header->checksum = table_compute_checksum((void *)xsdt,
+			sizeof(struct acpi_xsdt));
+}
+
 /**
-* Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
-* and checksum.
-*/
+ * Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
+ * and checksum.
+ */
 static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 {
 	int i, entries_num;
@@ -50,7 +118,7 @@
 	}
 
 	if (i >= entries_num) {
-		debug("ACPI: Error: too many tables.\n");
+		debug("ACPI: Error: too many tables\n");
 		return;
 	}
 
@@ -58,12 +126,13 @@
 	rsdt->entry[i] = (u32)table;
 
 	/* Fix RSDT length or the kernel will assume invalid entries */
-	rsdt->header.length = sizeof(acpi_header_t) + (sizeof(u32) * (i + 1));
+	rsdt->header.length = sizeof(struct acpi_table_header) +
+				(sizeof(u32) * (i + 1));
 
 	/* Re-calculate checksum */
 	rsdt->header.checksum = 0;
 	rsdt->header.checksum = table_compute_checksum((u8 *)rsdt,
-						       rsdt->header.length);
+			rsdt->header.length);
 
 	/*
 	 * And now the same thing for the XSDT. We use the same index as for
@@ -74,8 +143,8 @@
 		xsdt->entry[i] = (u64)(u32)table;
 
 		/* Fix XSDT length */
-		xsdt->header.length = sizeof(acpi_header_t) +
-			 (sizeof(u64) * (i + 1));
+		xsdt->header.length = sizeof(struct acpi_table_header) +
+			(sizeof(u64) * (i + 1));
 
 		/* Re-calculate checksum */
 		xsdt->header.checksum = 0;
@@ -84,149 +153,6 @@
 	}
 }
 
-static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
-			 u8 cpu, u8 apic)
-{
-	lapic->type = LOCALAPIC; /* Local APIC structure */
-	lapic->length = sizeof(struct acpi_madt_lapic);
-	lapic->flags = LOCAL_APIC_FLAG_ENABLED; /* Processor/LAPIC enabled */
-	lapic->processor_id = cpu;
-	lapic->apic_id = apic;
-
-	return lapic->length;
-}
-
-unsigned long acpi_create_madt_lapics(unsigned long current)
-{
-	struct udevice *dev;
-
-	for (uclass_find_first_device(UCLASS_CPU, &dev);
-	     dev;
-	     uclass_find_next_device(&dev)) {
-		struct cpu_platdata *plat = dev_get_parent_platdata(dev);
-
-		current += acpi_create_madt_lapic(
-			(struct acpi_madt_lapic *)current,
-			plat->cpu_id, plat->cpu_id);
-		}
-		return current;
-}
-
-int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
-			 u32 gsi_base)
-{
-	ioapic->type = IOAPIC;
-	ioapic->length = sizeof(struct acpi_madt_ioapic);
-	ioapic->reserved = 0x00;
-	ioapic->gsi_base = gsi_base;
-	ioapic->ioapic_id = id;
-	ioapic->ioapic_addr = addr;
-
-	return ioapic->length;
-}
-
-int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
-			 u8 bus, u8 source, u32 gsirq, u16 flags)
-{
-	irqoverride->type = IRQSOURCEOVERRIDE;
-	irqoverride->length = sizeof(struct acpi_madt_irqoverride);
-	irqoverride->bus = bus;
-	irqoverride->source = source;
-	irqoverride->gsirq = gsirq;
-	irqoverride->flags = flags;
-
-	return irqoverride->length;
-}
-
-int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
-			 u8 cpu, u16 flags, u8 lint)
-{
-	lapic_nmi->type = LOCALNMITYPE;
-	lapic_nmi->length = sizeof(struct acpi_madt_lapic_nmi);
-	lapic_nmi->flags = flags;
-	lapic_nmi->processor_id = cpu;
-	lapic_nmi->lint = lint;
-
-	return lapic_nmi->length;
-}
-
-static void fill_header(acpi_header_t *header, char *signature, int length)
-{
-	memcpy(header->signature, signature, length);
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-}
-
-static void acpi_create_madt(struct acpi_madt *madt)
-{
-	acpi_header_t *header = &(madt->header);
-	unsigned long current = (unsigned long)madt + sizeof(struct acpi_madt);
-
-	memset((void *)madt, 0, sizeof(struct acpi_madt));
-
-	/* Fill out header fields */
-	fill_header(header, "APIC", 4);
-	header->length = sizeof(struct acpi_madt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
-
-	madt->lapic_addr = LAPIC_DEFAULT_BASE;
-	madt->flags = PCAT_COMPAT;
-
-	current = acpi_fill_madt(current);
-
-	/* (Re)calculate length and checksum */
-	header->length = current - (unsigned long)madt;
-
-	header->checksum = table_compute_checksum((void *)madt, header->length);
-}
-
-static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig,
-			 u32 base, u16 seg_nr, u8 start, u8 end)
-{
-	memset(mmconfig, 0, sizeof(*mmconfig));
-	mmconfig->base_address = base;
-	mmconfig->base_reserved = 0;
-	mmconfig->pci_segment_group_number = seg_nr;
-	mmconfig->start_bus_number = start;
-	mmconfig->end_bus_number = end;
-
-	return sizeof(struct acpi_mcfg_mmconfig);
-}
-
-static unsigned long acpi_fill_mcfg(unsigned long current)
-{
-	current += acpi_create_mcfg_mmconfig
-		((struct acpi_mcfg_mmconfig *)current,
-		 CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
-
-	return current;
-}
-
-/* MCFG is defined in the PCI Firmware Specification 3.0 */
-static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
-{
-	acpi_header_t *header = &(mcfg->header);
-	unsigned long current = (unsigned long)mcfg + sizeof(struct acpi_mcfg);
-
-	memset((void *)mcfg, 0, sizeof(struct acpi_mcfg));
-
-	/* Fill out header fields */
-	fill_header(header, "MCFG", 4);
-	header->length = sizeof(struct acpi_mcfg);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
-
-	current = acpi_fill_mcfg(current);
-
-	/* (Re)calculate length and checksum */
-	header->length = current - (unsigned long)mcfg;
-	header->checksum = table_compute_checksum((void *)mcfg, header->length);
-}
-
 static void acpi_create_facs(struct acpi_facs *facs)
 {
 	memset((void *)facs, 0, sizeof(struct acpi_facs));
@@ -239,101 +165,165 @@
 	facs->flags = 0;
 	facs->x_firmware_waking_vector_l = 0;
 	facs->x_firmware_waking_vector_h = 0;
-	facs->version = 1; /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */
+	facs->version = 1;
 }
 
-static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
+static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
+				  u8 cpu, u8 apic)
 {
-	acpi_header_t *header = &(rsdt->header);
+	lapic->type = ACPI_APIC_LAPIC;
+	lapic->length = sizeof(struct acpi_madt_lapic);
+	lapic->flags = LOCAL_APIC_FLAG_ENABLED;
+	lapic->processor_id = cpu;
+	lapic->apic_id = apic;
 
-	/* Fill out header fields */
-	fill_header(header, "RSDT", 4);
-	header->length = sizeof(struct acpi_rsdt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
-
-	/* Entries are filled in later, we come with an empty set */
-
-	/* Fix checksum */
-	header->checksum = table_compute_checksum((void *)rsdt,
-			sizeof(struct acpi_rsdt));
+	return lapic->length;
 }
 
-static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
+int acpi_create_madt_lapics(u32 current)
 {
-	acpi_header_t *header = &(xsdt->header);
+	struct udevice *dev;
+	int length = 0;
 
-	/* Fill out header fields */
-	fill_header(header, "XSDT", 4);
-	header->length = sizeof(struct acpi_xsdt);
+	for (uclass_find_first_device(UCLASS_CPU, &dev);
+	     dev;
+	     uclass_find_next_device(&dev)) {
+		struct cpu_platdata *plat = dev_get_parent_platdata(dev);
 
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
-
-	/* Entries are filled in later, we come with an empty set */
-
-	/* Fix checksum */
-	header->checksum = table_compute_checksum((void *)xsdt,
-			sizeof(struct acpi_xsdt));
-}
-
-static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
-			 struct acpi_xsdt *xsdt)
-{
-	memset(rsdp, 0, sizeof(struct acpi_rsdp));
-
-	memcpy(rsdp->signature, RSDP_SIG, 8);
-	memcpy(rsdp->oem_id, OEM_ID, 6);
-
-	rsdp->length = sizeof(struct acpi_rsdp);
-	rsdp->rsdt_address = (u32)rsdt;
-
-	/*
-	* Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2
-	*
-	* Some OSes expect an XSDT to be present for RSD PTR revisions >= 2.
-	* If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR
-	* revision 0)
-	*/
-	if (xsdt == NULL) {
-		rsdp->revision = ACPI_RSDP_REV_ACPI_1_0;
-	} else {
-		rsdp->xsdt_address = (u64)(u32)xsdt;
-		rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
+		length += acpi_create_madt_lapic(
+			(struct acpi_madt_lapic *)current,
+			plat->cpu_id, plat->cpu_id);
+		current += length;
 	}
 
-	/* Calculate checksums */
-	rsdp->checksum = table_compute_checksum((void *)rsdp, 20);
-	rsdp->ext_checksum = table_compute_checksum((void *)rsdp,
-			sizeof(struct acpi_rsdp));
+	return length;
 }
 
-static void acpi_create_ssdt_generator(acpi_header_t *ssdt,
-			 const char *oem_table_id)
+int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
+			    u32 addr, u32 gsi_base)
 {
-	unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
+	ioapic->type = ACPI_APIC_IOAPIC;
+	ioapic->length = sizeof(struct acpi_madt_ioapic);
+	ioapic->reserved = 0x00;
+	ioapic->gsi_base = gsi_base;
+	ioapic->ioapic_id = id;
+	ioapic->ioapic_addr = addr;
 
-	memset((void *)ssdt, 0, sizeof(acpi_header_t));
+	return ioapic->length;
+}
 
-	memcpy(&ssdt->signature, "SSDT", 4);
-	/* Access size in ACPI 2.0c/3.0/4.0/5.0 */
-	ssdt->revision = ACPI_REV_ACPI_3_0;
-	memcpy(&ssdt->oem_id, OEM_ID, 6);
-	memcpy(&ssdt->oem_table_id, oem_table_id, 8);
-	ssdt->oem_revision = OEM_REVISION;
-	memcpy(&ssdt->asl_compiler_id, ASLC, 4);
-	ssdt->asl_compiler_revision = ASL_COMPILER_REVISION;
-	ssdt->length = sizeof(acpi_header_t);
+int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
+				 u8 bus, u8 source, u32 gsirq, u16 flags)
+{
+	irqoverride->type = ACPI_APIC_IRQ_SRC_OVERRIDE;
+	irqoverride->length = sizeof(struct acpi_madt_irqoverride);
+	irqoverride->bus = bus;
+	irqoverride->source = source;
+	irqoverride->gsirq = gsirq;
+	irqoverride->flags = flags;
+
+	return irqoverride->length;
+}
+
+int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
+			       u8 cpu, u16 flags, u8 lint)
+{
+	lapic_nmi->type = ACPI_APIC_LAPIC_NMI;
+	lapic_nmi->length = sizeof(struct acpi_madt_lapic_nmi);
+	lapic_nmi->flags = flags;
+	lapic_nmi->processor_id = cpu;
+	lapic_nmi->lint = lint;
+
+	return lapic_nmi->length;
+}
+
+static void acpi_create_madt(struct acpi_madt *madt)
+{
+	struct acpi_table_header *header = &(madt->header);
+	u32 current = (u32)madt + sizeof(struct acpi_madt);
+
+	memset((void *)madt, 0, sizeof(struct acpi_madt));
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "APIC");
+	header->length = sizeof(struct acpi_madt);
+	header->revision = 4;
+
+	madt->lapic_addr = LAPIC_DEFAULT_BASE;
+	madt->flags = ACPI_MADT_PCAT_COMPAT;
+
+	current = acpi_fill_madt(current);
 
 	/* (Re)calculate length and checksum */
-	ssdt->length = current - (unsigned long)ssdt;
-	ssdt->checksum = table_compute_checksum((void *)ssdt, ssdt->length);
+	header->length = current - (u32)madt;
+
+	header->checksum = table_compute_checksum((void *)madt, header->length);
+}
+
+static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig,
+				     u32 base, u16 seg_nr, u8 start, u8 end)
+{
+	memset(mmconfig, 0, sizeof(*mmconfig));
+	mmconfig->base_address_l = base;
+	mmconfig->base_address_h = 0;
+	mmconfig->pci_segment_group_number = seg_nr;
+	mmconfig->start_bus_number = start;
+	mmconfig->end_bus_number = end;
+
+	return sizeof(struct acpi_mcfg_mmconfig);
+}
+
+static u32 acpi_fill_mcfg(u32 current)
+{
+	current += acpi_create_mcfg_mmconfig
+		((struct acpi_mcfg_mmconfig *)current,
+		CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
+
+	return current;
+}
+
+/* MCFG is defined in the PCI Firmware Specification 3.0 */
+static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
+{
+	struct acpi_table_header *header = &(mcfg->header);
+	u32 current = (u32)mcfg + sizeof(struct acpi_mcfg);
+
+	memset((void *)mcfg, 0, sizeof(struct acpi_mcfg));
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "MCFG");
+	header->length = sizeof(struct acpi_mcfg);
+	header->revision = 1;
+
+	current = acpi_fill_mcfg(current);
+
+	/* (Re)calculate length and checksum */
+	header->length = current - (u32)mcfg;
+	header->checksum = table_compute_checksum((void *)mcfg, header->length);
+}
+
+static void enter_acpi_mode(int pm1_cnt)
+{
+	/*
+	 * PM1_CNT register bit0 selects the power management event to be
+	 * either an SCI or SMI interrupt. When this bit is set, then power
+	 * management events will generate an SCI interrupt. When this bit
+	 * is reset power management events will generate an SMI interrupt.
+	 *
+	 * Per ACPI spec, it is the responsibility of the hardware to set
+	 * or reset this bit. OSPM always preserves this bit position.
+	 *
+	 * U-Boot does not support SMI. And we don't have plan to support
+	 * anything running in SMM within U-Boot. To create a legacy-free
+	 * system, and expose ourselves to OSPM as working under ACPI mode
+	 * already, turn this bit on.
+	 */
+	outw(PM1_CNT_SCI_EN, pm1_cnt);
 }
 
 /*
  * QEMU's version of write_acpi_tables is defined in
- * arch/x86/cpu/qemu/fw_cfg.c
+ * arch/x86/cpu/qemu/acpi_table.c
  */
 u32 write_acpi_tables(u32 start)
 {
@@ -342,18 +332,17 @@
 	struct acpi_rsdt *rsdt;
 	struct acpi_xsdt *xsdt;
 	struct acpi_facs *facs;
-	acpi_header_t *dsdt;
+	struct acpi_table_header *dsdt;
 	struct acpi_fadt *fadt;
 	struct acpi_mcfg *mcfg;
 	struct acpi_madt *madt;
-	acpi_header_t *ssdt;
 
 	current = start;
 
-	/* Align ACPI tables to 16byte */
+	/* Align ACPI tables to 16 byte */
 	current = ALIGN(current, 16);
 
-	debug("ACPI: Writing ACPI tables at %lx.\n", start);
+	debug("ACPI: Writing ACPI tables at %x\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (struct acpi_rsdp *)current;
@@ -364,7 +353,11 @@
 	current = ALIGN(current, 16);
 	xsdt = (struct acpi_xsdt *)current;
 	current += sizeof(struct acpi_xsdt);
-	current = ALIGN(current, 16);
+	/*
+	 * Per ACPI spec, the FACS table address must be aligned to a 64 byte
+	 * boundary (Windows checks this, but Linux does not).
+	 */
+	current = ALIGN(current, 64);
 
 	/* clear all table memory */
 	memset((void *)start, 0, current - start);
@@ -381,21 +374,13 @@
 	acpi_create_facs(facs);
 
 	debug("ACPI:    * DSDT\n");
-	dsdt = (acpi_header_t *)current;
-	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-	if (dsdt->length >= sizeof(acpi_header_t)) {
-		current += sizeof(acpi_header_t);
-		memcpy((char *)current,
-				(char *)&AmlCode + sizeof(acpi_header_t),
-				dsdt->length - sizeof(acpi_header_t));
-		current += dsdt->length - sizeof(acpi_header_t);
-
-		/* (Re)calculate length and checksum */
-		dsdt->length = current - (unsigned long)dsdt;
-		dsdt->checksum = 0;
-		dsdt->checksum = table_compute_checksum((void *)dsdt,
-				dsdt->length);
-	}
+	dsdt = (struct acpi_table_header *)current;
+	memcpy(dsdt, &AmlCode, sizeof(struct acpi_table_header));
+	current += sizeof(struct acpi_table_header);
+	memcpy((char *)current,
+	       (char *)&AmlCode + sizeof(struct acpi_table_header),
+	       dsdt->length - sizeof(struct acpi_table_header));
+	current += dsdt->length - sizeof(struct acpi_table_header);
 	current = ALIGN(current, 16);
 
 	debug("ACPI:    * FADT\n");
@@ -405,36 +390,29 @@
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdp, fadt);
 
-	debug("ACPI:    * MCFG\n");
-	mcfg = (struct acpi_mcfg *)current;
-	acpi_create_mcfg(mcfg);
-	if (mcfg->header.length > sizeof(struct acpi_mcfg)) {
-		current += mcfg->header.length;
-		current = ALIGN(current, 16);
-		acpi_add_table(rsdp, mcfg);
-	}
-
 	debug("ACPI:    * MADT\n");
 	madt = (struct acpi_madt *)current;
 	acpi_create_madt(madt);
-	if (madt->header.length > sizeof(struct acpi_madt)) {
-		current += madt->header.length;
-		acpi_add_table(rsdp, madt);
-	}
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
 	current = ALIGN(current, 16);
 
-	debug("ACPI:    * SSDT\n");
-	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
-	if (ssdt->length > sizeof(acpi_header_t)) {
-		current += ssdt->length;
-		acpi_add_table(rsdp, ssdt);
-		current = ALIGN(current, 16);
-	}
+	debug("ACPI:    * MCFG\n");
+	mcfg = (struct acpi_mcfg *)current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	acpi_add_table(rsdp, mcfg);
+	current = ALIGN(current, 16);
 
-	debug("current = %lx\n", current);
+	debug("current = %x\n", current);
 
-	debug("ACPI: done.\n");
+	debug("ACPI: done\n");
+
+	/*
+	 * Other than waiting for OSPM to request us to switch to ACPI mode,
+	 * do it by ourselves, since SMI will not be triggered.
+	 */
+	enter_acpi_mode(fadt->pm1a_cnt_blk);
 
 	return current;
 }
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 783be69..7cf9de4 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -26,14 +26,6 @@
 
 #define COMMAND_LINE_OFFSET 0x9000
 
-/*
- * Implement a weak default function for boards that optionally
- * need to clean up the system before jumping to the kernel.
- */
-__weak void board_final_cleanup(void)
-{
-}
-
 void bootm_announce_and_cleanup(void)
 {
 	printf("\nStarting kernel ...\n\n");
@@ -45,7 +37,6 @@
 #ifdef CONFIG_BOOTSTAGE_REPORT
 	bootstage_report();
 #endif
-	board_final_cleanup();
 }
 
 #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)
diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c
index cb45a79..ceab3cf 100644
--- a/arch/x86/lib/coreboot_table.c
+++ b/arch/x86/lib/coreboot_table.c
@@ -9,6 +9,37 @@
 #include <asm/coreboot_tables.h>
 #include <asm/e820.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+int high_table_reserve(void)
+{
+	/* adjust stack pointer to reserve space for configuration tables */
+	gd->arch.high_table_limit = gd->start_addr_sp;
+	gd->start_addr_sp -= CONFIG_HIGH_TABLE_SIZE;
+	gd->arch.high_table_ptr = gd->start_addr_sp;
+
+	/* clear the memory */
+	memset((void *)gd->arch.high_table_ptr, 0, CONFIG_HIGH_TABLE_SIZE);
+
+	gd->start_addr_sp &= ~0xf;
+
+	return 0;
+}
+
+void *high_table_malloc(size_t bytes)
+{
+	u32 new_ptr;
+	void *ptr;
+
+	new_ptr = gd->arch.high_table_ptr + bytes;
+	if (new_ptr >= gd->arch.high_table_limit)
+		return NULL;
+	ptr = (void *)gd->arch.high_table_ptr;
+	gd->arch.high_table_ptr = new_ptr;
+
+	return ptr;
+}
+
 /**
  * cb_table_init() - initialize a coreboot table header
  *
diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c
index 3cc6adb..a93d355 100644
--- a/arch/x86/lib/pirq_routing.c
+++ b/arch/x86/lib/pirq_routing.c
@@ -10,7 +10,6 @@
 #include <pci.h>
 #include <asm/pci.h>
 #include <asm/pirq_routing.h>
-#include <asm/tables.h>
 
 static bool irq_already_routed[16];
 
@@ -111,9 +110,6 @@
 {
 	struct irq_routing_table *rom_rt;
 
-	/* Fix up the table checksum */
-	rt->checksum = table_compute_checksum(rt, rt->size);
-
 	/* Align the table to be 16 byte aligned */
 	addr = ALIGN(addr, 16);
 
diff --git a/arch/x86/lib/smbios.c b/arch/x86/lib/smbios.c
index 441fca9..9f30550 100644
--- a/arch/x86/lib/smbios.c
+++ b/arch/x86/lib/smbios.c
@@ -105,8 +105,8 @@
 
 	memset(t, 0, sizeof(struct smbios_type1));
 	fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle);
-	t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
-	t->product_name = smbios_add_string(t->eos, CONFIG_SYS_BOARD);
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
+	t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
 
 	len = t->length + smbios_string_table_len(t->eos);
 	*current += len;
@@ -121,8 +121,8 @@
 
 	memset(t, 0, sizeof(struct smbios_type2));
 	fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle);
-	t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
-	t->product_name = smbios_add_string(t->eos, CONFIG_SYS_BOARD);
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
+	t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
 	t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING;
 	t->board_type = SMBIOS_BOARD_MOTHERBOARD;
 
@@ -139,7 +139,7 @@
 
 	memset(t, 0, sizeof(struct smbios_type3));
 	fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle);
-	t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
 	t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP;
 	t->bootup_state = SMBIOS_STATE_SAFE;
 	t->power_supply_state = SMBIOS_STATE_SAFE;
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index a156f2c..f92111e 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -80,9 +80,8 @@
 
 #ifdef CONFIG_SEABIOS
 		table_size = rom_table_end - rom_table_start;
-		high_table = (u32)memalign(ROM_TABLE_ALIGN, table_size);
+		high_table = (u32)high_table_malloc(table_size);
 		if (high_table) {
-			memset((void *)high_table, 0, table_size);
 			table_write_funcs[i](high_table);
 
 			cfg_tables[i].start = high_table;
diff --git a/board/atmel/sama5d2_ptc/Kconfig b/board/atmel/sama5d2_ptc/Kconfig
new file mode 100644
index 0000000..d2661c6
--- /dev/null
+++ b/board/atmel/sama5d2_ptc/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D2_PTC
+
+config SYS_BOARD
+	default "sama5d2_ptc"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at91"
+
+config SYS_CONFIG_NAME
+	default "sama5d2_ptc"
+
+endif
diff --git a/board/atmel/sama5d2_ptc/MAINTAINERS b/board/atmel/sama5d2_ptc/MAINTAINERS
new file mode 100644
index 0000000..7ab03d6
--- /dev/null
+++ b/board/atmel/sama5d2_ptc/MAINTAINERS
@@ -0,0 +1,7 @@
+SAMA5D2 PTC Engineering BOARD
+M:	Wenyou Yang <wenyou.yang@atmel.com>
+S:	Maintained
+F:	board/atmel/sama5d2_ptc/
+F:	include/configs/sama5d2_ptc.h
+F:	configs/sama5d2_ptc_spiflash_defconfig
+F:	configs/sama5d2_ptc_nandflash_defconfig
diff --git a/board/atmel/sama5d2_ptc/Makefile b/board/atmel/sama5d2_ptc/Makefile
new file mode 100644
index 0000000..1fe0392
--- /dev/null
+++ b/board/atmel/sama5d2_ptc/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Atmel
+#		     Wenyou Yang <wenyou.yang@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += sama5d2_ptc.o
diff --git a/board/atmel/sama5d2_ptc/sama5d2_ptc.c b/board/atmel/sama5d2_ptc/sama5d2_ptc.c
new file mode 100644
index 0000000..9e6544b
--- /dev/null
+++ b/board/atmel/sama5d2_ptc/sama5d2_ptc.c
@@ -0,0 +1,285 @@
+/*
+ * Copyright (C) 2016 Atmel
+ *		      Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <atmel_hlcdc.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5_sfr.h>
+#include <asm/arch/sama5d2.h>
+#include <asm/arch/sama5d3_smc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+}
+
+static void board_spi0_hw_init(void)
+{
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
+
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+
+static void board_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+
+	at91_periph_clk_enable(ATMEL_ID_HSMC);
+
+	writel(AT91_SFR_EBICFG_DRIVE0_HIGH |
+	       AT91_SFR_EBICFG_PULL0_NONE |
+	       AT91_SFR_EBICFG_DRIVE1_HIGH |
+	       AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg);
+
+	/* Configure SMC CS3 for NAND */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+	       AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
+	       AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3) |
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0);	/* D0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0);	/* D1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0);	/* D2 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0);	/* D3 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0);	/* D4 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0);	/* D5 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0);	/* D6 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0);	/* D7 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0);	/* RE */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0);	/* WE */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1);	/* NCS */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1);	/* RDY */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1);	/* ALE */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1);	/* CLE */
+}
+
+static void board_usb_hw_init(void)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1);
+}
+
+static void board_gmac_hw_init(void)
+{
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0);	/* GTXCK */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0);	/* GTXEN */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0);	/* GRXDV */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0);	/* GRXER */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0);	/* GRX0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0);	/* GRX1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0);	/* GTX0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0);	/* GTX1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0);	/* GMDC */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0);	/* GMDIO */
+
+	at91_periph_clk_enable(ATMEL_ID_GMAC);
+}
+
+static void board_uart0_hw_init(void)
+{
+	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1);	/* URXD0 */
+	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0);	/* UTXD0 */
+
+	at91_periph_clk_enable(CONFIG_USART_ID);
+}
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+	board_uart0_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+	board_spi0_hw_init();
+#endif
+#ifdef CONFIG_NAND_ATMEL
+	board_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	board_gmac_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	board_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	at91_udp_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+	if (rc)
+		printf("GMAC register failed\n");
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+	usb_eth_initialize(bis);
+#endif
+#endif
+
+	return rc;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+	board_spi0_hw_init();
+#endif
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+	board_nand_hw_init();
+#endif
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
+
+	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
+		    ATMEL_MPDDRC_CR_DIC_DS |
+		    ATMEL_MPDDRC_CR_DIS_DLL |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddrc->rtr = 0x511;
+
+	ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+		      (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+	ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+		      (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+	ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+		      (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	struct atmel_mpddrc_config ddrc_config;
+	u32 reg;
+
+	ddrc_conf(&ddrc_config);
+
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	reg = readl(&mpddrc->io_calibr);
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
+	writel(reg, &mpddrc->io_calibr);
+
+	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
+	       &mpddrc->rd_data_path);
+
+	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+
+	writel(0x3, &mpddrc->cal_mr4);
+	writel(64, &mpddrc->tim_cal);
+}
+
+void at91_pmc_init(void)
+{
+	at91_plla_init(AT91_PMC_PLLAR_29 |
+		       AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+		       AT91_PMC_PLLXR_MUL(82) |
+		       AT91_PMC_PLLXR_DIV(1));
+
+	at91_pllicpr_init(0);
+
+	at91_mck_init(AT91_PMC_MCKR_H32MXDIV |
+		      AT91_PMC_MCKR_PLLADIV_2 |
+		      AT91_PMC_MCKR_MDIV_3 |
+		      AT91_PMC_MCKR_CSS_PLLA);
+}
+#endif
diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
index 10edf28..93df7ba 100644
--- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c
+++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
@@ -171,10 +171,11 @@
 	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0);	/* SDMMC0_DAT7 */
 	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* SDMMC0_RSTN */
 	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* SDMMC0_VDDSEL */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* SDMMC0_CD */
 
 	at91_periph_clk_enable(ATMEL_ID_SDMMC0);
 	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0,
-					 GCK_CSS_PLLA_CLK, 1);
+					 GCK_CSS_UPLL_CLK, 1);
 }
 
 static void board_sdhci1_hw_init(void)
@@ -190,7 +191,7 @@
 
 	at91_periph_clk_enable(ATMEL_ID_SDMMC1);
 	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1,
-					 GCK_CSS_PLLA_CLK, 1);
+					 GCK_CSS_UPLL_CLK, 1);
 }
 
 int board_mmc_init(bd_t *bis)
diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c
index 2ed90de..4740c83 100644
--- a/board/cm5200/fwupdate.c
+++ b/board/cm5200/fwupdate.c
@@ -105,7 +105,7 @@
 
 	/* Detect storage device */
 	for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) {
-		stor_dev = usb_stor_get_dev(devno);
+		stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, devno);
 		if (stor_dev->type != DEV_TYPE_UNKNOWN)
 			break;
 	}
diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c
index 6304468..b5f1aa6 100644
--- a/board/compulab/common/eeprom.c
+++ b/board/compulab/common/eeprom.c
@@ -9,6 +9,9 @@
 
 #include <common.h>
 #include <i2c.h>
+#include <eeprom_layout.h>
+#include <eeprom_field.h>
+#include <linux/kernel.h>
 #include "eeprom.h"
 
 #ifndef CONFIG_SYS_I2C_EEPROM_ADDR
@@ -181,3 +184,344 @@
 
 	return err;
 }
+
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+/**
+ * eeprom_field_print_bin_ver() - print a "version field" which contains binary
+ *				  data
+ *
+ * Treat the field data as simple binary data, and print it formatted as a
+ * version number (2 digits after decimal point).
+ * The field size must be exactly 2 bytes.
+ *
+ * Sample output:
+ *      Field Name      123.45
+ *
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_bin_ver(const struct eeprom_field *field)
+{
+	if ((field->buf[0] == 0xff) && (field->buf[1] == 0xff)) {
+		field->buf[0] = 0;
+		field->buf[1] = 0;
+	}
+
+	printf(PRINT_FIELD_SEGMENT, field->name);
+	int major = (field->buf[1] << 8 | field->buf[0]) / 100;
+	int minor = (field->buf[1] << 8 | field->buf[0]) - major * 100;
+	printf("%d.%02d\n", major, minor);
+}
+
+/**
+ * eeprom_field_update_bin_ver() - update a "version field" which contains
+ *				   binary data
+ *
+ * This function takes a version string in the form of x.y (x and y are both
+ * decimal values, y is limited to two digits), translates it to the binary
+ * form, then writes it to the field. The field size must be exactly 2 bytes.
+ *
+ * This function strictly enforces the data syntax, and will not update the
+ * field if there's any deviation from it. It also protects from overflow.
+ *
+ * @field:	an initialized field
+ * @value:	a version string
+ *
+ * Returns 0 on success, -1 on failure.
+ */
+int eeprom_field_update_bin_ver(struct eeprom_field *field, char *value)
+{
+	char *endptr;
+	char *tok = strtok(value, ".");
+	if (tok == NULL)
+		return -1;
+
+	int num = simple_strtol(tok, &endptr, 0);
+	if (*endptr != '\0')
+		return -1;
+
+	tok = strtok(NULL, "");
+	if (tok == NULL)
+		return -1;
+
+	int remainder = simple_strtol(tok, &endptr, 0);
+	if (*endptr != '\0')
+		return -1;
+
+	num = num * 100 + remainder;
+	if (num >> 16)
+		return -1;
+
+	field->buf[0] = (unsigned char)num;
+	field->buf[1] = num >> 8;
+
+	return 0;
+}
+
+char *months[12] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun",
+		    "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"};
+
+/**
+ * eeprom_field_print_date() - print a field which contains date data
+ *
+ * Treat the field data as simple binary data, and print it formatted as a date.
+ * Sample output:
+ *      Field Name      07/Feb/2014
+ *      Field Name      56/BAD/9999
+ *
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_date(const struct eeprom_field *field)
+{
+	printf(PRINT_FIELD_SEGMENT, field->name);
+	printf("%02d/", field->buf[0]);
+	if (field->buf[1] >= 1 && field->buf[1] <= 12)
+		printf("%s", months[field->buf[1] - 1]);
+	else
+		printf("BAD");
+
+	printf("/%d\n", field->buf[3] << 8 | field->buf[2]);
+}
+
+static int validate_date(unsigned char day, unsigned char month,
+			unsigned int year)
+{
+	int days_in_february;
+
+	switch (month) {
+	case 0:
+	case 2:
+	case 4:
+	case 6:
+	case 7:
+	case 9:
+	case 11:
+		if (day > 31)
+			return -1;
+		break;
+	case 3:
+	case 5:
+	case 8:
+	case 10:
+		if (day > 30)
+			return -1;
+		break;
+	case 1:
+		days_in_february = 28;
+		if (year % 4 == 0) {
+			if (year % 100 != 0)
+				days_in_february = 29;
+			else if (year % 400 == 0)
+				days_in_february = 29;
+		}
+
+		if (day > days_in_february)
+			return -1;
+
+		break;
+	default:
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * eeprom_field_update_date() - update a date field which contains binary data
+ *
+ * This function takes a date string in the form of x/Mon/y (x and y are both
+ * decimal values), translates it to the binary representation, then writes it
+ * to the field.
+ *
+ * This function strictly enforces the data syntax, and will not update the
+ * field if there's any deviation from it. It also protects from overflow in the
+ * year value, and checks the validity of the date.
+ *
+ * @field:	an initialized field
+ * @value:	a date string
+ *
+ * Returns 0 on success, -1 on failure.
+ */
+int eeprom_field_update_date(struct eeprom_field *field, char *value)
+{
+	char *endptr;
+	char *tok1 = strtok(value, "/");
+	char *tok2 = strtok(NULL, "/");
+	char *tok3 = strtok(NULL, "/");
+
+	if (tok1 == NULL || tok2 == NULL || tok3 == NULL) {
+		printf("%s: syntax error\n", field->name);
+		return -1;
+	}
+
+	unsigned char day = (unsigned char)simple_strtol(tok1, &endptr, 0);
+	if (*endptr != '\0' || day == 0) {
+		printf("%s: invalid day\n", field->name);
+		return -1;
+	}
+
+	unsigned char month;
+	for (month = 1; month <= 12; month++)
+		if (!strcmp(tok2, months[month - 1]))
+			break;
+
+	unsigned int year = simple_strtol(tok3, &endptr, 0);
+	if (*endptr != '\0') {
+		printf("%s: invalid year\n", field->name);
+		return -1;
+	}
+
+	if (validate_date(day, month - 1, year)) {
+		printf("%s: invalid date\n", field->name);
+		return -1;
+	}
+
+	if (year >> 16) {
+		printf("%s: year overflow\n", field->name);
+		return -1;
+	}
+
+	field->buf[0] = day;
+	field->buf[1] = month;
+	field->buf[2] = (unsigned char)year;
+	field->buf[3] = (unsigned char)(year >> 8);
+
+	return 0;
+}
+
+#define	LAYOUT_VERSION_LEGACY 1
+#define	LAYOUT_VERSION_VER1 2
+#define	LAYOUT_VERSION_VER2 3
+#define	LAYOUT_VERSION_VER3 4
+
+extern struct eeprom_field layout_unknown[1];
+
+#define DEFINE_PRINT_UPDATE(x) eeprom_field_print_##x, eeprom_field_update_##x
+
+#ifdef CONFIG_CM_T3X
+struct eeprom_field layout_legacy[5] = {
+	{ "MAC address",          6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Board Revision",       2, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ "Serial Number",        8, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ "Board Configuration", 64, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ RESERVED_FIELDS,      176, NULL, eeprom_field_print_reserved,
+					   eeprom_field_update_ascii },
+};
+#else
+#define layout_legacy layout_unknown
+#endif
+
+#if defined(CONFIG_CM_T3X) || defined(CONFIG_CM_T3517)
+struct eeprom_field layout_v1[12] = {
+	{ "Major Revision",      2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "Minor Revision",      2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "1st MAC Address",     6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "2nd MAC Address",     6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Production Date",     4, NULL, DEFINE_PRINT_UPDATE(date) },
+	{ "Serial Number",      12, NULL, DEFINE_PRINT_UPDATE(bin_rev) },
+	{ RESERVED_FIELDS,      96, NULL, DEFINE_PRINT_UPDATE(reserved) },
+	{ "Product Name",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ RESERVED_FIELDS,      64, NULL, eeprom_field_print_reserved,
+					  eeprom_field_update_ascii },
+};
+#else
+#define layout_v1 layout_unknown
+#endif
+
+struct eeprom_field layout_v2[15] = {
+	{ "Major Revision",            2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "Minor Revision",            2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "1st MAC Address",           6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "2nd MAC Address",           6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Production Date",           4, NULL, DEFINE_PRINT_UPDATE(date) },
+	{ "Serial Number",            12, NULL, DEFINE_PRINT_UPDATE(bin_rev) },
+	{ "3rd MAC Address (WIFI)",    6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "4th MAC Address (Bluetooth)", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Layout Version",            1, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ RESERVED_FIELDS,            83, NULL, DEFINE_PRINT_UPDATE(reserved) },
+	{ "Product Name",             16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #1",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #2",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #3",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ RESERVED_FIELDS,            64, NULL, eeprom_field_print_reserved,
+						eeprom_field_update_ascii },
+};
+
+struct eeprom_field layout_v3[16] = {
+	{ "Major Revision",            2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "Minor Revision",            2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "1st MAC Address",           6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "2nd MAC Address",           6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Production Date",           4, NULL, DEFINE_PRINT_UPDATE(date) },
+	{ "Serial Number",            12, NULL, DEFINE_PRINT_UPDATE(bin_rev) },
+	{ "3rd MAC Address (WIFI)",    6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "4th MAC Address (Bluetooth)", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Layout Version",            1, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ "CompuLab EEPROM ID",        3, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ RESERVED_FIELDS,            80, NULL, DEFINE_PRINT_UPDATE(reserved) },
+	{ "Product Name",             16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #1",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #2",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #3",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ RESERVED_FIELDS,            64, NULL, eeprom_field_print_reserved,
+						eeprom_field_update_ascii },
+};
+
+void eeprom_layout_assign(struct eeprom_layout *layout, int layout_version)
+{
+	switch (layout->layout_version) {
+	case LAYOUT_VERSION_LEGACY:
+		layout->fields = layout_legacy;
+		layout->num_of_fields = ARRAY_SIZE(layout_legacy);
+		break;
+	case LAYOUT_VERSION_VER1:
+		layout->fields = layout_v1;
+		layout->num_of_fields = ARRAY_SIZE(layout_v1);
+		break;
+	case LAYOUT_VERSION_VER2:
+		layout->fields = layout_v2;
+		layout->num_of_fields = ARRAY_SIZE(layout_v2);
+		break;
+	case LAYOUT_VERSION_VER3:
+		layout->fields = layout_v3;
+		layout->num_of_fields = ARRAY_SIZE(layout_v3);
+		break;
+	default:
+		__eeprom_layout_assign(layout, layout_version);
+	}
+}
+
+int eeprom_parse_layout_version(char *str)
+{
+	if (!strcmp(str, "legacy"))
+		return LAYOUT_VERSION_LEGACY;
+	else if (!strcmp(str, "v1"))
+		return LAYOUT_VERSION_VER1;
+	else if (!strcmp(str, "v2"))
+		return LAYOUT_VERSION_VER2;
+	else if (!strcmp(str, "v3"))
+		return LAYOUT_VERSION_VER3;
+	else
+		return LAYOUT_VERSION_UNRECOGNIZED;
+}
+
+int eeprom_layout_detect(unsigned char *data)
+{
+	switch (data[EEPROM_LAYOUT_VER_OFFSET]) {
+	case 0xff:
+	case 0:
+		return LAYOUT_VERSION_VER1;
+	case 2:
+		return LAYOUT_VERSION_VER2;
+	case 3:
+		return LAYOUT_VERSION_VER3;
+	}
+
+	if (data[EEPROM_LAYOUT_VER_OFFSET] >= 0x20)
+		return LAYOUT_VERSION_LEGACY;
+
+	return LAYOUT_VERSION_UNRECOGNIZED;
+}
+#endif
diff --git a/board/congatec/conga-qeval20-qa3-e3845/.gitignore b/board/congatec/conga-qeval20-qa3-e3845/.gitignore
new file mode 100644
index 0000000..6eb8a54
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/congatec/conga-qeval20-qa3-e3845/Makefile b/board/congatec/conga-qeval20-qa3-e3845/Makefile
index 23b8748..b784510 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/Makefile
+++ b/board/congatec/conga-qeval20-qa3-e3845/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= conga-qeval20-qa3.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl b/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl
new file mode 100644
index 0000000..eace459
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
+
+/* TODO: Need add Winbond SuperIO chipset W83627 ASL codes */
diff --git a/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl b/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl
new file mode 100644
index 0000000..6042011
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index ae09c27..534db1d 100644
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -24,7 +24,6 @@
 
 	.text
 	.set noreorder
-	.set mips32
 
 	.globl	lowlevel_init
 lowlevel_init:
diff --git a/board/intel/bayleybay/.gitignore b/board/intel/bayleybay/.gitignore
new file mode 100644
index 0000000..6eb8a54
--- /dev/null
+++ b/board/intel/bayleybay/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/intel/bayleybay/Makefile b/board/intel/bayleybay/Makefile
index 88b5aad..52dda7d 100644
--- a/board/intel/bayleybay/Makefile
+++ b/board/intel/bayleybay/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= bayleybay.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/intel/bayleybay/acpi/mainboard.asl b/board/intel/bayleybay/acpi/mainboard.asl
new file mode 100644
index 0000000..21785ea
--- /dev/null
+++ b/board/intel/bayleybay/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/intel/bayleybay/dsdt.asl b/board/intel/bayleybay/dsdt.asl
new file mode 100644
index 0000000..6042011
--- /dev/null
+++ b/board/intel/bayleybay/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig
index 6515bac..87a0ec4 100644
--- a/board/intel/galileo/Kconfig
+++ b/board/intel/galileo/Kconfig
@@ -21,4 +21,15 @@
 	select INTEL_QUARK
 	select BOARD_ROMSIZE_KB_1024
 
+config SMBIOS_PRODUCT_NAME
+	default "GalileoGen2"
+	help
+	  Override the default product name U-Boot reports in the SMBIOS
+	  table, to be compatible with the Intel provided UEFI BIOS, as
+	  Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and
+	  drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
+	  it to do different board level configuration.
+
+	  This can be "Galileo" for GEN1 Galileo board.
+
 endif
diff --git a/board/intel/minnowmax/.gitignore b/board/intel/minnowmax/.gitignore
new file mode 100644
index 0000000..6eb8a54
--- /dev/null
+++ b/board/intel/minnowmax/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile
index 1a61432..73e5a8f 100644
--- a/board/intel/minnowmax/Makefile
+++ b/board/intel/minnowmax/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= minnowmax.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/intel/minnowmax/acpi/mainboard.asl b/board/intel/minnowmax/acpi/mainboard.asl
new file mode 100644
index 0000000..21785ea
--- /dev/null
+++ b/board/intel/minnowmax/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/intel/minnowmax/dsdt.asl b/board/intel/minnowmax/dsdt.asl
new file mode 100644
index 0000000..6042011
--- /dev/null
+++ b/board/intel/minnowmax/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/board/keymile/km83xx/km83xx_i2c.c b/board/keymile/km83xx/km83xx_i2c.c
index c961937..f0b528d 100644
--- a/board/keymile/km83xx/km83xx_i2c.c
+++ b/board/keymile/km83xx/km83xx_i2c.c
@@ -13,31 +13,33 @@
 
 static void i2c_write_start_seq(void)
 {
-	struct fsl_i2c *dev;
-	dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+	struct fsl_i2c_base *base;
+	base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
+			CONFIG_SYS_I2C_OFFSET);
 	udelay(DELAY_ABORT_SEQ);
-	out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+	out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
 	udelay(DELAY_ABORT_SEQ);
-	out_8(&dev->cr, (I2C_CR_MEN));
+	out_8(&base->cr, (I2C_CR_MEN));
 }
 
 int i2c_make_abort(void)
 {
-	struct fsl_i2c *dev;
-	dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+	struct fsl_i2c_base *base;
+	base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
+			CONFIG_SYS_I2C_OFFSET);
 	uchar   last;
 	int     nbr_read = 0;
 	int     i = 0;
 	int	    ret = 0;
 
 	/* wait after each operation to finsh with a delay */
-	out_8(&dev->cr, (I2C_CR_MSTA));
+	out_8(&base->cr, (I2C_CR_MSTA));
 	udelay(DELAY_ABORT_SEQ);
-	out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+	out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
 	udelay(DELAY_ABORT_SEQ);
-	in_8(&dev->dr);
+	in_8(&base->dr);
 	udelay(DELAY_ABORT_SEQ);
-	last = in_8(&dev->dr);
+	last = in_8(&base->dr);
 	nbr_read++;
 
 	/*
@@ -47,7 +49,7 @@
 	while (((last & 0x01) != 0x01) &&
 		(nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) {
 		udelay(DELAY_ABORT_SEQ);
-		last = in_8(&dev->dr);
+		last = in_8(&base->dr);
 		nbr_read++;
 	}
 	if ((last & 0x01) != 0x01)
@@ -56,10 +58,10 @@
 		printf("[INFO] i2c abort after %d bytes (0x%02x)\n",
 			nbr_read, last);
 	udelay(DELAY_ABORT_SEQ);
-	out_8(&dev->cr, (I2C_CR_MEN));
+	out_8(&base->cr, (I2C_CR_MEN));
 	udelay(DELAY_ABORT_SEQ);
 	/* clear status reg */
-	out_8(&dev->sr, 0);
+	out_8(&base->sr, 0);
 
 	for (i = 0; i < 5; i++)
 		i2c_write_start_seq();
diff --git a/board/mpl/pip405/README b/board/mpl/pip405/README
index e900c56..f039817 100644
--- a/board/mpl/pip405/README
+++ b/board/mpl/pip405/README
@@ -32,8 +32,8 @@
 - include/cmd_bsp.h		added PIP405 commands definitions
 - include/cmd_condefs.h		added Floppy and SCSI support
 - include/cmd_disk.h		changed to work with block device description
-- include/config_LANTEC.h	excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI
-- include/config_hymod.h	excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI
+- include/config_LANTEC.h	excluded CONFIG_CMD_FDC and CONFIG_SCSI
+- include/config_hymod.h	excluded CONFIG_CMD_FDC and CONFIG_SCSI
 - include/flash.h		added INTEL_ID_28F320C3T  0x88C488C4
 - include/i2c.h			added "defined(CONFIG_PIP405)"
 - include/image.h		added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
@@ -86,7 +86,7 @@
 
 New Commands:
 -------------
-CONFIG_CMD_SCSI	SCSI Support
+CONFIG_SCSI	SCSI Support
 CONFIG_CMF_FDC	Floppy disk support
 
 IDE additions:
diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
new file mode 100644
index 0000000..f7e768a
--- /dev/null
+++ b/board/qca/ap121/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AP121
+
+config SYS_VENDOR
+	default "qca"
+
+config SYS_BOARD
+	default "ap121"
+
+config SYS_CONFIG_NAME
+	default "ap121"
+
+endif
diff --git a/board/qca/ap121/MAINTAINERS b/board/qca/ap121/MAINTAINERS
new file mode 100644
index 0000000..8b02988
--- /dev/null
+++ b/board/qca/ap121/MAINTAINERS
@@ -0,0 +1,6 @@
+AP121 BOARD
+M:	Wills Wang <wills.wang@live.com>
+S:	Maintained
+F:	board/qca/ap121/
+F:	include/configs/ap121.h
+F:	configs/ap121_defconfig
diff --git a/board/qca/ap121/Makefile b/board/qca/ap121/Makefile
new file mode 100644
index 0000000..ced5432
--- /dev/null
+++ b/board/qca/ap121/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= ap121.o
diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c
new file mode 100644
index 0000000..d6c60fe
--- /dev/null
+++ b/board/qca/ap121/ap121.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+			   MAP_NOCACHE);
+
+	/*
+	 * GPIO9 as input, GPIO10 as output
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_OE);
+	val &= ~AR933X_GPIO(9);
+	val |= AR933X_GPIO(10);
+	writel(val, regs + AR71XX_GPIO_REG_OE);
+
+	/*
+	 * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_FUNC);
+	val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE;
+	writel(val, regs + AR71XX_GPIO_REG_FUNC);
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	ddr_init();
+	return 0;
+}
diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
new file mode 100644
index 0000000..4cdac0d
--- /dev/null
+++ b/board/qca/ap143/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AP143
+
+config SYS_VENDOR
+	default "qca"
+
+config SYS_BOARD
+	default "ap143"
+
+config SYS_CONFIG_NAME
+	default "ap143"
+
+endif
diff --git a/board/qca/ap143/MAINTAINERS b/board/qca/ap143/MAINTAINERS
new file mode 100644
index 0000000..11cb14f
--- /dev/null
+++ b/board/qca/ap143/MAINTAINERS
@@ -0,0 +1,6 @@
+AP143 BOARD
+M:	Wills Wang <wills.wang@live.com>
+S:	Maintained
+F:	board/qca/ap143/
+F:	include/configs/ap143.h
+F:	configs/ap143_defconfig
diff --git a/board/qca/ap143/Makefile b/board/qca/ap143/Makefile
new file mode 100644
index 0000000..00f7837
--- /dev/null
+++ b/board/qca/ap143/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= ap143.o
diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c
new file mode 100644
index 0000000..1572472
--- /dev/null
+++ b/board/qca/ap143/ap143.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+			   MAP_NOCACHE);
+
+	/*
+	 * GPIO9 as input, GPIO10 as output
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_OE);
+	val |= QCA953X_GPIO(9);
+	val &= ~QCA953X_GPIO(10);
+	writel(val, regs + AR71XX_GPIO_REG_OE);
+
+	/*
+	 * Enable GPIO10 as UART0_SOUT
+	 */
+	val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2);
+	val &= ~QCA953X_GPIO_MUX_MASK(16);
+	val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16;
+	writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2);
+
+	/*
+	 * Enable GPIO9 as UART0_SIN
+	 */
+	val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0);
+	val &= ~QCA953X_GPIO_MUX_MASK(8);
+	val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8;
+	writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0);
+
+	/*
+	 * Enable GPIO10 output
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_OUT);
+	val |= QCA953X_GPIO(10);
+	writel(val, regs + AR71XX_GPIO_REG_OUT);
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	ddr_init();
+	return 0;
+}
diff --git a/board/sandbox/MAINTAINERS b/board/sandbox/MAINTAINERS
index 10d88a2..f5db773 100644
--- a/board/sandbox/MAINTAINERS
+++ b/board/sandbox/MAINTAINERS
@@ -4,3 +4,10 @@
 F:	board/sandbox/
 F:	include/configs/sandbox.h
 F:	configs/sandbox_defconfig
+
+SANDBOX_NOBLK BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/sandbox/
+F:	include/configs/sandbox.h
+F:	configs/sandbox_noblk_defconfig
diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
new file mode 100644
index 0000000..902abf5
--- /dev/null
+++ b/board/tplink/wdr4300/Kconfig
@@ -0,0 +1,15 @@
+if BOARD_TPLINK_WDR4300
+
+config SYS_VENDOR
+	default "tplink"
+
+config SYS_SOC
+	default "ath79"
+
+config SYS_BOARD
+	default "wdr4300"
+
+config SYS_CONFIG_NAME
+	default "tplink_wdr4300"
+
+endif
diff --git a/board/tplink/wdr4300/MAINTAINERS b/board/tplink/wdr4300/MAINTAINERS
new file mode 100644
index 0000000..db239c2
--- /dev/null
+++ b/board/tplink/wdr4300/MAINTAINERS
@@ -0,0 +1,6 @@
+TPLINK_WDR4300 BOARD
+M:	Marek Vasut <marex@denx.de>
+S:	Maintained
+F:	board/tplink/wdr4300/
+F:	include/configs/tplink_wdr4300.h
+F:	configs/tplink_wdr4300_defconfig
diff --git a/board/tplink/wdr4300/Makefile b/board/tplink/wdr4300/Makefile
new file mode 100644
index 0000000..4f0c296
--- /dev/null
+++ b/board/tplink/wdr4300/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= wdr4300.o
diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c
new file mode 100644
index 0000000..6e070fd
--- /dev/null
+++ b/board/tplink/wdr4300/wdr4300.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB
+static void wdr4300_usb_start(void)
+{
+	void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE,
+					      AR71XX_GPIO_SIZE, MAP_NOCACHE);
+	if (!gpio_regs)
+		return;
+
+	/* Power up the USB HUB. */
+	clrbits_be32(gpio_regs + AR71XX_GPIO_REG_OE, BIT(21) | BIT(22));
+	writel(BIT(21) | BIT(22), gpio_regs + AR71XX_GPIO_REG_SET);
+	mdelay(1);
+
+	ath79_usb_reset();
+}
+#else
+static inline void wdr4300_usb_start(void) {}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	void __iomem *regs;
+
+	regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+			   MAP_NOCACHE);
+
+	/* Assure JTAG is not disconnected. */
+	writel(0x40, regs + AR934X_GPIO_REG_FUNC);
+
+	/* Configure default GPIO input/output regs. */
+	writel(0x3031b, regs + AR71XX_GPIO_REG_OE);
+	writel(0x0f804, regs + AR71XX_GPIO_REG_OUT);
+
+	/* Configure pin multiplexing. */
+	writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC0);
+	writel(0x0b0a0980, regs + AR934X_GPIO_REG_OUT_FUNC1);
+	writel(0x00180000, regs + AR934X_GPIO_REG_OUT_FUNC2);
+	writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC3);
+	writel(0x0000004d, regs + AR934X_GPIO_REG_OUT_FUNC4);
+	writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC5);
+
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	ar934x_pll_init(560, 480, 240);
+	ar934x_ddr_init(560, 480, 240);
+#endif
+
+	wdr4300_usb_start();
+	ath79_eth_reset();
+
+	return 0;
+}
+#endif
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index eab9303..7de0212 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -7,17 +7,7 @@
 
 obj-y	:= board.o
 
-# Copied from Xilinx SDK 2014.4
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZED)		:= zed_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_MICROZED)	:= MicroZed_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZC702)		:= ZC702_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZC706)		:= ZC706_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZYBO)		:= zybo_hw_platform
-# If you want to use customized ps7_init_gpl.c/h,
-# enable CONFIG_ZYNQ_CUSTOM_INIT and put them into custom_hw_platform/.
-# This line must be placed at the bottom of the list because
-# it takes precedence over the default ones.
-hw-platform-$(CONFIG_ZYNQ_CUSTOM_INIT)		:= custom_hw_platform
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
 
 init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\
 	$(hw-platform-y)/ps7_init_gpl.o)
diff --git a/board/xilinx/zynq/custom_hw_platform/.gitignore b/board/xilinx/zynq/custom_hw_platform/.gitignore
deleted file mode 100644
index c455361..0000000
--- a/board/xilinx/zynq/custom_hw_platform/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-ps7_init_gpl.[ch]
diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
similarity index 100%
rename from board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c
rename to board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
similarity index 100%
rename from board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h
rename to board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
similarity index 100%
rename from board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c
rename to board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
similarity index 100%
rename from board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h
rename to board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
similarity index 100%
rename from board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c
rename to board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
similarity index 100%
rename from board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h
rename to board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
similarity index 100%
rename from board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c
rename to board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
similarity index 100%
rename from board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h
rename to board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
similarity index 100%
rename from board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c
rename to board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
similarity index 100%
rename from board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h
rename to board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 2ab3f19..90f00c6 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -1,8 +1,29 @@
 #
-# (C) Copyright 2014 - 2015 Xilinx, Inc.
+# (C) Copyright 2014 - 2016 Xilinx, Inc.
 # Michal Simek <michal.simek@xilinx.com>
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
 obj-y	:= zynqmp.o
+
+hw-platform-y :=$(shell echo $(CONFIG_SYS_CONFIG_NAME))
+
+init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
+	$(hw-platform-y)/psu_init_gpl.o)
+
+ifeq ($(init-objs),)
+ifneq ($(wildcard $(srctree)/$(src)/psu_init_gpl.c),)
+init-objs := psu_init_gpl.o
+$(if $(CONFIG_SPL_BUILD),\
+$(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/))
+endif
+endif
+
+obj-$(CONFIG_SPL_BUILD) += $(init-objs)
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
+
+# To include xil_io.h
+CFLAGS_psu_init_gpl.o := -I$(srctree)/$(src)
diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h
new file mode 100644
index 0000000..57ca4ad
--- /dev/null
+++ b/board/xilinx/zynqmp/xil_io.h
@@ -0,0 +1,35 @@
+/*
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H
+
+/* FIXME remove this when vivado is fixed */
+#include <asm/io.h>
+
+#define xil_printf(...)
+
+void Xil_ICacheEnable(void)
+{}
+
+void Xil_DCacheEnable(void)
+{}
+
+void Xil_ICacheDisable(void)
+{}
+
+void Xil_DCacheDisable(void)
+{}
+
+void Xil_Out32(unsigned long addr, unsigned long val)
+{
+	writel(val, addr);
+}
+
+int Xil_In32(unsigned long addr)
+{
+	return readl(addr);
+}
+
+#endif /* XIL_IO_H */
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 132d724..4623cd4 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -15,6 +15,7 @@
 #include <asm/io.h>
 #include <usb.h>
 #include <dwc3-uboot.h>
+#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -50,6 +51,22 @@
 	return 0;
 }
 
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
+{
+#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
+    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
+    defined(CONFIG_ZYNQ_EEPROM_BUS)
+	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
+
+	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
+			CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
+			ethaddr, 6))
+		printf("I2C EEPROM MAC address read failed\n");
+#endif
+
+	return 0;
+}
+
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 /*
  * fdt_get_reg - Fill buffer by information from DT
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 9336752..d51645c 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -593,6 +593,13 @@
 	     sound init   - set up sound system
 	     sound play   - play a sound
 
+config CMD_QFW
+	bool "qfw"
+	select QFW
+	help
+	  This provides access to the QEMU firmware interface.  The main
+	  feature is to allow easy loading of files passed to qemu-system
+	  via -kernel / -initrd
 endmenu
 
 config CMD_BOOTSTAGE
diff --git a/cmd/Makefile b/cmd/Makefile
index f95759e..9ce7861 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -105,6 +105,7 @@
 obj-y += pcmcia.o
 obj-$(CONFIG_CMD_PORTIO) += portio.o
 obj-$(CONFIG_CMD_PXE) += pxe.o
+obj-$(CONFIG_CMD_QFW) += qfw.o
 obj-$(CONFIG_CMD_READ) += read.o
 obj-$(CONFIG_CMD_REGINFO) += reginfo.o
 obj-$(CONFIG_CMD_REISER) += reiser.o
@@ -112,7 +113,7 @@
 obj-$(CONFIG_SANDBOX) += host.o
 obj-$(CONFIG_CMD_SATA) += sata.o
 obj-$(CONFIG_CMD_SF) += sf.o
-obj-$(CONFIG_CMD_SCSI) += scsi.o
+obj-$(CONFIG_SCSI) += scsi.o
 obj-$(CONFIG_CMD_SHA1SUM) += sha1sum.o
 obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
 obj-$(CONFIG_CMD_SOFTSWITCH) += softswitch.o
@@ -155,12 +156,6 @@
 obj-$(CONFIG_CMD_REGULATOR) += regulator.o
 endif # !CONFIG_SPL_BUILD
 
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_SATA_SUPPORT
-obj-$(CONFIG_CMD_SCSI) += scsi.o
-endif
-endif # CONFIG_SPL_BUILD
-
 obj-$(CONFIG_CMD_BLOB) += blob.o
 
 # core command
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 8eda68b..1c4bed9 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -341,6 +341,8 @@
 	print_eth(0);
 	printf("ip_addr     = %s\n", getenv("ipaddr"));
 	printf("baudrate    = %u bps\n", gd->baudrate);
+	print_num("relocaddr", gd->relocaddr);
+	print_num("reloc off", gd->reloc_off);
 
 	return 0;
 }
diff --git a/cmd/disk.c b/cmd/disk.c
index 2fd1717..fcc4123 100644
--- a/cmd/disk.c
+++ b/cmd/disk.c
@@ -8,7 +8,7 @@
 #include <command.h>
 #include <part.h>
 
-#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_SCSI) || \
+#if defined(CONFIG_CMD_IDE) || defined(CONFIG_SCSI) || \
 	defined(CONFIG_USB_STORAGE)
 int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc,
 		    char *const argv[])
diff --git a/cmd/eeprom.c b/cmd/eeprom.c
index e5457ba..0a0e4a2 100644
--- a/cmd/eeprom.c
+++ b/cmd/eeprom.c
@@ -24,6 +24,7 @@
 #include <config.h>
 #include <command.h>
 #include <i2c.h>
+#include <eeprom_layout.h>
 
 #ifndef	CONFIG_SYS_I2C_SPEED
 #define	CONFIG_SYS_I2C_SPEED	50000
@@ -72,7 +73,7 @@
 #endif
 
 	/* I2C EEPROM */
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
 #if defined(CONFIG_SYS_I2C)
 	if (bus >= 0)
 		i2c_set_bus_num(bus);
@@ -207,63 +208,243 @@
 	return ret;
 }
 
-static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int parse_numeric_param(char *str)
 {
-	const char *const fmt =
-		"\nEEPROM @0x%lX %s: addr %08lx  off %04lx  count %ld ... ";
-	char * const *args = &argv[2];
-	int rcode;
-	ulong dev_addr, addr, off, cnt;
-	int bus_addr;
+	char *endptr;
+	int value = simple_strtol(str, &endptr, 16);
 
-	switch (argc) {
+	return (*endptr != '\0') ? -1 : value;
+}
+
+/**
+ * parse_i2c_bus_addr - parse the i2c bus and i2c devaddr parameters
+ *
+ * @i2c_bus:	address to store the i2c bus
+ * @i2c_addr:	address to store the device i2c address
+ * @argc:	count of command line arguments left to parse
+ * @argv:	command line arguments left to parse
+ * @argc_no_bus_addr:	argc value we expect to see when bus & addr aren't given
+ *
+ * @returns:	number of arguments parsed or CMD_RET_USAGE if error
+ */
+static int parse_i2c_bus_addr(int *i2c_bus, ulong *i2c_addr, int argc,
+			      char * const argv[], int argc_no_bus_addr)
+{
+	int argc_no_bus = argc_no_bus_addr + 1;
+	int argc_bus_addr = argc_no_bus_addr + 2;
+
 #ifdef CONFIG_SYS_DEF_EEPROM_ADDR
-	case 5:
-		bus_addr = -1;
-		dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
-		break;
+	if (argc == argc_no_bus_addr) {
+		*i2c_bus = -1;
+		*i2c_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
+
+		return 0;
+	}
 #endif
-	case 6:
-		bus_addr = -1;
-		dev_addr = simple_strtoul(*args++, NULL, 16);
-		break;
-	case 7:
-		bus_addr = simple_strtoul(*args++, NULL, 16);
-		dev_addr = simple_strtoul(*args++, NULL, 16);
-		break;
-	default:
-		return CMD_RET_USAGE;
+	if (argc == argc_no_bus) {
+		*i2c_bus = -1;
+		*i2c_addr = parse_numeric_param(argv[0]);
+
+		return 1;
 	}
 
-	addr = simple_strtoul(*args++, NULL, 16);
-	off = simple_strtoul(*args++, NULL, 16);
-	cnt = simple_strtoul(*args++, NULL, 16);
+	if (argc == argc_bus_addr) {
+		*i2c_bus = parse_numeric_param(argv[0]);
+		*i2c_addr = parse_numeric_param(argv[1]);
 
-	eeprom_init(bus_addr);
-
-	if (strcmp(argv[1], "read") == 0) {
-		printf(fmt, dev_addr, argv[1], addr, off, cnt);
-
-		rcode = eeprom_read(dev_addr, off, (uchar *)addr, cnt);
-
-		puts("done\n");
-		return rcode;
-	} else if (strcmp(argv[1], "write") == 0) {
-		printf(fmt, dev_addr, argv[1], addr, off, cnt);
-
-		rcode = eeprom_write(dev_addr, off, (uchar *)addr, cnt);
-
-		puts("done\n");
-		return rcode;
+		return 2;
 	}
 
 	return CMD_RET_USAGE;
 }
 
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+
+__weak int eeprom_parse_layout_version(char *str)
+{
+	return LAYOUT_VERSION_UNRECOGNIZED;
+}
+
+static unsigned char eeprom_buf[CONFIG_SYS_EEPROM_SIZE];
+
+#ifndef CONFIG_EEPROM_LAYOUT_HELP_STRING
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "<not defined>"
+#endif
+
+#endif
+
+enum eeprom_action {
+	EEPROM_READ,
+	EEPROM_WRITE,
+	EEPROM_PRINT,
+	EEPROM_UPDATE,
+	EEPROM_ACTION_INVALID,
+};
+
+static enum eeprom_action parse_action(char *cmd)
+{
+	if (!strncmp(cmd, "read", 4))
+		return EEPROM_READ;
+	if (!strncmp(cmd, "write", 5))
+		return EEPROM_WRITE;
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+	if (!strncmp(cmd, "print", 5))
+		return EEPROM_PRINT;
+	if (!strncmp(cmd, "update", 6))
+		return EEPROM_UPDATE;
+#endif
+
+	return EEPROM_ACTION_INVALID;
+}
+
+static int eeprom_execute_command(enum eeprom_action action, int i2c_bus,
+				  ulong i2c_addr, int layout_ver, char *key,
+				  char *value, ulong addr, ulong off, ulong cnt)
+{
+	int rcode = 0;
+	const char *const fmt =
+		"\nEEPROM @0x%lX %s: addr %08lx  off %04lx  count %ld ... ";
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+	struct eeprom_layout layout;
+#endif
+
+	if (action == EEPROM_ACTION_INVALID)
+		return CMD_RET_USAGE;
+
+	eeprom_init(i2c_bus);
+	if (action == EEPROM_READ) {
+		printf(fmt, i2c_addr, "read", addr, off, cnt);
+
+		rcode = eeprom_read(i2c_addr, off, (uchar *)addr, cnt);
+
+		puts("done\n");
+		return rcode;
+	} else if (action == EEPROM_WRITE) {
+		printf(fmt, i2c_addr, "write", addr, off, cnt);
+
+		rcode = eeprom_write(i2c_addr, off, (uchar *)addr, cnt);
+
+		puts("done\n");
+		return rcode;
+	}
+
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+	rcode = eeprom_read(i2c_addr, 0, eeprom_buf, CONFIG_SYS_EEPROM_SIZE);
+	if (rcode < 0)
+		return rcode;
+
+	eeprom_layout_setup(&layout, eeprom_buf, CONFIG_SYS_EEPROM_SIZE,
+			    layout_ver);
+
+	if (action == EEPROM_PRINT) {
+		layout.print(&layout);
+		return 0;
+	}
+
+	layout.update(&layout, key, value);
+
+	rcode = eeprom_write(i2c_addr, 0, layout.data, CONFIG_SYS_EEPROM_SIZE);
+#endif
+
+	return rcode;
+}
+
+#define NEXT_PARAM(argc, index)	{ (argc)--; (index)++; }
+int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int layout_ver = LAYOUT_VERSION_AUTODETECT;
+	enum eeprom_action action = EEPROM_ACTION_INVALID;
+	int i2c_bus = -1, index = 0;
+	ulong i2c_addr = -1, addr = 0, cnt = 0, off = 0;
+	int ret;
+	char *field_name = "";
+	char *field_value = "";
+
+	if (argc <= 1)
+		return CMD_RET_USAGE;
+
+	NEXT_PARAM(argc, index); /* Skip program name */
+
+	action = parse_action(argv[index]);
+	NEXT_PARAM(argc, index);
+
+	if (action == EEPROM_ACTION_INVALID)
+		return CMD_RET_USAGE;
+
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+	if (action == EEPROM_PRINT || action == EEPROM_UPDATE) {
+		if (!strcmp(argv[index], "-l")) {
+			NEXT_PARAM(argc, index);
+			layout_ver = eeprom_parse_layout_version(argv[index]);
+			NEXT_PARAM(argc, index);
+		}
+	}
+#endif
+
+	switch (action) {
+	case EEPROM_READ:
+	case EEPROM_WRITE:
+		ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc,
+					 argv + index, 3);
+		break;
+	case EEPROM_PRINT:
+		ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc,
+					 argv + index, 0);
+		break;
+	case EEPROM_UPDATE:
+		ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc,
+					 argv + index, 2);
+		break;
+	default:
+		/* Get compiler to stop whining */
+		return CMD_RET_USAGE;
+	}
+
+	if (ret == CMD_RET_USAGE)
+		return ret;
+
+	while (ret--)
+		NEXT_PARAM(argc, index);
+
+	if (action == EEPROM_READ || action == EEPROM_WRITE) {
+		addr = parse_numeric_param(argv[index]);
+		NEXT_PARAM(argc, index);
+		off = parse_numeric_param(argv[index]);
+		NEXT_PARAM(argc, index);
+		cnt = parse_numeric_param(argv[index]);
+	}
+
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+	if (action == EEPROM_UPDATE) {
+		field_name = argv[index];
+		NEXT_PARAM(argc, index);
+		field_value = argv[index];
+		NEXT_PARAM(argc, index);
+	}
+#endif
+
+	return eeprom_execute_command(action, i2c_bus, i2c_addr, layout_ver,
+				      field_name, field_value, addr, off, cnt);
+}
+
 U_BOOT_CMD(
-	eeprom,	7,	1,	do_eeprom,
+	eeprom,	8,	1,	do_eeprom,
 	"EEPROM sub-system",
 	"read  <bus> <devaddr> addr off cnt\n"
 	"eeprom write <bus> <devaddr> addr off cnt\n"
 	"       - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+	"\n"
+	"eeprom print [-l <layout_version>] <bus> <devaddr>\n"
+	"       - Print layout fields and their data in human readable format\n"
+	"eeprom update [-l <layout_version>] <bus> <devaddr> field_name field_value\n"
+	"       - Update a specific eeprom field with new data.\n"
+	"         The new data must be written in the same human readable format as shown by the print command.\n"
+	"\n"
+	"LAYOUT VERSIONS\n"
+	"The -l option can be used to force the command to interpret the EEPROM data using the chosen layout.\n"
+	"If the -l option is omitted, the command will auto detect the layout based on the data in the EEPROM.\n"
+	"The values which can be provided with the -l option are:\n"
+	CONFIG_EEPROM_LAYOUT_HELP_STRING"\n"
+#endif
 )
diff --git a/cmd/ide.c b/cmd/ide.c
index c4c08c8..c942744 100644
--- a/cmd/ide.c
+++ b/cmd/ide.c
@@ -29,64 +29,9 @@
 # include <status_led.h>
 #endif
 
-#ifdef __PPC__
-# define EIEIO		__asm__ volatile ("eieio")
-# define SYNC		__asm__ volatile ("sync")
-#else
-# define EIEIO		/* nothing */
-# define SYNC		/* nothing */
-#endif
-
-/* ------------------------------------------------------------------------- */
-
 /* Current I/O Device	*/
 static int curr_device = -1;
 
-/* Current offset for IDE0 / IDE1 bus access	*/
-ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS] = {
-#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
-	CONFIG_SYS_ATA_IDE0_OFFSET,
-#endif
-#if defined(CONFIG_SYS_ATA_IDE1_OFFSET) && (CONFIG_SYS_IDE_MAXBUS > 1)
-	CONFIG_SYS_ATA_IDE1_OFFSET,
-#endif
-};
-
-static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
-
-struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_IDE_RESET
-static void  ide_reset (void);
-#else
-#define ide_reset()	/* dummy */
-#endif
-
-static void ide_ident(struct blk_desc *dev_desc);
-static uchar ide_wait  (int dev, ulong t);
-
-#define IDE_TIME_OUT	2000	/* 2 sec timeout */
-
-#define ATAPI_TIME_OUT	7000	/* 7 sec timeout (5 sec seems to work...) */
-
-#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
-
-static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
-
-#ifndef CONFIG_SYS_ATA_PORT_ADDR
-#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
-#endif
-
-#ifdef CONFIG_ATAPI
-static void	atapi_inquiry(struct blk_desc *dev_desc);
-static ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr,
-			lbaint_t blkcnt, void *buffer);
-#endif
-
-
-/* ------------------------------------------------------------------------- */
-
 int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
 	int rcode = 0;
@@ -106,79 +51,41 @@
 			ide_init();
 			return 0;
 		} else if (strncmp(argv[1], "inf", 3) == 0) {
-			int i;
-
-			putc('\n');
-
-			for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
-				if (ide_dev_desc[i].type == DEV_TYPE_UNKNOWN)
-					continue;  /* list only known devices */
-				printf("IDE device %d: ", i);
-				dev_print(&ide_dev_desc[i]);
-			}
+			blk_list_devices(IF_TYPE_IDE);
 			return 0;
 
 		} else if (strncmp(argv[1], "dev", 3) == 0) {
-			if ((curr_device < 0)
-			    || (curr_device >= CONFIG_SYS_IDE_MAXDEVICE)) {
-				puts("\nno IDE devices available\n");
-				return 1;
+			if (blk_print_device_num(IF_TYPE_IDE, curr_device)) {
+				printf("\nno IDE devices available\n");
+				return CMD_RET_FAILURE;
 			}
-			printf("\nIDE device %d: ", curr_device);
-			dev_print(&ide_dev_desc[curr_device]);
+
 			return 0;
 		} else if (strncmp(argv[1], "part", 4) == 0) {
-			int dev, ok;
-
-			for (ok = 0, dev = 0;
-			     dev < CONFIG_SYS_IDE_MAXDEVICE;
-			     ++dev) {
-				if (ide_dev_desc[dev].part_type !=
-				    PART_TYPE_UNKNOWN) {
-					++ok;
-					if (dev)
-						putc('\n');
-					part_print(&ide_dev_desc[dev]);
-				}
-			}
-			if (!ok) {
-				puts("\nno IDE devices available\n");
-				rcode++;
-			}
-			return rcode;
+			if (blk_list_part(IF_TYPE_IDE))
+				printf("\nno IDE devices available\n");
+			return 1;
 		}
 		return CMD_RET_USAGE;
 	case 3:
 		if (strncmp(argv[1], "dev", 3) == 0) {
-			int dev = (int) simple_strtoul(argv[2], NULL, 10);
+			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 
-			printf("\nIDE device %d: ", dev);
-			if (dev >= CONFIG_SYS_IDE_MAXDEVICE) {
-				puts("unknown device\n");
-				return 1;
+			if (!blk_show_device(IF_TYPE_IDE, dev)) {
+				curr_device = dev;
+				printf("... is now current device\n");
+			} else {
+				return CMD_RET_FAILURE;
 			}
-			dev_print(&ide_dev_desc[dev]);
-			/*ide_print (dev); */
-
-			if (ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
-				return 1;
-
-			curr_device = dev;
-
-			puts("... is now current device\n");
-
 			return 0;
 		} else if (strncmp(argv[1], "part", 4) == 0) {
-			int dev = (int) simple_strtoul(argv[2], NULL, 10);
+			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 
-			if (ide_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
-				part_print(&ide_dev_desc[dev]);
-			} else {
-				printf("\nIDE device %d not available\n",
-				       dev);
-				rcode = 1;
+			if (blk_print_part_devnum(IF_TYPE_IDE, dev)) {
+				printf("\nIDE device %d not available\n", dev);
+				return CMD_RET_FAILURE;
 			}
-			return rcode;
+			return 1;
 		}
 
 		return CMD_RET_USAGE;
@@ -188,26 +95,22 @@
 		if (strcmp(argv[1], "read") == 0) {
 			ulong addr = simple_strtoul(argv[2], NULL, 16);
 			ulong cnt = simple_strtoul(argv[4], NULL, 16);
-			struct blk_desc *dev_desc;
 			ulong n;
 
 #ifdef CONFIG_SYS_64BIT_LBA
 			lbaint_t blk = simple_strtoull(argv[3], NULL, 16);
 
-			printf("\nIDE read: device %d block # %lld, count %ld ... ",
-				curr_device, blk, cnt);
+			printf("\nIDE read: device %d block # %lld, count %ld...",
+			       curr_device, blk, cnt);
 #else
 			lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
 
-			printf("\nIDE read: device %d block # %ld, count %ld ... ",
-				curr_device, blk, cnt);
+			printf("\nIDE read: device %d block # %ld, count %ld...",
+			       curr_device, blk, cnt);
 #endif
 
-			dev_desc = &ide_dev_desc[curr_device];
-			n = blk_dread(dev_desc, blk, cnt, (ulong *)addr);
-			/* flush cache after read */
-			flush_cache(addr,
-				    cnt * ide_dev_desc[curr_device].blksz);
+			n = blk_read_devnum(IF_TYPE_IDE, curr_device, blk, cnt,
+					    (ulong *)addr);
 
 			printf("%ld blocks read: %s\n",
 			       n, (n == cnt) ? "OK" : "ERROR");
@@ -223,19 +126,19 @@
 #ifdef CONFIG_SYS_64BIT_LBA
 			lbaint_t blk = simple_strtoull(argv[3], NULL, 16);
 
-			printf("\nIDE write: device %d block # %lld, count %ld ... ",
-				curr_device, blk, cnt);
+			printf("\nIDE write: device %d block # %lld, count %ld...",
+			       curr_device, blk, cnt);
 #else
 			lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
 
-			printf("\nIDE write: device %d block # %ld, count %ld ... ",
-				curr_device, blk, cnt);
+			printf("\nIDE write: device %d block # %ld, count %ld...",
+			       curr_device, blk, cnt);
 #endif
-			n = ide_write(&ide_dev_desc[curr_device], blk, cnt,
-				      (ulong *)addr);
+			n = blk_write_devnum(IF_TYPE_IDE, curr_device, blk, cnt,
+					     (ulong *)addr);
 
-			printf("%ld blocks written: %s\n",
-				n, (n == cnt) ? "OK" : "ERROR");
+			printf("%ld blocks written: %s\n", n,
+			       n == cnt ? "OK" : "ERROR");
 			if (n == cnt)
 				return 0;
 			else
@@ -253,1195 +156,6 @@
 	return common_diskboot(cmdtp, "ide", argc, argv);
 }
 
-/* ------------------------------------------------------------------------- */
-
-__weak void ide_led(uchar led, uchar status)
-{
-#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
-	static uchar led_buffer;	/* Buffer for current LED status */
-
-	uchar *led_port = LED_PORT;
-
-	if (status)		/* switch LED on        */
-		led_buffer |= led;
-	else			/* switch LED off       */
-		led_buffer &= ~led;
-
-	*led_port = led_buffer;
-#endif
-}
-
-#ifndef CONFIG_IDE_LED	/* define LED macros, they are not used anyways */
-# define DEVICE_LED(x) 0
-# define LED_IDE1 1
-# define LED_IDE2 2
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-__weak void ide_outb(int dev, int port, unsigned char val)
-{
-	debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
-	      dev, port, val,
-	      (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
-
-#if defined(CONFIG_IDE_AHB)
-	if (port) {
-		/* write command */
-		ide_write_register(dev, port, val);
-	} else {
-		/* write data */
-		outb(val, (ATA_CURR_BASE(dev)));
-	}
-#else
-	outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
-#endif
-}
-
-__weak unsigned char ide_inb(int dev, int port)
-{
-	uchar val;
-
-#if defined(CONFIG_IDE_AHB)
-	val = ide_read_register(dev, port);
-#else
-	val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
-#endif
-
-	debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
-	      dev, port,
-	      (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
-	return val;
-}
-
-void ide_init(void)
-{
-	unsigned char c;
-	int i, bus;
-
-#ifdef CONFIG_IDE_8xx_PCCARD
-	extern int ide_devices_found;	/* Initialized in check_ide_device() */
-#endif /* CONFIG_IDE_8xx_PCCARD */
-
-#ifdef CONFIG_IDE_PREINIT
-	WATCHDOG_RESET();
-
-	if (ide_preinit()) {
-		puts("ide_preinit failed\n");
-		return;
-	}
-#endif /* CONFIG_IDE_PREINIT */
-
-	WATCHDOG_RESET();
-
-	/*
-	 * Reset the IDE just to be sure.
-	 * Light LED's to show
-	 */
-	ide_led((LED_IDE1 | LED_IDE2), 1);	/* LED's on     */
-
-	/* ATAPI Drives seems to need a proper IDE Reset */
-	ide_reset();
-
-#ifdef CONFIG_IDE_INIT_POSTRESET
-	WATCHDOG_RESET();
-
-	if (ide_init_postreset()) {
-		puts("ide_preinit_postreset failed\n");
-		return;
-	}
-#endif /* CONFIG_IDE_INIT_POSTRESET */
-
-	/*
-	 * Wait for IDE to get ready.
-	 * According to spec, this can take up to 31 seconds!
-	 */
-	for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
-		int dev =
-			bus * (CONFIG_SYS_IDE_MAXDEVICE /
-			       CONFIG_SYS_IDE_MAXBUS);
-
-#ifdef CONFIG_IDE_8xx_PCCARD
-		/* Skip non-ide devices from probing */
-		if ((ide_devices_found & (1 << bus)) == 0) {
-			ide_led((LED_IDE1 | LED_IDE2), 0);	/* LED's off */
-			continue;
-		}
-#endif
-		printf("Bus %d: ", bus);
-
-		ide_bus_ok[bus] = 0;
-
-		/* Select device
-		 */
-		udelay(100000);	/* 100 ms */
-		ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
-		udelay(100000);	/* 100 ms */
-		i = 0;
-		do {
-			udelay(10000);	/* 10 ms */
-
-			c = ide_inb(dev, ATA_STATUS);
-			i++;
-			if (i > (ATA_RESET_TIME * 100)) {
-				puts("** Timeout **\n");
-				/* LED's off */
-				ide_led((LED_IDE1 | LED_IDE2), 0);
-				return;
-			}
-			if ((i >= 100) && ((i % 100) == 0))
-				putc('.');
-
-		} while (c & ATA_STAT_BUSY);
-
-		if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
-			puts("not available  ");
-			debug("Status = 0x%02X ", c);
-#ifndef CONFIG_ATAPI		/* ATAPI Devices do not set DRDY */
-		} else if ((c & ATA_STAT_READY) == 0) {
-			puts("not available  ");
-			debug("Status = 0x%02X ", c);
-#endif
-		} else {
-			puts("OK ");
-			ide_bus_ok[bus] = 1;
-		}
-		WATCHDOG_RESET();
-	}
-
-	putc('\n');
-
-	ide_led((LED_IDE1 | LED_IDE2), 0);	/* LED's off    */
-
-	curr_device = -1;
-	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
-		int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
-		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
-		ide_dev_desc[i].if_type = IF_TYPE_IDE;
-		ide_dev_desc[i].devnum = i;
-		ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
-		ide_dev_desc[i].blksz = 0;
-		ide_dev_desc[i].log2blksz =
-			LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
-		ide_dev_desc[i].lba = 0;
-		ide_dev_desc[i].block_read = ide_read;
-		ide_dev_desc[i].block_write = ide_write;
-		if (!ide_bus_ok[IDE_BUS(i)])
-			continue;
-		ide_led(led, 1);	/* LED on       */
-		ide_ident(&ide_dev_desc[i]);
-		ide_led(led, 0);	/* LED off      */
-		dev_print(&ide_dev_desc[i]);
-
-		if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
-			/* initialize partition type */
-			part_init(&ide_dev_desc[i]);
-			if (curr_device < 0)
-				curr_device = i;
-		}
-	}
-	WATCHDOG_RESET();
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *ide_get_dev(int dev)
-{
-	return (dev < CONFIG_SYS_IDE_MAXDEVICE) ? &ide_dev_desc[dev] : NULL;
-}
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-/* We only need to swap data if we are running on a big endian cpu. */
-#if defined(__LITTLE_ENDIAN)
-__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
-	ide_input_data(dev, sect_buf, words);
-}
-#else
-__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
-	volatile ushort *pbuf =
-		(ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	ushort *dbuf = (ushort *) sect_buf;
-
-	debug("in input swap data base for read is %lx\n",
-	      (unsigned long) pbuf);
-
-	while (words--) {
-#ifdef __MIPS__
-		*dbuf++ = swab16p((u16 *) pbuf);
-		*dbuf++ = swab16p((u16 *) pbuf);
-#else
-		*dbuf++ = ld_le16(pbuf);
-		*dbuf++ = ld_le16(pbuf);
-#endif /* !MIPS */
-	}
-}
-#endif /* __LITTLE_ENDIAN */
-
-
-#if defined(CONFIG_IDE_SWAP_IO)
-__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
-{
-	ushort *dbuf;
-	volatile ushort *pbuf;
-
-	pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	dbuf = (ushort *) sect_buf;
-	while (words--) {
-		EIEIO;
-		*pbuf = *dbuf++;
-		EIEIO;
-		*pbuf = *dbuf++;
-	}
-}
-#else  /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
-{
-#if defined(CONFIG_IDE_AHB)
-	ide_write_data(dev, sect_buf, words);
-#else
-	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
-#endif
-}
-#endif /* CONFIG_IDE_SWAP_IO */
-
-#if defined(CONFIG_IDE_SWAP_IO)
-__weak void ide_input_data(int dev, ulong *sect_buf, int words)
-{
-	ushort *dbuf;
-	volatile ushort *pbuf;
-
-	pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	dbuf = (ushort *) sect_buf;
-
-	debug("in input data base for read is %lx\n", (unsigned long) pbuf);
-
-	while (words--) {
-		EIEIO;
-		*dbuf++ = *pbuf;
-		EIEIO;
-		*dbuf++ = *pbuf;
-	}
-}
-#else  /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_input_data(int dev, ulong *sect_buf, int words)
-{
-#if defined(CONFIG_IDE_AHB)
-	ide_read_data(dev, sect_buf, words);
-#else
-	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
-#endif
-}
-
-#endif /* CONFIG_IDE_SWAP_IO */
-
-/* -------------------------------------------------------------------------
- */
-static void ide_ident(struct blk_desc *dev_desc)
-{
-	unsigned char c;
-	hd_driveid_t iop;
-
-#ifdef CONFIG_ATAPI
-	int retries = 0;
-#endif
-	int device;
-
-	device = dev_desc->devnum;
-	printf("  Device %d: ", device);
-
-	ide_led(DEVICE_LED(device), 1);	/* LED on       */
-	/* Select device
-	 */
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-	dev_desc->if_type = IF_TYPE_IDE;
-#ifdef CONFIG_ATAPI
-
-	retries = 0;
-
-	/* Warning: This will be tricky to read */
-	while (retries <= 1) {
-		/* check signature */
-		if ((ide_inb(device, ATA_SECT_CNT) == 0x01) &&
-		    (ide_inb(device, ATA_SECT_NUM) == 0x01) &&
-		    (ide_inb(device, ATA_CYL_LOW) == 0x14) &&
-		    (ide_inb(device, ATA_CYL_HIGH) == 0xEB)) {
-			/* ATAPI Signature found */
-			dev_desc->if_type = IF_TYPE_ATAPI;
-			/*
-			 * Start Ident Command
-			 */
-			ide_outb(device, ATA_COMMAND, ATAPI_CMD_IDENT);
-			/*
-			 * Wait for completion - ATAPI devices need more time
-			 * to become ready
-			 */
-			c = ide_wait(device, ATAPI_TIME_OUT);
-		} else
-#endif
-		{
-			/*
-			 * Start Ident Command
-			 */
-			ide_outb(device, ATA_COMMAND, ATA_CMD_IDENT);
-
-			/*
-			 * Wait for completion
-			 */
-			c = ide_wait(device, IDE_TIME_OUT);
-		}
-		ide_led(DEVICE_LED(device), 0);	/* LED off      */
-
-		if (((c & ATA_STAT_DRQ) == 0) ||
-		    ((c & (ATA_STAT_FAULT | ATA_STAT_ERR)) != 0)) {
-#ifdef CONFIG_ATAPI
-			{
-				/*
-				 * Need to soft reset the device
-				 * in case it's an ATAPI...
-				 */
-				debug("Retrying...\n");
-				ide_outb(device, ATA_DEV_HD,
-					 ATA_LBA | ATA_DEVICE(device));
-				udelay(100000);
-				ide_outb(device, ATA_COMMAND, 0x08);
-				udelay(500000);	/* 500 ms */
-			}
-			/*
-			 * Select device
-			 */
-			ide_outb(device, ATA_DEV_HD,
-				 ATA_LBA | ATA_DEVICE(device));
-			retries++;
-#else
-			return;
-#endif
-		}
-#ifdef CONFIG_ATAPI
-		else
-			break;
-	}			/* see above - ugly to read */
-
-	if (retries == 2)	/* Not found */
-		return;
-#endif
-
-	ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
-
-	ident_cpy((unsigned char *) dev_desc->revision, iop.fw_rev,
-		  sizeof(dev_desc->revision));
-	ident_cpy((unsigned char *) dev_desc->vendor, iop.model,
-		  sizeof(dev_desc->vendor));
-	ident_cpy((unsigned char *) dev_desc->product, iop.serial_no,
-		  sizeof(dev_desc->product));
-#ifdef __LITTLE_ENDIAN
-	/*
-	 * firmware revision, model, and serial number have Big Endian Byte
-	 * order in Word. Convert all three to little endian.
-	 *
-	 * See CF+ and CompactFlash Specification Revision 2.0:
-	 * 6.2.1.6: Identify Drive, Table 39 for more details
-	 */
-
-	strswab(dev_desc->revision);
-	strswab(dev_desc->vendor);
-	strswab(dev_desc->product);
-#endif /* __LITTLE_ENDIAN */
-
-	if ((iop.config & 0x0080) == 0x0080)
-		dev_desc->removable = 1;
-	else
-		dev_desc->removable = 0;
-
-#ifdef CONFIG_ATAPI
-	if (dev_desc->if_type == IF_TYPE_ATAPI) {
-		atapi_inquiry(dev_desc);
-		return;
-	}
-#endif /* CONFIG_ATAPI */
-
-#ifdef __BIG_ENDIAN
-	/* swap shorts */
-	dev_desc->lba = (iop.lba_capacity << 16) | (iop.lba_capacity >> 16);
-#else  /* ! __BIG_ENDIAN */
-	/*
-	 * do not swap shorts on little endian
-	 *
-	 * See CF+ and CompactFlash Specification Revision 2.0:
-	 * 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details.
-	 */
-	dev_desc->lba = iop.lba_capacity;
-#endif /* __BIG_ENDIAN */
-
-#ifdef CONFIG_LBA48
-	if (iop.command_set_2 & 0x0400) {	/* LBA 48 support */
-		dev_desc->lba48 = 1;
-		dev_desc->lba = (unsigned long long) iop.lba48_capacity[0] |
-			((unsigned long long) iop.lba48_capacity[1] << 16) |
-			((unsigned long long) iop.lba48_capacity[2] << 32) |
-			((unsigned long long) iop.lba48_capacity[3] << 48);
-	} else {
-		dev_desc->lba48 = 0;
-	}
-#endif /* CONFIG_LBA48 */
-	/* assuming HD */
-	dev_desc->type = DEV_TYPE_HARDDISK;
-	dev_desc->blksz = ATA_BLOCKSIZE;
-	dev_desc->log2blksz = LOG2(dev_desc->blksz);
-	dev_desc->lun = 0;	/* just to fill something in... */
-
-#if 0				/* only used to test the powersaving mode,
-				 * if enabled, the drive goes after 5 sec
-				 * in standby mode */
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-	c = ide_wait(device, IDE_TIME_OUT);
-	ide_outb(device, ATA_SECT_CNT, 1);
-	ide_outb(device, ATA_LBA_LOW, 0);
-	ide_outb(device, ATA_LBA_MID, 0);
-	ide_outb(device, ATA_LBA_HIGH, 0);
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-	ide_outb(device, ATA_COMMAND, 0xe3);
-	udelay(50);
-	c = ide_wait(device, IDE_TIME_OUT);	/* can't take over 500 ms */
-#endif
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-	       void *buffer)
-{
-	int device = block_dev->devnum;
-	ulong n = 0;
-	unsigned char c;
-	unsigned char pwrsave = 0;	/* power save */
-
-#ifdef CONFIG_LBA48
-	unsigned char lba48 = 0;
-
-	if (blknr & 0x0000fffff0000000ULL) {
-		/* more than 28 bits used, use 48bit mode */
-		lba48 = 1;
-	}
-#endif
-	debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n",
-	      device, blknr, blkcnt, (ulong) buffer);
-
-	ide_led(DEVICE_LED(device), 1);	/* LED on       */
-
-	/* Select device
-	 */
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-	c = ide_wait(device, IDE_TIME_OUT);
-
-	if (c & ATA_STAT_BUSY) {
-		printf("IDE read: device %d not ready\n", device);
-		goto IDE_READ_E;
-	}
-
-	/* first check if the drive is in Powersaving mode, if yes,
-	 * increase the timeout value */
-	ide_outb(device, ATA_COMMAND, ATA_CMD_CHK_PWR);
-	udelay(50);
-
-	c = ide_wait(device, IDE_TIME_OUT);	/* can't take over 500 ms */
-
-	if (c & ATA_STAT_BUSY) {
-		printf("IDE read: device %d not ready\n", device);
-		goto IDE_READ_E;
-	}
-	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
-		printf("No Powersaving mode %X\n", c);
-	} else {
-		c = ide_inb(device, ATA_SECT_CNT);
-		debug("Powersaving %02X\n", c);
-		if (c == 0)
-			pwrsave = 1;
-	}
-
-
-	while (blkcnt-- > 0) {
-
-		c = ide_wait(device, IDE_TIME_OUT);
-
-		if (c & ATA_STAT_BUSY) {
-			printf("IDE read: device %d not ready\n", device);
-			break;
-		}
-#ifdef CONFIG_LBA48
-		if (lba48) {
-			/* write high bits */
-			ide_outb(device, ATA_SECT_CNT, 0);
-			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
-#ifdef CONFIG_SYS_64BIT_LBA
-			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
-			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
-#else
-			ide_outb(device, ATA_LBA_MID, 0);
-			ide_outb(device, ATA_LBA_HIGH, 0);
-#endif
-		}
-#endif
-		ide_outb(device, ATA_SECT_CNT, 1);
-		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
-		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
-		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
-
-#ifdef CONFIG_LBA48
-		if (lba48) {
-			ide_outb(device, ATA_DEV_HD,
-				 ATA_LBA | ATA_DEVICE(device));
-			ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT);
-
-		} else
-#endif
-		{
-			ide_outb(device, ATA_DEV_HD, ATA_LBA |
-				 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
-			ide_outb(device, ATA_COMMAND, ATA_CMD_READ);
-		}
-
-		udelay(50);
-
-		if (pwrsave) {
-			/* may take up to 4 sec */
-			c = ide_wait(device, IDE_SPIN_UP_TIME_OUT);
-			pwrsave = 0;
-		} else {
-			/* can't take over 500 ms */
-			c = ide_wait(device, IDE_TIME_OUT);
-		}
-
-		if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
-		    ATA_STAT_DRQ) {
-			printf("Error (no IRQ) dev %d blk " LBAF ": status "
-			       "%#02x\n", device, blknr, c);
-			break;
-		}
-
-		ide_input_data(device, buffer, ATA_SECTORWORDS);
-		(void) ide_inb(device, ATA_STATUS);	/* clear IRQ */
-
-		++n;
-		++blknr;
-		buffer += ATA_BLOCKSIZE;
-	}
-IDE_READ_E:
-	ide_led(DEVICE_LED(device), 0);	/* LED off      */
-	return (n);
-}
-
-/* ------------------------------------------------------------------------- */
-
-
-ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-		const void *buffer)
-{
-	int device = block_dev->devnum;
-	ulong n = 0;
-	unsigned char c;
-
-#ifdef CONFIG_LBA48
-	unsigned char lba48 = 0;
-
-	if (blknr & 0x0000fffff0000000ULL) {
-		/* more than 28 bits used, use 48bit mode */
-		lba48 = 1;
-	}
-#endif
-
-	ide_led(DEVICE_LED(device), 1);	/* LED on       */
-
-	/* Select device
-	 */
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-
-	while (blkcnt-- > 0) {
-
-		c = ide_wait(device, IDE_TIME_OUT);
-
-		if (c & ATA_STAT_BUSY) {
-			printf("IDE read: device %d not ready\n", device);
-			goto WR_OUT;
-		}
-#ifdef CONFIG_LBA48
-		if (lba48) {
-			/* write high bits */
-			ide_outb(device, ATA_SECT_CNT, 0);
-			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
-#ifdef CONFIG_SYS_64BIT_LBA
-			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
-			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
-#else
-			ide_outb(device, ATA_LBA_MID, 0);
-			ide_outb(device, ATA_LBA_HIGH, 0);
-#endif
-		}
-#endif
-		ide_outb(device, ATA_SECT_CNT, 1);
-		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
-		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
-		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
-
-#ifdef CONFIG_LBA48
-		if (lba48) {
-			ide_outb(device, ATA_DEV_HD,
-				 ATA_LBA | ATA_DEVICE(device));
-			ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
-
-		} else
-#endif
-		{
-			ide_outb(device, ATA_DEV_HD, ATA_LBA |
-				 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
-			ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE);
-		}
-
-		udelay(50);
-
-		/* can't take over 500 ms */
-		c = ide_wait(device, IDE_TIME_OUT);
-
-		if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
-		    ATA_STAT_DRQ) {
-			printf("Error (no IRQ) dev %d blk " LBAF ": status "
-				"%#02x\n", device, blknr, c);
-			goto WR_OUT;
-		}
-
-		ide_output_data(device, buffer, ATA_SECTORWORDS);
-		c = ide_inb(device, ATA_STATUS);	/* clear IRQ */
-		++n;
-		++blknr;
-		buffer += ATA_BLOCKSIZE;
-	}
-WR_OUT:
-	ide_led(DEVICE_LED(device), 0);	/* LED off      */
-	return (n);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * copy src to dest, skipping leading and trailing blanks and null
- * terminate the string
- * "len" is the size of available memory including the terminating '\0'
- */
-static void ident_cpy(unsigned char *dst, unsigned char *src,
-		      unsigned int len)
-{
-	unsigned char *end, *last;
-
-	last = dst;
-	end = src + len - 1;
-
-	/* reserve space for '\0' */
-	if (len < 2)
-		goto OUT;
-
-	/* skip leading white space */
-	while ((*src) && (src < end) && (*src == ' '))
-		++src;
-
-	/* copy string, omitting trailing white space */
-	while ((*src) && (src < end)) {
-		*dst++ = *src;
-		if (*src++ != ' ')
-			last = dst;
-	}
-OUT:
-	*last = '\0';
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Wait until Busy bit is off, or timeout (in ms)
- * Return last status
- */
-static uchar ide_wait(int dev, ulong t)
-{
-	ulong delay = 10 * t;	/* poll every 100 us */
-	uchar c;
-
-	while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
-		udelay(100);
-		if (delay-- == 0)
-			break;
-	}
-	return (c);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_IDE_RESET
-extern void ide_set_reset(int idereset);
-
-static void ide_reset(void)
-{
-	int i;
-
-	curr_device = -1;
-	for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
-		ide_bus_ok[i] = 0;
-	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
-		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
-
-	ide_set_reset(1);	/* assert reset */
-
-	/* the reset signal shall be asserted for et least 25 us */
-	udelay(25);
-
-	WATCHDOG_RESET();
-
-	/* de-assert RESET signal */
-	ide_set_reset(0);
-
-	/* wait 250 ms */
-	for (i = 0; i < 250; ++i)
-		udelay(1000);
-}
-
-#endif /* CONFIG_IDE_RESET */
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_OF_IDE_FIXUP)
-int ide_device_present(int dev)
-{
-	if (dev >= CONFIG_SYS_IDE_MAXBUS)
-		return 0;
-	return (ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1);
-}
-#endif
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_ATAPI
-/****************************************************************************
- * ATAPI Support
- */
-
-#if defined(CONFIG_IDE_SWAP_IO)
-/* since ATAPI may use commands with not 4 bytes alligned length
- * we have our own transfer functions, 2 bytes alligned */
-__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
-	ushort *dbuf;
-	volatile ushort *pbuf;
-
-	pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	dbuf = (ushort *) sect_buf;
-
-	debug("in output data shorts base for read is %lx\n",
-	      (unsigned long) pbuf);
-
-	while (shorts--) {
-		EIEIO;
-		*pbuf = *dbuf++;
-	}
-}
-
-__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
-	ushort *dbuf;
-	volatile ushort *pbuf;
-
-	pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	dbuf = (ushort *) sect_buf;
-
-	debug("in input data shorts base for read is %lx\n",
-	      (unsigned long) pbuf);
-
-	while (shorts--) {
-		EIEIO;
-		*dbuf++ = *pbuf;
-	}
-}
-
-#else  /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
-	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
-}
-
-__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
-	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
-}
-
-#endif /* CONFIG_IDE_SWAP_IO */
-
-/*
- * Wait until (Status & mask) == res, or timeout (in ms)
- * Return last status
- * This is used since some ATAPI CD ROMs clears their Busy Bit first
- * and then they set their DRQ Bit
- */
-static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
-{
-	ulong delay = 10 * t;	/* poll every 100 us */
-	uchar c;
-
-	/* prevents to read the status before valid */
-	c = ide_inb(dev, ATA_DEV_CTL);
-
-	while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
-		/* break if error occurs (doesn't make sense to wait more) */
-		if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
-			break;
-		udelay(100);
-		if (delay-- == 0)
-			break;
-	}
-	return (c);
-}
-
-/*
- * issue an atapi command
- */
-unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
-			  unsigned char *buffer, int buflen)
-{
-	unsigned char c, err, mask, res;
-	int n;
-
-	ide_led(DEVICE_LED(device), 1);	/* LED on       */
-
-	/* Select device
-	 */
-	mask = ATA_STAT_BUSY | ATA_STAT_DRQ;
-	res = 0;
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
-	if ((c & mask) != res) {
-		printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
-		       c);
-		err = 0xFF;
-		goto AI_OUT;
-	}
-	/* write taskfile */
-	ide_outb(device, ATA_ERROR_REG, 0);	/* no DMA, no overlaped */
-	ide_outb(device, ATA_SECT_CNT, 0);
-	ide_outb(device, ATA_SECT_NUM, 0);
-	ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
-	ide_outb(device, ATA_CYL_HIGH,
-		 (unsigned char) ((buflen >> 8) & 0xFF));
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-
-	ide_outb(device, ATA_COMMAND, ATAPI_CMD_PACKET);
-	udelay(50);
-
-	mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
-	res = ATA_STAT_DRQ;
-	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
-
-	if ((c & mask) != res) {	/* DRQ must be 1, BSY 0 */
-		printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
-			device, c);
-		err = 0xFF;
-		goto AI_OUT;
-	}
-
-	/* write command block */
-	ide_output_data_shorts(device, (unsigned short *) ccb, ccblen / 2);
-
-	/* ATAPI Command written wait for completition */
-	udelay(5000);		/* device must set bsy */
-
-	mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
-	/*
-	 * if no data wait for DRQ = 0 BSY = 0
-	 * if data wait for DRQ = 1 BSY = 0
-	 */
-	res = 0;
-	if (buflen)
-		res = ATA_STAT_DRQ;
-	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
-	if ((c & mask) != res) {
-		if (c & ATA_STAT_ERR) {
-			err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
-			debug("atapi_issue 1 returned sense key %X status %02X\n",
-				err, c);
-		} else {
-			printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x)  status 0x%02x\n",
-				ccb[0], c);
-			err = 0xFF;
-		}
-		goto AI_OUT;
-	}
-	n = ide_inb(device, ATA_CYL_HIGH);
-	n <<= 8;
-	n += ide_inb(device, ATA_CYL_LOW);
-	if (n > buflen) {
-		printf("ERROR, transfer bytes %d requested only %d\n", n,
-		       buflen);
-		err = 0xff;
-		goto AI_OUT;
-	}
-	if ((n == 0) && (buflen < 0)) {
-		printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
-		err = 0xff;
-		goto AI_OUT;
-	}
-	if (n != buflen) {
-		debug("WARNING, transfer bytes %d not equal with requested %d\n",
-			n, buflen);
-	}
-	if (n != 0) {		/* data transfer */
-		debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
-		/* we transfer shorts */
-		n >>= 1;
-		/* ok now decide if it is an in or output */
-		if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
-			debug("Write to device\n");
-			ide_output_data_shorts(device,
-				(unsigned short *) buffer, n);
-		} else {
-			debug("Read from device @ %p shorts %d\n", buffer, n);
-			ide_input_data_shorts(device,
-				(unsigned short *) buffer, n);
-		}
-	}
-	udelay(5000);		/* seems that some CD ROMs need this... */
-	mask = ATA_STAT_BUSY | ATA_STAT_ERR;
-	res = 0;
-	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
-	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
-		err = (ide_inb(device, ATA_ERROR_REG) >> 4);
-		debug("atapi_issue 2 returned sense key %X status %X\n", err,
-		      c);
-	} else {
-		err = 0;
-	}
-AI_OUT:
-	ide_led(DEVICE_LED(device), 0);	/* LED off      */
-	return (err);
-}
-
-/*
- * sending the command to atapi_issue. If an status other than good
- * returns, an request_sense will be issued
- */
-
-#define ATAPI_DRIVE_NOT_READY	100
-#define ATAPI_UNIT_ATTN		10
-
-unsigned char atapi_issue_autoreq(int device,
-				  unsigned char *ccb,
-				  int ccblen,
-				  unsigned char *buffer, int buflen)
-{
-	unsigned char sense_data[18], sense_ccb[12];
-	unsigned char res, key, asc, ascq;
-	int notready, unitattn;
-
-	unitattn = ATAPI_UNIT_ATTN;
-	notready = ATAPI_DRIVE_NOT_READY;
-
-retry:
-	res = atapi_issue(device, ccb, ccblen, buffer, buflen);
-	if (res == 0)
-		return 0;	/* Ok */
-
-	if (res == 0xFF)
-		return 0xFF;	/* error */
-
-	debug("(auto_req)atapi_issue returned sense key %X\n", res);
-
-	memset(sense_ccb, 0, sizeof(sense_ccb));
-	memset(sense_data, 0, sizeof(sense_data));
-	sense_ccb[0] = ATAPI_CMD_REQ_SENSE;
-	sense_ccb[4] = 18;	/* allocation Length */
-
-	res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
-	key = (sense_data[2] & 0xF);
-	asc = (sense_data[12]);
-	ascq = (sense_data[13]);
-
-	debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
-	debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
-	      sense_data[0], key, asc, ascq);
-
-	if ((key == 0))
-		return 0;	/* ok device ready */
-
-	if ((key == 6) || (asc == 0x29) || (asc == 0x28)) { /* Unit Attention */
-		if (unitattn-- > 0) {
-			udelay(200 * 1000);
-			goto retry;
-		}
-		printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
-		goto error;
-	}
-	if ((asc == 0x4) && (ascq == 0x1)) {
-		/* not ready, but will be ready soon */
-		if (notready-- > 0) {
-			udelay(200 * 1000);
-			goto retry;
-		}
-		printf("Drive not ready, tried %d times\n",
-		       ATAPI_DRIVE_NOT_READY);
-		goto error;
-	}
-	if (asc == 0x3a) {
-		debug("Media not present\n");
-		goto error;
-	}
-
-	printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
-	       ascq);
-error:
-	debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
-	return (0xFF);
-}
-
-
-static void atapi_inquiry(struct blk_desc *dev_desc)
-{
-	unsigned char ccb[12];	/* Command descriptor block */
-	unsigned char iobuf[64];	/* temp buf */
-	unsigned char c;
-	int device;
-
-	device = dev_desc->devnum;
-	dev_desc->type = DEV_TYPE_UNKNOWN;	/* not yet valid */
-	dev_desc->block_read = atapi_read;
-
-	memset(ccb, 0, sizeof(ccb));
-	memset(iobuf, 0, sizeof(iobuf));
-
-	ccb[0] = ATAPI_CMD_INQUIRY;
-	ccb[4] = 40;		/* allocation Legnth */
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 40);
-
-	debug("ATAPI_CMD_INQUIRY returned %x\n", c);
-	if (c != 0)
-		return;
-
-	/* copy device ident strings */
-	ident_cpy((unsigned char *) dev_desc->vendor, &iobuf[8], 8);
-	ident_cpy((unsigned char *) dev_desc->product, &iobuf[16], 16);
-	ident_cpy((unsigned char *) dev_desc->revision, &iobuf[32], 5);
-
-	dev_desc->lun = 0;
-	dev_desc->lba = 0;
-	dev_desc->blksz = 0;
-	dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
-	dev_desc->type = iobuf[0] & 0x1f;
-
-	if ((iobuf[1] & 0x80) == 0x80)
-		dev_desc->removable = 1;
-	else
-		dev_desc->removable = 0;
-
-	memset(ccb, 0, sizeof(ccb));
-	memset(iobuf, 0, sizeof(iobuf));
-	ccb[0] = ATAPI_CMD_START_STOP;
-	ccb[4] = 0x03;		/* start */
-
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 0);
-
-	debug("ATAPI_CMD_START_STOP returned %x\n", c);
-	if (c != 0)
-		return;
-
-	memset(ccb, 0, sizeof(ccb));
-	memset(iobuf, 0, sizeof(iobuf));
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 0);
-
-	debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
-	if (c != 0)
-		return;
-
-	memset(ccb, 0, sizeof(ccb));
-	memset(iobuf, 0, sizeof(iobuf));
-	ccb[0] = ATAPI_CMD_READ_CAP;
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 8);
-	debug("ATAPI_CMD_READ_CAP returned %x\n", c);
-	if (c != 0)
-		return;
-
-	debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
-	      iobuf[0], iobuf[1], iobuf[2], iobuf[3],
-	      iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
-
-	dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
-		((unsigned long) iobuf[1] << 16) +
-		((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
-	dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
-		((unsigned long) iobuf[5] << 16) +
-		((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
-	dev_desc->log2blksz = LOG2(dev_desc->blksz);
-#ifdef CONFIG_LBA48
-	/* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
-	dev_desc->lba48 = 0;
-#endif
-	return;
-}
-
-
-/*
- * atapi_read:
- * we transfer only one block per command, since the multiple DRQ per
- * command is not yet implemented
- */
-#define ATAPI_READ_MAX_BYTES	2048	/* we read max 2kbytes */
-#define ATAPI_READ_BLOCK_SIZE	2048	/* assuming CD part */
-#define ATAPI_READ_MAX_BLOCK	(ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
-
-ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-		 void *buffer)
-{
-	int device = block_dev->devnum;
-	ulong n = 0;
-	unsigned char ccb[12];	/* Command descriptor block */
-	ulong cnt;
-
-	debug("atapi_read dev %d start " LBAF " blocks " LBAF " buffer at %lX\n",
-	      device, blknr, blkcnt, (ulong) buffer);
-
-	do {
-		if (blkcnt > ATAPI_READ_MAX_BLOCK)
-			cnt = ATAPI_READ_MAX_BLOCK;
-		else
-			cnt = blkcnt;
-
-		ccb[0] = ATAPI_CMD_READ_12;
-		ccb[1] = 0;	/* reserved */
-		ccb[2] = (unsigned char) (blknr >> 24) & 0xFF;	/* MSB Block */
-		ccb[3] = (unsigned char) (blknr >> 16) & 0xFF;	/*  */
-		ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
-		ccb[5] = (unsigned char) blknr & 0xFF;	/* LSB Block */
-		ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
-		ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
-		ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
-		ccb[9] = (unsigned char) cnt & 0xFF;	/* LSB Block */
-		ccb[10] = 0;	/* reserved */
-		ccb[11] = 0;	/* reserved */
-
-		if (atapi_issue_autoreq(device, ccb, 12,
-					(unsigned char *) buffer,
-					cnt * ATAPI_READ_BLOCK_SIZE)
-		    == 0xFF) {
-			return (n);
-		}
-		n += cnt;
-		blkcnt -= cnt;
-		blknr += cnt;
-		buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
-	} while (blkcnt > 0);
-	return (n);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#endif /* CONFIG_ATAPI */
-
 U_BOOT_CMD(ide, 5, 1, do_ide,
 	   "IDE sub-system",
 	   "reset - reset IDE controller\n"
diff --git a/cmd/mmc.c b/cmd/mmc.c
index c5454bf..eb4a547 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -314,12 +314,14 @@
 	}
 	/* Switch to the RPMB partition */
 	original_part = mmc->block_dev.hwpart;
-	if (mmc_select_hwpart(curr_device, MMC_PART_RPMB) != 0)
+	if (blk_select_hwpart_devnum(IF_TYPE_MMC, curr_device, MMC_PART_RPMB) !=
+	    0)
 		return CMD_RET_FAILURE;
 	ret = cp->cmd(cmdtp, flag, argc, argv);
 
 	/* Return to original partition */
-	if (mmc_select_hwpart(curr_device, original_part) != 0)
+	if (blk_select_hwpart_devnum(IF_TYPE_MMC, curr_device, original_part) !=
+	    0)
 		return CMD_RET_FAILURE;
 	return ret;
 }
@@ -346,7 +348,7 @@
 	printf("\nMMC read: dev # %d, block # %d, count %d ... ",
 	       curr_device, blk, cnt);
 
-	n = blk_dread(&mmc->block_dev, blk, cnt, addr);
+	n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
 	/* flush cache after read */
 	flush_cache((ulong)addr, cnt * 512); /* FIXME */
 	printf("%d blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR");
@@ -378,7 +380,7 @@
 		printf("Error: card is write protected!\n");
 		return CMD_RET_FAILURE;
 	}
-	n = blk_dwrite(&mmc->block_dev, blk, cnt, addr);
+	n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr);
 	printf("%d blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR");
 
 	return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
@@ -406,7 +408,7 @@
 		printf("Error: card is write protected!\n");
 		return CMD_RET_FAILURE;
 	}
-	n = blk_derase(&mmc->block_dev, blk, cnt);
+	n = blk_derase(mmc_get_blk_desc(mmc), blk, cnt);
 	printf("%d blocks erased: %s\n", n, (n == cnt) ? "OK" : "ERROR");
 
 	return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
@@ -432,7 +434,7 @@
 	if (!mmc)
 		return CMD_RET_FAILURE;
 
-	mmc_dev = mmc_get_dev(curr_device);
+	mmc_dev = blk_get_devnum_by_type(IF_TYPE_MMC, curr_device);
 	if (mmc_dev != NULL && mmc_dev->type != DEV_TYPE_UNKNOWN) {
 		part_print(mmc_dev);
 		return CMD_RET_SUCCESS;
@@ -467,7 +469,7 @@
 	if (!mmc)
 		return CMD_RET_FAILURE;
 
-	ret = mmc_select_hwpart(dev, part);
+	ret = blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part);
 	printf("switch to partitions #%d, %s\n",
 	       part, (!ret) ? "OK" : "ERROR");
 	if (ret)
@@ -478,7 +480,7 @@
 		printf("mmc%d is current device\n", curr_device);
 	else
 		printf("mmc%d(part %d) is current device\n",
-		       curr_device, mmc->block_dev.hwpart);
+		       curr_device, mmc_get_blk_desc(mmc)->hwpart);
 
 	return CMD_RET_SUCCESS;
 }
diff --git a/cmd/qfw.c b/cmd/qfw.c
new file mode 100644
index 0000000..12436ec
--- /dev/null
+++ b/cmd/qfw.c
@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <qfw.h>
+
+/*
+ * This function prepares kernel for zboot. It loads kernel data
+ * to 'load_addr', initrd to 'initrd_addr' and kernel command
+ * line using qemu fw_cfg interface.
+ */
+static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
+{
+	char *data_addr;
+	uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
+
+	qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
+	qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
+
+	if (setup_size == 0 || kernel_size == 0) {
+		printf("warning: no kernel available\n");
+		return -1;
+	}
+
+	data_addr = load_addr;
+	qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
+			      le32_to_cpu(setup_size), data_addr);
+	data_addr += le32_to_cpu(setup_size);
+
+	qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
+			      le32_to_cpu(kernel_size), data_addr);
+	data_addr += le32_to_cpu(kernel_size);
+
+	data_addr = initrd_addr;
+	qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
+	if (initrd_size == 0) {
+		printf("warning: no initrd available\n");
+	} else {
+		qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
+				      le32_to_cpu(initrd_size), data_addr);
+		data_addr += le32_to_cpu(initrd_size);
+	}
+
+	qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
+	if (cmdline_size) {
+		qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
+				      le32_to_cpu(cmdline_size), data_addr);
+		/*
+		 * if kernel cmdline only contains '\0', (e.g. no -append
+		 * when invoking qemu), do not update bootargs
+		 */
+		if (*data_addr != '\0') {
+			if (setenv("bootargs", data_addr) < 0)
+				printf("warning: unable to change bootargs\n");
+		}
+	}
+
+	printf("loading kernel to address %p size %x", load_addr,
+	       le32_to_cpu(kernel_size));
+	if (initrd_size)
+		printf(" initrd %p size %x\n",
+		       initrd_addr,
+		       le32_to_cpu(initrd_size));
+	else
+		printf("\n");
+
+	return 0;
+}
+
+static int qemu_fwcfg_list_firmware(void)
+{
+	int ret;
+	struct fw_cfg_file_iter iter;
+	struct fw_file *file;
+
+	/* make sure fw_list is loaded */
+	ret = qemu_fwcfg_read_firmware_list();
+	if (ret)
+		return ret;
+
+
+	for (file = qemu_fwcfg_file_iter_init(&iter);
+	     !qemu_fwcfg_file_iter_end(&iter);
+	     file = qemu_fwcfg_file_iter_next(&iter)) {
+		printf("%-56s\n", file->cfg.name);
+	}
+
+	return 0;
+}
+
+static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	if (qemu_fwcfg_list_firmware() < 0)
+		return CMD_RET_FAILURE;
+
+	return 0;
+}
+
+static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	int ret = qemu_fwcfg_online_cpus();
+	if (ret < 0) {
+		printf("QEMU fw_cfg interface not found\n");
+		return CMD_RET_FAILURE;
+	}
+
+	printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
+
+	return 0;
+}
+
+static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	char *env;
+	void *load_addr;
+	void *initrd_addr;
+
+	env = getenv("loadaddr");
+	load_addr = env ?
+		(void *)simple_strtoul(env, NULL, 16) :
+#ifdef CONFIG_LOADADDR
+		(void *)CONFIG_LOADADDR;
+#else
+		NULL;
+#endif
+
+	env = getenv("ramdiskaddr");
+	initrd_addr = env ?
+		(void *)simple_strtoul(env, NULL, 16) :
+#ifdef CONFIG_RAMDISK_ADDR
+		(void *)CONFIG_RAMDISK_ADDR;
+#else
+		NULL;
+#endif
+
+	if (argc == 2) {
+		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+		initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
+	} else if (argc == 1) {
+		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+	}
+
+	if (!load_addr || !initrd_addr) {
+		printf("missing load or initrd address\n");
+		return CMD_RET_FAILURE;
+	}
+
+	return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
+}
+
+static cmd_tbl_t fwcfg_commands[] = {
+	U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
+	U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
+	U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
+};
+
+static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int ret;
+	cmd_tbl_t *fwcfg_cmd;
+
+	if (!qemu_fwcfg_present()) {
+		printf("QEMU fw_cfg interface not found\n");
+		return CMD_RET_USAGE;
+	}
+
+	fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
+				 ARRAY_SIZE(fwcfg_commands));
+	argc -= 2;
+	argv += 2;
+	if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
+		return CMD_RET_USAGE;
+
+	ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
+
+	return cmd_process_error(fwcfg_cmd, ret);
+}
+
+U_BOOT_CMD(
+	qfw,	4,	1,	do_qemu_fw,
+	"QEMU firmware interface",
+	"<command>\n"
+	"    - list                             : print firmware(s) currently loaded\n"
+	"    - cpus                             : print online cpu number\n"
+	"    - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
+)
diff --git a/cmd/sata.c b/cmd/sata.c
index 8748cce..d18b523 100644
--- a/cmd/sata.c
+++ b/cmd/sata.c
@@ -16,70 +16,6 @@
 #include <sata.h>
 
 static int sata_curr_device = -1;
-struct blk_desc sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
-static unsigned long sata_bread(struct blk_desc *block_dev, lbaint_t start,
-				lbaint_t blkcnt, void *dst)
-{
-	return sata_read(block_dev->devnum, start, blkcnt, dst);
-}
-
-static unsigned long sata_bwrite(struct blk_desc *block_dev, lbaint_t start,
-				 lbaint_t blkcnt, const void *buffer)
-{
-	return sata_write(block_dev->devnum, start, blkcnt, buffer);
-}
-
-int __sata_initialize(void)
-{
-	int rc;
-	int i;
-
-	for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) {
-		memset(&sata_dev_desc[i], 0, sizeof(struct blk_desc));
-		sata_dev_desc[i].if_type = IF_TYPE_SATA;
-		sata_dev_desc[i].devnum = i;
-		sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
-		sata_dev_desc[i].type = DEV_TYPE_HARDDISK;
-		sata_dev_desc[i].lba = 0;
-		sata_dev_desc[i].blksz = 512;
-		sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz);
-		sata_dev_desc[i].block_read = sata_bread;
-		sata_dev_desc[i].block_write = sata_bwrite;
-
-		rc = init_sata(i);
-		if (!rc) {
-			rc = scan_sata(i);
-			if (!rc && (sata_dev_desc[i].lba > 0) &&
-				(sata_dev_desc[i].blksz > 0))
-				part_init(&sata_dev_desc[i]);
-		}
-	}
-	sata_curr_device = 0;
-	return rc;
-}
-int sata_initialize(void) __attribute__((weak,alias("__sata_initialize")));
-
-__weak int __sata_stop(void)
-{
-	int i, err = 0;
-
-	for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++)
-		err |= reset_sata(i);
-
-	if (err)
-		printf("Could not reset some SATA devices\n");
-
-	return err;
-}
-int sata_stop(void) __attribute__((weak, alias("__sata_stop")));
-
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *sata_get_dev(int dev)
-{
-	return (dev < CONFIG_SYS_SATA_MAX_DEVICE) ? &sata_dev_desc[dev] : NULL;
-}
-#endif
 
 static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -105,69 +41,40 @@
 	case 1:
 		return CMD_RET_USAGE;
 	case 2:
-		if (strncmp(argv[1],"inf", 3) == 0) {
-			int i;
-			putc('\n');
-			for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; ++i) {
-				if (sata_dev_desc[i].type == DEV_TYPE_UNKNOWN)
-					continue;
-				printf ("SATA device %d: ", i);
-				dev_print(&sata_dev_desc[i]);
+		if (strncmp(argv[1], "inf", 3) == 0) {
+			blk_list_devices(IF_TYPE_SATA);
+			return 0;
+		} else if (strncmp(argv[1], "dev", 3) == 0) {
+			if (blk_print_device_num(IF_TYPE_SATA,
+						 sata_curr_device)) {
+				printf("\nno SATA devices available\n");
+				return CMD_RET_FAILURE;
 			}
 			return 0;
-		} else if (strncmp(argv[1],"dev", 3) == 0) {
-			if ((sata_curr_device < 0) || (sata_curr_device >= CONFIG_SYS_SATA_MAX_DEVICE)) {
+		} else if (strncmp(argv[1], "part", 4) == 0) {
+			if (blk_list_part(IF_TYPE_SATA))
 				puts("\nno SATA devices available\n");
-				return 1;
-			}
-			printf("\nSATA device %d: ", sata_curr_device);
-			dev_print(&sata_dev_desc[sata_curr_device]);
 			return 0;
-		} else if (strncmp(argv[1],"part",4) == 0) {
-			int dev, ok;
-
-			for (ok = 0, dev = 0; dev < CONFIG_SYS_SATA_MAX_DEVICE; ++dev) {
-				if (sata_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
-					++ok;
-					if (dev)
-						putc ('\n');
-					part_print(&sata_dev_desc[dev]);
-				}
-			}
-			if (!ok) {
-				puts("\nno SATA devices available\n");
-				rc ++;
-			}
-			return rc;
 		}
 		return CMD_RET_USAGE;
 	case 3:
 		if (strncmp(argv[1], "dev", 3) == 0) {
 			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 
-			printf("\nSATA device %d: ", dev);
-			if (dev >= CONFIG_SYS_SATA_MAX_DEVICE) {
-				puts ("unknown device\n");
-				return 1;
+			if (!blk_show_device(IF_TYPE_SATA, dev)) {
+				sata_curr_device = dev;
+				printf("... is now current device\n");
+			} else {
+				return CMD_RET_FAILURE;
 			}
-			dev_print(&sata_dev_desc[dev]);
-
-			if (sata_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
-				return 1;
-
-			sata_curr_device = dev;
-
-			puts("... is now current device\n");
-
 			return 0;
 		} else if (strncmp(argv[1], "part", 4) == 0) {
 			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 
-			if (sata_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
-				part_print(&sata_dev_desc[dev]);
-			} else {
-				printf("\nSATA device %d not available\n", dev);
-				rc = 1;
+			if (blk_print_part_devnum(IF_TYPE_SATA, dev)) {
+				printf("\nSATA device %d not available\n",
+				       dev);
+				return CMD_RET_FAILURE;
 			}
 			return rc;
 		}
@@ -183,11 +90,8 @@
 			printf("\nSATA read: device %d block # %ld, count %ld ... ",
 				sata_curr_device, blk, cnt);
 
-			n = blk_dread(&sata_dev_desc[sata_curr_device],
-				      blk, cnt, (u32 *)addr);
-
-			/* flush cache after read */
-			flush_cache(addr, cnt * sata_dev_desc[sata_curr_device].blksz);
+			n = blk_read_devnum(IF_TYPE_SATA, sata_curr_device, blk,
+					    cnt, (ulong *)addr);
 
 			printf("%ld blocks read: %s\n",
 				n, (n==cnt) ? "OK" : "ERROR");
@@ -202,8 +106,8 @@
 			printf("\nSATA write: device %d block # %ld, count %ld ... ",
 				sata_curr_device, blk, cnt);
 
-			n = blk_dwrite(&sata_dev_desc[sata_curr_device],
-				       blk, cnt, (u32 *)addr);
+			n = blk_write_devnum(IF_TYPE_SATA, sata_curr_device,
+					     blk, cnt, (ulong *)addr);
 
 			printf("%ld blocks written: %s\n",
 				n, (n == cnt) ? "OK" : "ERROR");
diff --git a/cmd/scsi.c b/cmd/scsi.c
index 8991125..387ca1a 100644
--- a/cmd/scsi.c
+++ b/cmd/scsi.c
@@ -10,361 +10,108 @@
  */
 #include <common.h>
 #include <command.h>
-#include <inttypes.h>
-#include <asm/processor.h>
 #include <scsi.h>
-#include <image.h>
-#include <pci.h>
-
-#ifdef CONFIG_SCSI_DEV_LIST
-#define SCSI_DEV_LIST CONFIG_SCSI_DEV_LIST
-#else
-#ifdef CONFIG_SCSI_SYM53C8XX
-#define SCSI_VEND_ID	0x1000
-#ifndef CONFIG_SCSI_DEV_ID
-#define SCSI_DEV_ID		0x0001
-#else
-#define SCSI_DEV_ID		CONFIG_SCSI_DEV_ID
-#endif
-#elif defined CONFIG_SATA_ULI5288
-
-#define SCSI_VEND_ID 0x10b9
-#define SCSI_DEV_ID  0x5288
-
-#elif !defined(CONFIG_SCSI_AHCI_PLAT)
-#error no scsi device defined
-#endif
-#define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
-#endif
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
-const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST };
-#endif
-static ccb tempccb;	/* temporary scsi command buffer */
-
-static unsigned char tempbuff[512]; /* temporary data buffer */
-
-static int scsi_max_devs; /* number of highest available scsi device */
 
 static int scsi_curr_dev; /* current device */
 
-static struct blk_desc scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
-
-/********************************************************************************
- *  forward declerations of some Setup Routines
- */
-void scsi_setup_test_unit_ready(ccb * pccb);
-void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks);
-void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks);
-void scsi_setup_read16(ccb * pccb, lbaint_t start, unsigned long blocks);
-
-static void scsi_setup_write_ext(ccb *pccb, lbaint_t start,
-				unsigned short blocks);
-void scsi_setup_inquiry(ccb * pccb);
-void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
-
-
-static int scsi_read_capacity(ccb *pccb, lbaint_t *capacity,
-			      unsigned long *blksz);
-static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
-		       lbaint_t blkcnt, void *buffer);
-static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr,
-			lbaint_t blkcnt, const void *buffer);
-
-
-/*********************************************************************************
- * (re)-scan the scsi bus and reports scsi device info
- * to the user if mode = 1
- */
-void scsi_scan(int mode)
-{
-	unsigned char i,perq,modi,lun;
-	lbaint_t capacity;
-	unsigned long blksz;
-	ccb* pccb=(ccb *)&tempccb;
-
-	if(mode==1) {
-		printf("scanning bus for devices...\n");
-	}
-	for(i=0;i<CONFIG_SYS_SCSI_MAX_DEVICE;i++) {
-		scsi_dev_desc[i].target=0xff;
-		scsi_dev_desc[i].lun=0xff;
-		scsi_dev_desc[i].lba=0;
-		scsi_dev_desc[i].blksz=0;
-		scsi_dev_desc[i].log2blksz =
-			LOG2_INVALID(typeof(scsi_dev_desc[i].log2blksz));
-		scsi_dev_desc[i].type=DEV_TYPE_UNKNOWN;
-		scsi_dev_desc[i].vendor[0]=0;
-		scsi_dev_desc[i].product[0]=0;
-		scsi_dev_desc[i].revision[0]=0;
-		scsi_dev_desc[i].removable = false;
-		scsi_dev_desc[i].if_type=IF_TYPE_SCSI;
-		scsi_dev_desc[i].devnum = i;
-		scsi_dev_desc[i].part_type=PART_TYPE_UNKNOWN;
-		scsi_dev_desc[i].block_read=scsi_read;
-		scsi_dev_desc[i].block_write = scsi_write;
-	}
-	scsi_max_devs=0;
-	for(i=0;i<CONFIG_SYS_SCSI_MAX_SCSI_ID;i++) {
-		pccb->target=i;
-		for(lun=0;lun<CONFIG_SYS_SCSI_MAX_LUN;lun++) {
-			pccb->lun=lun;
-			pccb->pdata=(unsigned char *)&tempbuff;
-			pccb->datalen=512;
-			scsi_setup_inquiry(pccb);
-			if (scsi_exec(pccb) != true) {
-				if(pccb->contr_stat==SCSI_SEL_TIME_OUT) {
-					debug ("Selection timeout ID %d\n",pccb->target);
-					continue; /* selection timeout => assuming no device present */
-				}
-				scsi_print_error(pccb);
-				continue;
-			}
-			perq=tempbuff[0];
-			modi=tempbuff[1];
-			if((perq & 0x1f)==0x1f) {
-				continue; /* skip unknown devices */
-			}
-			if((modi&0x80)==0x80) /* drive is removable */
-				scsi_dev_desc[scsi_max_devs].removable=true;
-			/* get info for this device */
-			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].vendor[0],
-				       &tempbuff[8], 8);
-			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].product[0],
-				       &tempbuff[16], 16);
-			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].revision[0],
-				       &tempbuff[32], 4);
-			scsi_dev_desc[scsi_max_devs].target=pccb->target;
-			scsi_dev_desc[scsi_max_devs].lun=pccb->lun;
-
-			pccb->datalen=0;
-			scsi_setup_test_unit_ready(pccb);
-			if (scsi_exec(pccb) != true) {
-				if (scsi_dev_desc[scsi_max_devs].removable == true) {
-					scsi_dev_desc[scsi_max_devs].type=perq;
-					goto removable;
-				}
-				scsi_print_error(pccb);
-				continue;
-			}
-			if (scsi_read_capacity(pccb, &capacity, &blksz)) {
-				scsi_print_error(pccb);
-				continue;
-			}
-			scsi_dev_desc[scsi_max_devs].lba=capacity;
-			scsi_dev_desc[scsi_max_devs].blksz=blksz;
-			scsi_dev_desc[scsi_max_devs].log2blksz =
-				LOG2(scsi_dev_desc[scsi_max_devs].blksz);
-			scsi_dev_desc[scsi_max_devs].type=perq;
-			part_init(&scsi_dev_desc[scsi_max_devs]);
-removable:
-			if(mode==1) {
-				printf ("  Device %d: ", scsi_max_devs);
-				dev_print(&scsi_dev_desc[scsi_max_devs]);
-			} /* if mode */
-			scsi_max_devs++;
-		} /* next LUN */
-	}
-	if(scsi_max_devs>0)
-		scsi_curr_dev=0;
-	else
-		scsi_curr_dev = -1;
-
-	printf("Found %d device(s).\n", scsi_max_devs);
-#ifndef CONFIG_SPL_BUILD
-	setenv_ulong("scsidevs", scsi_max_devs);
-#endif
-}
-
-int scsi_get_disk_count(void)
-{
-	return scsi_max_devs;
-}
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
-void scsi_init(void)
-{
-	int busdevfunc = -1;
-	int i;
-	/*
-	 * Find a device from the list, this driver will support a single
-	 * controller.
-	 */
-	for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
-		/* get PCI Device ID */
-#ifdef CONFIG_DM_PCI
-		struct udevice *dev;
-		int ret;
-
-		ret = dm_pci_find_device(scsi_device_list[i].vendor,
-					 scsi_device_list[i].device, 0, &dev);
-		if (!ret) {
-			busdevfunc = dm_pci_get_bdf(dev);
-			break;
-		}
-#else
-		busdevfunc = pci_find_device(scsi_device_list[i].vendor,
-					     scsi_device_list[i].device,
-					     0);
-#endif
-		if (busdevfunc != -1)
-			break;
-	}
-
-	if (busdevfunc == -1) {
-		printf("Error: SCSI Controller(s) ");
-		for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
-			printf("%04X:%04X ",
-			       scsi_device_list[i].vendor,
-			       scsi_device_list[i].device);
-		}
-		printf("not found\n");
-		return;
-	}
-#ifdef DEBUG
-	else {
-		printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n",
-		       scsi_device_list[i].vendor,
-		       scsi_device_list[i].device,
-		       (busdevfunc >> 16) & 0xFF,
-		       (busdevfunc >> 11) & 0x1F,
-		       (busdevfunc >> 8) & 0x7);
-	}
-#endif
-	bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
-	scsi_low_level_init(busdevfunc);
-	scsi_scan(1);
-	bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);
-}
-#endif
-
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *scsi_get_dev(int dev)
-{
-	return (dev < CONFIG_SYS_SCSI_MAX_DEVICE) ? &scsi_dev_desc[dev] : NULL;
-}
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-/******************************************************************************
+/*
  * scsi boot command intepreter. Derived from diskboot
  */
-int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_scsiboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
 	return common_diskboot(cmdtp, "scsi", argc, argv);
 }
 
-/*********************************************************************************
+/*
  * scsi command intepreter
  */
-int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_scsi(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
 	switch (argc) {
 	case 0:
 	case 1:
 		return CMD_RET_USAGE;
-
 	case 2:
-			if (strncmp(argv[1],"res",3) == 0) {
-				printf("\nReset SCSI\n");
-				scsi_bus_reset();
-				scsi_scan(1);
-				return 0;
+		if (strncmp(argv[1], "res", 3) == 0) {
+			printf("\nReset SCSI\n");
+			scsi_bus_reset();
+			scsi_scan(1);
+			return 0;
+		}
+		if (strncmp(argv[1], "inf", 3) == 0) {
+			blk_list_devices(IF_TYPE_SCSI);
+			return 0;
+		}
+		if (strncmp(argv[1], "dev", 3) == 0) {
+			if (blk_print_device_num(IF_TYPE_SCSI, scsi_curr_dev)) {
+				printf("\nno SCSI devices available\n");
+				return CMD_RET_FAILURE;
 			}
-			if (strncmp(argv[1],"inf",3) == 0) {
-				int i;
-				for (i=0; i<CONFIG_SYS_SCSI_MAX_DEVICE; ++i) {
-					if(scsi_dev_desc[i].type==DEV_TYPE_UNKNOWN)
-						continue; /* list only known devices */
-					printf ("SCSI dev. %d:  ", i);
-					dev_print(&scsi_dev_desc[i]);
-				}
-				return 0;
-			}
-			if (strncmp(argv[1],"dev",3) == 0) {
-				if ((scsi_curr_dev < 0) || (scsi_curr_dev >= CONFIG_SYS_SCSI_MAX_DEVICE)) {
-					printf("\nno SCSI devices available\n");
-					return 1;
-				}
-				printf ("\n    Device %d: ", scsi_curr_dev);
-				dev_print(&scsi_dev_desc[scsi_curr_dev]);
-				return 0;
-			}
-			if (strncmp(argv[1],"scan",4) == 0) {
-				scsi_scan(1);
-				return 0;
-			}
-			if (strncmp(argv[1],"part",4) == 0) {
-				int dev, ok;
-				for (ok=0, dev=0; dev<CONFIG_SYS_SCSI_MAX_DEVICE; ++dev) {
-					if (scsi_dev_desc[dev].type!=DEV_TYPE_UNKNOWN) {
-						ok++;
-						if (dev)
-							printf("\n");
-						debug ("print_part of %x\n",dev);
-						part_print(&scsi_dev_desc[dev]);
-					}
-				}
-				if (!ok)
-					printf("\nno SCSI devices available\n");
-				return 1;
-			}
-			return CMD_RET_USAGE;
+
+			return 0;
+		}
+		if (strncmp(argv[1], "scan", 4) == 0) {
+			scsi_scan(1);
+			return 0;
+		}
+		if (strncmp(argv[1], "part", 4) == 0) {
+			if (blk_list_part(IF_TYPE_SCSI))
+				printf("\nno SCSI devices available\n");
+			return 0;
+		}
+		return CMD_RET_USAGE;
 	case 3:
-			if (strncmp(argv[1],"dev",3) == 0) {
-				int dev = (int)simple_strtoul(argv[2], NULL, 10);
-				printf ("\nSCSI device %d: ", dev);
-				if (dev >= CONFIG_SYS_SCSI_MAX_DEVICE) {
-					printf("unknown device\n");
-					return 1;
-				}
-				printf ("\n    Device %d: ", dev);
-				dev_print(&scsi_dev_desc[dev]);
-				if(scsi_dev_desc[dev].type == DEV_TYPE_UNKNOWN) {
-					return 1;
-				}
+		if (strncmp(argv[1], "dev", 3) == 0) {
+			int dev = (int)simple_strtoul(argv[2], NULL, 10);
+
+			if (!blk_show_device(IF_TYPE_SCSI, dev)) {
 				scsi_curr_dev = dev;
 				printf("... is now current device\n");
-				return 0;
+			} else {
+				return CMD_RET_FAILURE;
 			}
-			if (strncmp(argv[1],"part",4) == 0) {
-				int dev = (int)simple_strtoul(argv[2], NULL, 10);
-				if(scsi_dev_desc[dev].type != DEV_TYPE_UNKNOWN) {
-					part_print(&scsi_dev_desc[dev]);
-				}
-				else {
-					printf ("\nSCSI device %d not available\n", dev);
-				}
-				return 1;
+			return 0;
+		}
+		if (strncmp(argv[1], "part", 4) == 0) {
+			int dev = (int)simple_strtoul(argv[2], NULL, 10);
+
+			if (blk_print_part_devnum(IF_TYPE_SCSI, dev)) {
+				printf("\nSCSI device %d not available\n",
+				       dev);
+				return CMD_RET_FAILURE;
 			}
-			return CMD_RET_USAGE;
-    default:
-			/* at least 4 args */
-			if (strcmp(argv[1],"read") == 0) {
-				ulong addr = simple_strtoul(argv[2], NULL, 16);
-				ulong blk  = simple_strtoul(argv[3], NULL, 16);
-				ulong cnt  = simple_strtoul(argv[4], NULL, 16);
-				ulong n;
-				printf ("\nSCSI read: device %d block # %ld, count %ld ... ",
-						scsi_curr_dev, blk, cnt);
-				n = scsi_read(&scsi_dev_desc[scsi_curr_dev],
-					      blk, cnt, (ulong *)addr);
-				printf ("%ld blocks read: %s\n",n,(n==cnt) ? "OK" : "ERROR");
-				return 0;
-			} else if (strcmp(argv[1], "write") == 0) {
-				ulong addr = simple_strtoul(argv[2], NULL, 16);
-				ulong blk = simple_strtoul(argv[3], NULL, 16);
-				ulong cnt = simple_strtoul(argv[4], NULL, 16);
-				ulong n;
-				printf("\nSCSI write: device %d block # %ld, "
-				       "count %ld ... ",
-				       scsi_curr_dev, blk, cnt);
-				n = scsi_write(&scsi_dev_desc[scsi_curr_dev],
-					       blk, cnt, (ulong *)addr);
-				printf("%ld blocks written: %s\n", n,
-				       (n == cnt) ? "OK" : "ERROR");
-				return 0;
-			}
+			return 0;
+		}
+		return CMD_RET_USAGE;
+	default:
+		/* at least 4 args */
+		if (strcmp(argv[1], "read") == 0) {
+			ulong addr = simple_strtoul(argv[2], NULL, 16);
+			ulong blk  = simple_strtoul(argv[3], NULL, 16);
+			ulong cnt  = simple_strtoul(argv[4], NULL, 16);
+			ulong n;
+
+			printf("\nSCSI read: device %d block # %ld, count %ld ... ",
+			       scsi_curr_dev, blk, cnt);
+			n = blk_read_devnum(IF_TYPE_SCSI, scsi_curr_dev, blk,
+					    cnt, (ulong *)addr);
+			printf("%ld blocks read: %s\n", n,
+			       n == cnt ? "OK" : "ERROR");
+			return 0;
+		} else if (strcmp(argv[1], "write") == 0) {
+			ulong addr = simple_strtoul(argv[2], NULL, 16);
+			ulong blk = simple_strtoul(argv[3], NULL, 16);
+			ulong cnt = simple_strtoul(argv[4], NULL, 16);
+			ulong n;
+
+			printf("\nSCSI write: device %d block # %ld, count %ld ... ",
+			       scsi_curr_dev, blk, cnt);
+			n = blk_write_devnum(IF_TYPE_SCSI, scsi_curr_dev, blk,
+					     cnt, (ulong *)addr);
+			printf("%ld blocks written: %s\n", n,
+			       n == cnt ? "OK" : "ERROR");
+			return 0;
+		}
 	} /* switch */
 	return CMD_RET_USAGE;
 }
@@ -388,347 +135,3 @@
 	"boot from SCSI device",
 	"loadAddr dev:part"
 );
-#endif
-
-/****************************************************************************************
- * scsi_read
- */
-
-/* almost the maximum amount of the scsi_ext command.. */
-#define SCSI_MAX_READ_BLK 0xFFFF
-#define SCSI_LBA48_READ	0xFFFFFFF
-
-static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
-		       lbaint_t blkcnt, void *buffer)
-{
-	int device = block_dev->devnum;
-	lbaint_t start, blks;
-	uintptr_t buf_addr;
-	unsigned short smallblks = 0;
-	ccb* pccb=(ccb *)&tempccb;
-	device&=0xff;
-	/* Setup  device
-	 */
-	pccb->target=scsi_dev_desc[device].target;
-	pccb->lun=scsi_dev_desc[device].lun;
-	buf_addr=(unsigned long)buffer;
-	start=blknr;
-	blks=blkcnt;
-	debug("\nscsi_read: dev %d startblk " LBAF
-	      ", blccnt " LBAF " buffer %lx\n",
-	      device, start, blks, (unsigned long)buffer);
-	do {
-		pccb->pdata=(unsigned char *)buf_addr;
-#ifdef CONFIG_SYS_64BIT_LBA
-		if (start > SCSI_LBA48_READ) {
-			unsigned long blocks;
-			blocks = min_t(lbaint_t, blks, SCSI_MAX_READ_BLK);
-			pccb->datalen = scsi_dev_desc[device].blksz * blocks;
-			scsi_setup_read16(pccb, start, blocks);
-			start += blocks;
-			blks -= blocks;
-		} else
-#endif
-		if (blks > SCSI_MAX_READ_BLK) {
-			pccb->datalen=scsi_dev_desc[device].blksz * SCSI_MAX_READ_BLK;
-			smallblks=SCSI_MAX_READ_BLK;
-			scsi_setup_read_ext(pccb,start,smallblks);
-			start+=SCSI_MAX_READ_BLK;
-			blks-=SCSI_MAX_READ_BLK;
-		}
-		else {
-			pccb->datalen=scsi_dev_desc[device].blksz * blks;
-			smallblks=(unsigned short) blks;
-			scsi_setup_read_ext(pccb,start,smallblks);
-			start+=blks;
-			blks=0;
-		}
-		debug("scsi_read_ext: startblk " LBAF
-		      ", blccnt %x buffer %" PRIXPTR "\n",
-		      start, smallblks, buf_addr);
-		if (scsi_exec(pccb) != true) {
-			scsi_print_error(pccb);
-			blkcnt-=blks;
-			break;
-		}
-		buf_addr+=pccb->datalen;
-	} while(blks!=0);
-	debug("scsi_read_ext: end startblk " LBAF
-	      ", blccnt %x buffer %" PRIXPTR "\n", start, smallblks, buf_addr);
-	return(blkcnt);
-}
-
-/*******************************************************************************
- * scsi_write
- */
-
-/* Almost the maximum amount of the scsi_ext command.. */
-#define SCSI_MAX_WRITE_BLK 0xFFFF
-
-static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr,
-			lbaint_t blkcnt, const void *buffer)
-{
-	int device = block_dev->devnum;
-	lbaint_t start, blks;
-	uintptr_t buf_addr;
-	unsigned short smallblks;
-	ccb* pccb = (ccb *)&tempccb;
-	device &= 0xff;
-	/* Setup  device
-	 */
-	pccb->target = scsi_dev_desc[device].target;
-	pccb->lun = scsi_dev_desc[device].lun;
-	buf_addr = (unsigned long)buffer;
-	start = blknr;
-	blks = blkcnt;
-	debug("\n%s: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n",
-	      __func__, device, start, blks, (unsigned long)buffer);
-	do {
-		pccb->pdata = (unsigned char *)buf_addr;
-		if (blks > SCSI_MAX_WRITE_BLK) {
-			pccb->datalen = (scsi_dev_desc[device].blksz *
-					 SCSI_MAX_WRITE_BLK);
-			smallblks = SCSI_MAX_WRITE_BLK;
-			scsi_setup_write_ext(pccb, start, smallblks);
-			start += SCSI_MAX_WRITE_BLK;
-			blks -= SCSI_MAX_WRITE_BLK;
-		} else {
-			pccb->datalen = scsi_dev_desc[device].blksz * blks;
-			smallblks = (unsigned short)blks;
-			scsi_setup_write_ext(pccb, start, smallblks);
-			start += blks;
-			blks = 0;
-		}
-		debug("%s: startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
-		      __func__, start, smallblks, buf_addr);
-		if (scsi_exec(pccb) != true) {
-			scsi_print_error(pccb);
-			blkcnt -= blks;
-			break;
-		}
-		buf_addr += pccb->datalen;
-	} while (blks != 0);
-	debug("%s: end startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
-	      __func__, start, smallblks, buf_addr);
-	return blkcnt;
-}
-
-/* copy src to dest, skipping leading and trailing blanks
- * and null terminate the string
- */
-void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len)
-{
-	int start,end;
-
-	start=0;
-	while(start<len) {
-		if(src[start]!=' ')
-			break;
-		start++;
-	}
-	end=len-1;
-	while(end>start) {
-		if(src[end]!=' ')
-			break;
-		end--;
-	}
-	for( ; start<=end; start++) {
-		*dest++=src[start];
-	}
-	*dest='\0';
-}
-
-
-/* Trim trailing blanks, and NUL-terminate string
- */
-void scsi_trim_trail (unsigned char *str, unsigned int len)
-{
-	unsigned char *p = str + len - 1;
-
-	while (len-- > 0) {
-		*p-- = '\0';
-		if (*p != ' ') {
-			return;
-		}
-	}
-}
-
-int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz)
-{
-	*capacity = 0;
-
-	memset(pccb->cmd, 0, sizeof(pccb->cmd));
-	pccb->cmd[0] = SCSI_RD_CAPAC10;
-	pccb->cmd[1] = pccb->lun << 5;
-	pccb->cmdlen = 10;
-	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
-
-	pccb->datalen = 8;
-	if (scsi_exec(pccb) != true)
-		return 1;
-
-	*capacity = ((lbaint_t)pccb->pdata[0] << 24) |
-		    ((lbaint_t)pccb->pdata[1] << 16) |
-		    ((lbaint_t)pccb->pdata[2] << 8)  |
-		    ((lbaint_t)pccb->pdata[3]);
-
-	if (*capacity != 0xffffffff) {
-		/* Read capacity (10) was sufficient for this drive. */
-		*blksz = ((unsigned long)pccb->pdata[4] << 24) |
-			 ((unsigned long)pccb->pdata[5] << 16) |
-			 ((unsigned long)pccb->pdata[6] << 8)  |
-			 ((unsigned long)pccb->pdata[7]);
-		return 0;
-	}
-
-	/* Read capacity (10) was insufficient. Use read capacity (16). */
-
-	memset(pccb->cmd, 0, sizeof(pccb->cmd));
-	pccb->cmd[0] = SCSI_RD_CAPAC16;
-	pccb->cmd[1] = 0x10;
-	pccb->cmdlen = 16;
-	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
-
-	pccb->datalen = 16;
-	if (scsi_exec(pccb) != true)
-		return 1;
-
-	*capacity = ((uint64_t)pccb->pdata[0] << 56) |
-		    ((uint64_t)pccb->pdata[1] << 48) |
-		    ((uint64_t)pccb->pdata[2] << 40) |
-		    ((uint64_t)pccb->pdata[3] << 32) |
-		    ((uint64_t)pccb->pdata[4] << 24) |
-		    ((uint64_t)pccb->pdata[5] << 16) |
-		    ((uint64_t)pccb->pdata[6] << 8)  |
-		    ((uint64_t)pccb->pdata[7]);
-
-	*blksz = ((uint64_t)pccb->pdata[8]  << 56) |
-		 ((uint64_t)pccb->pdata[9]  << 48) |
-		 ((uint64_t)pccb->pdata[10] << 40) |
-		 ((uint64_t)pccb->pdata[11] << 32) |
-		 ((uint64_t)pccb->pdata[12] << 24) |
-		 ((uint64_t)pccb->pdata[13] << 16) |
-		 ((uint64_t)pccb->pdata[14] << 8)  |
-		 ((uint64_t)pccb->pdata[15]);
-
-	return 0;
-}
-
-
-/************************************************************************************
- * Some setup (fill-in) routines
- */
-void scsi_setup_test_unit_ready(ccb * pccb)
-{
-	pccb->cmd[0]=SCSI_TST_U_RDY;
-	pccb->cmd[1]=pccb->lun<<5;
-	pccb->cmd[2]=0;
-	pccb->cmd[3]=0;
-	pccb->cmd[4]=0;
-	pccb->cmd[5]=0;
-	pccb->cmdlen=6;
-	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
-}
-
-#ifdef CONFIG_SYS_64BIT_LBA
-void scsi_setup_read16(ccb * pccb, lbaint_t start, unsigned long blocks)
-{
-	pccb->cmd[0] = SCSI_READ16;
-	pccb->cmd[1] = pccb->lun<<5;
-	pccb->cmd[2] = ((unsigned char) (start >> 56)) & 0xff;
-	pccb->cmd[3] = ((unsigned char) (start >> 48)) & 0xff;
-	pccb->cmd[4] = ((unsigned char) (start >> 40)) & 0xff;
-	pccb->cmd[5] = ((unsigned char) (start >> 32)) & 0xff;
-	pccb->cmd[6] = ((unsigned char) (start >> 24)) & 0xff;
-	pccb->cmd[7] = ((unsigned char) (start >> 16)) & 0xff;
-	pccb->cmd[8] = ((unsigned char) (start >> 8)) & 0xff;
-	pccb->cmd[9] = ((unsigned char) (start)) & 0xff;
-	pccb->cmd[10] = 0;
-	pccb->cmd[11] = ((unsigned char) (blocks >> 24)) & 0xff;
-	pccb->cmd[12] = ((unsigned char) (blocks >> 16)) & 0xff;
-	pccb->cmd[13] = ((unsigned char) (blocks >> 8)) & 0xff;
-	pccb->cmd[14] = (unsigned char) blocks & 0xff;
-	pccb->cmd[15] = 0;
-	pccb->cmdlen = 16;
-	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
-	debug ("scsi_setup_read16: cmd: %02X %02X "
-	       "startblk %02X%02X%02X%02X%02X%02X%02X%02X "
-	       "blccnt %02X%02X%02X%02X\n",
-		pccb->cmd[0], pccb->cmd[1],
-		pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
-		pccb->cmd[6], pccb->cmd[7], pccb->cmd[8], pccb->cmd[9],
-		pccb->cmd[11], pccb->cmd[12], pccb->cmd[13], pccb->cmd[14]);
-}
-#endif
-
-void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks)
-{
-	pccb->cmd[0]=SCSI_READ10;
-	pccb->cmd[1]=pccb->lun<<5;
-	pccb->cmd[2]=((unsigned char) (start>>24))&0xff;
-	pccb->cmd[3]=((unsigned char) (start>>16))&0xff;
-	pccb->cmd[4]=((unsigned char) (start>>8))&0xff;
-	pccb->cmd[5]=((unsigned char) (start))&0xff;
-	pccb->cmd[6]=0;
-	pccb->cmd[7]=((unsigned char) (blocks>>8))&0xff;
-	pccb->cmd[8]=(unsigned char) blocks & 0xff;
-	pccb->cmd[6]=0;
-	pccb->cmdlen=10;
-	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
-	debug ("scsi_setup_read_ext: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
-		pccb->cmd[0],pccb->cmd[1],
-		pccb->cmd[2],pccb->cmd[3],pccb->cmd[4],pccb->cmd[5],
-		pccb->cmd[7],pccb->cmd[8]);
-}
-
-void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
-{
-	pccb->cmd[0] = SCSI_WRITE10;
-	pccb->cmd[1] = pccb->lun << 5;
-	pccb->cmd[2] = ((unsigned char) (start>>24)) & 0xff;
-	pccb->cmd[3] = ((unsigned char) (start>>16)) & 0xff;
-	pccb->cmd[4] = ((unsigned char) (start>>8)) & 0xff;
-	pccb->cmd[5] = ((unsigned char) (start)) & 0xff;
-	pccb->cmd[6] = 0;
-	pccb->cmd[7] = ((unsigned char) (blocks>>8)) & 0xff;
-	pccb->cmd[8] = (unsigned char)blocks & 0xff;
-	pccb->cmd[9] = 0;
-	pccb->cmdlen = 10;
-	pccb->msgout[0] = SCSI_IDENTIFY;  /* NOT USED */
-	debug("%s: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
-	      __func__,
-	      pccb->cmd[0], pccb->cmd[1],
-	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
-	      pccb->cmd[7], pccb->cmd[8]);
-}
-
-void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks)
-{
-	pccb->cmd[0]=SCSI_READ6;
-	pccb->cmd[1]=pccb->lun<<5 | (((unsigned char)(start>>16))&0x1f);
-	pccb->cmd[2]=((unsigned char) (start>>8))&0xff;
-	pccb->cmd[3]=((unsigned char) (start))&0xff;
-	pccb->cmd[4]=(unsigned char) blocks & 0xff;
-	pccb->cmd[5]=0;
-	pccb->cmdlen=6;
-	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
-	debug ("scsi_setup_read6: cmd: %02X %02X startblk %02X%02X blccnt %02X\n",
-		pccb->cmd[0],pccb->cmd[1],
-		pccb->cmd[2],pccb->cmd[3],pccb->cmd[4]);
-}
-
-
-void scsi_setup_inquiry(ccb * pccb)
-{
-	pccb->cmd[0]=SCSI_INQUIRY;
-	pccb->cmd[1]=pccb->lun<<5;
-	pccb->cmd[2]=0;
-	pccb->cmd[3]=0;
-	if(pccb->datalen>255)
-		pccb->cmd[4]=255;
-	else
-		pccb->cmd[4]=(unsigned char)pccb->datalen;
-	pccb->cmd[5]=0;
-	pccb->cmdlen=6;
-	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
-}
diff --git a/cmd/usb.c b/cmd/usb.c
index f1a7deb..b83d323 100644
--- a/cmd/usb.c
+++ b/cmd/usb.c
@@ -723,7 +723,8 @@
 		int devno, ok = 0;
 		if (argc == 2) {
 			for (devno = 0; ; ++devno) {
-				stor_dev = usb_stor_get_dev(devno);
+				stor_dev = blk_get_devnum_by_type(IF_TYPE_USB,
+								  devno);
 				if (stor_dev == NULL)
 					break;
 				if (stor_dev->type != DEV_TYPE_UNKNOWN) {
@@ -736,7 +737,7 @@
 			}
 		} else {
 			devno = simple_strtoul(argv[2], NULL, 16);
-			stor_dev = usb_stor_get_dev(devno);
+			stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, devno);
 			if (stor_dev != NULL &&
 			    stor_dev->type != DEV_TYPE_UNKNOWN) {
 				ok++;
@@ -762,7 +763,8 @@
 			unsigned long n;
 			printf("\nUSB read: device %d block # %ld, count %ld"
 				" ... ", usb_stor_curr_dev, blk, cnt);
-			stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+			stor_dev = blk_get_devnum_by_type(IF_TYPE_USB,
+							  usb_stor_curr_dev);
 			n = blk_dread(stor_dev, blk, cnt, (ulong *)addr);
 			printf("%ld blocks read: %s\n", n,
 				(n == cnt) ? "OK" : "ERROR");
@@ -783,7 +785,8 @@
 			unsigned long n;
 			printf("\nUSB write: device %d block # %ld, count %ld"
 				" ... ", usb_stor_curr_dev, blk, cnt);
-			stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+			stor_dev = blk_get_devnum_by_type(IF_TYPE_USB,
+							  usb_stor_curr_dev);
 			n = blk_dwrite(stor_dev, blk, cnt, (ulong *)addr);
 			printf("%ld blocks write: %s\n", n,
 				(n == cnt) ? "OK" : "ERROR");
@@ -796,7 +799,7 @@
 		if (argc == 3) {
 			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 			printf("\nUSB device %d: ", dev);
-			stor_dev = usb_stor_get_dev(dev);
+			stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, dev);
 			if (stor_dev == NULL) {
 				printf("unknown device\n");
 				return 1;
@@ -810,7 +813,8 @@
 			return 0;
 		} else {
 			printf("\nUSB device %d: ", usb_stor_curr_dev);
-			stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+			stor_dev = blk_get_devnum_by_type(IF_TYPE_USB,
+							  usb_stor_curr_dev);
 			dev_print(stor_dev);
 			if (stor_dev->type == DEV_TYPE_UNKNOWN)
 				return 1;
diff --git a/common/Makefile b/common/Makefile
index b23f312..0562d5c 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -84,6 +84,8 @@
 obj-$(CONFIG_LCD_DT_SIMPLEFB) += lcd_simplefb.o
 obj-$(CONFIG_LYNXKDI) += lynxkdi.o
 obj-$(CONFIG_MENU) += menu.o
+obj-$(CONFIG_CMD_SATA) += sata.o
+obj-$(CONFIG_SCSI) += scsi.o
 obj-$(CONFIG_UPDATE_TFTP) += update.o
 obj-$(CONFIG_DFU_TFTP) += update.o
 obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
@@ -112,6 +114,9 @@
 obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
 obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
 endif
+ifdef CONFIG_SPL_SATA_SUPPORT
+obj-$(CONFIG_SCSI) += scsi.o
+endif
 endif
 #environment
 obj-y += env_common.o
@@ -130,6 +135,7 @@
 ifdef CONFIG_SYS_MALLOC_F_LEN
 obj-y += malloc_simple.o
 endif
+obj-$(CONFIG_CMD_IDE) += ide.o
 obj-y += image.o
 obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
 obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o
@@ -150,6 +156,9 @@
 endif
 endif
 
+ifdef CONFIG_CMD_EEPROM_LAYOUT
+obj-y += eeprom/eeprom_field.o eeprom/eeprom_layout.o
+endif
 # We always have this since drivers/ddr/fs/interactive.c needs it
 obj-$(CONFIG_CMDLINE) += cli_simple.o
 
diff --git a/common/board_r.c b/common/board_r.c
index ad02549..d959ad3 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -620,7 +620,7 @@
 }
 #endif
 
-#if defined(CONFIG_CMD_SCSI)
+#if defined(CONFIG_SCSI)
 static int initr_scsi(void)
 {
 	puts("SCSI:  ");
@@ -923,7 +923,7 @@
 	initr_ambapp_print,
 #endif
 #endif
-#ifdef CONFIG_CMD_SCSI
+#ifdef CONFIG_SCSI
 	INIT_FUNC_WATCHDOG_RESET
 	initr_scsi,
 #endif
diff --git a/common/bootm.c b/common/bootm.c
index c965326..4941414 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -246,6 +246,16 @@
 #endif
 
 #if IMAGE_ENABLE_FIT
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+	/* find bitstreams */
+	ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT,
+			    NULL, NULL);
+	if (ret) {
+		printf("FPGA image is corrupted or invalid\n");
+		return 1;
+	}
+#endif
+
 	/* find all of the loadables */
 	ret = boot_get_loadable(argc, argv, &images, IH_ARCH_DEFAULT,
 			       NULL, NULL);
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index b09f524..adc680e 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -1909,6 +1909,7 @@
   * fulfill the user's request.
   */
   if (m == NULL) {
+    size_t extra, extra2;
     /*
      * Use bytes not nb, since mALLOc internally calls request2size too, and
      * each call increases the size to allocate, to account for the header.
@@ -1917,9 +1918,27 @@
     /* Aligned -> return it */
     if ((((unsigned long)(m)) % alignment) == 0)
       return m;
-    /* Otherwise, fail */
+    /*
+     * Otherwise, try again, requesting enough extra space to be able to
+     * acquire alignment.
+     */
     fREe(m);
-    m = NULL;
+    /* Add in extra bytes to match misalignment of unexpanded allocation */
+    extra = alignment - (((unsigned long)(m)) % alignment);
+    m  = (char*)(mALLOc(bytes + extra));
+    /*
+     * m might not be the same as before. Validate that the previous value of
+     * extra still works for the current value of m.
+     * If (!m), extra2=alignment so 
+     */
+    if (m) {
+      extra2 = alignment - (((unsigned long)(m)) % alignment);
+      if (extra2 > extra) {
+        fREe(m);
+        m = NULL;
+      }
+    }
+    /* Fall through to original NULL check and chunk splitting logic */
   }
 
   if (m == NULL) return NULL; /* propagate failure */
diff --git a/common/eeprom/eeprom_field.c b/common/eeprom/eeprom_field.c
new file mode 100644
index 0000000..7f095a6
--- /dev/null
+++ b/common/eeprom/eeprom_field.c
@@ -0,0 +1,250 @@
+/*
+ * (C) Copyright 2009-2016 CompuLab, Ltd.
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/string.h>
+#include <eeprom_field.h>
+
+static void __eeprom_field_print_bin(const struct eeprom_field *field,
+				     char *delimiter, bool reverse)
+{
+	int i;
+	int from = reverse ? field->size - 1 : 0;
+	int to = reverse ? 0 : field->size - 1;
+
+	printf(PRINT_FIELD_SEGMENT, field->name);
+	for (i = from; i != to; reverse ? i-- : i++)
+		printf("%02x%s", field->buf[i], delimiter);
+
+	printf("%02x\n", field->buf[i]);
+}
+
+static int __eeprom_field_update_bin(struct eeprom_field *field,
+				     const char *value, bool reverse)
+{
+	int len = strlen(value);
+	int k, j, i = reverse ? len - 1 : 0;
+	unsigned char byte;
+	char *endptr;
+
+	/* each two characters in the string fit in one byte */
+	if (len > field->size * 2)
+		return -1;
+
+	memset(field->buf, 0, field->size);
+
+	/* i - string iterator, j - buf iterator */
+	for (j = 0; j < field->size; j++) {
+		byte = 0;
+		char tmp[3] = { 0, 0, 0 };
+
+		if ((reverse && i < 0) || (!reverse && i >= len))
+			break;
+
+		for (k = 0; k < 2; k++) {
+			if (reverse && i == 0) {
+				tmp[k] = value[i];
+				break;
+			}
+
+			tmp[k] = value[reverse ? i - 1 + k : i + k];
+		}
+
+		byte = simple_strtoul(tmp, &endptr, 0);
+		if (*endptr != '\0' || byte < 0)
+			return -1;
+
+		field->buf[j] = byte;
+		i = reverse ? i - 2 : i + 2;
+	}
+
+	return 0;
+}
+
+static int __eeprom_field_update_bin_delim(struct eeprom_field *field,
+					   char *value, char *delimiter)
+{
+	int count = 0;
+	int i, val;
+	const char *tmp = value;
+	char *tok;
+	char *endptr;
+
+	tmp = strstr(tmp, delimiter);
+	while (tmp != NULL) {
+		count++;
+		tmp++;
+		tmp = strstr(tmp, delimiter);
+	}
+
+	if (count > field->size)
+		return -1;
+
+	tok = strtok(value, delimiter);
+	for (i = 0; tok && i < field->size; i++) {
+		val = simple_strtoul(tok, &endptr, 0);
+		if (*endptr != '\0')
+			return -1;
+
+		/* here we assume that each tok is no more than byte long */
+		field->buf[i] = (unsigned char)val;
+		tok = strtok(NULL, delimiter);
+	}
+
+	return 0;
+}
+
+/**
+ * eeprom_field_print_bin() - print a field which contains binary data
+ *
+ * Treat the field data as simple binary data, and print it as two digit
+ * hexadecimal values.
+ * Sample output:
+ *      Field Name       0102030405060708090a
+ *
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_bin(const struct eeprom_field *field)
+{
+	__eeprom_field_print_bin(field, "", false);
+}
+
+/**
+ * eeprom_field_update_bin() - Update field with new data in binary form
+ *
+ * @field:	an initialized field
+ * @value:	a string of values (i.e. "10b234a")
+ */
+int eeprom_field_update_bin(struct eeprom_field *field, char *value)
+{
+	return __eeprom_field_update_bin(field, value, false);
+}
+
+/**
+ * eeprom_field_update_reserved() - Update reserved field with new data in
+ *				    binary form
+ *
+ * @field:	an initialized field
+ * @value:	a space delimited string of byte values (i.e. "1 02 3 0x4")
+ */
+int eeprom_field_update_reserved(struct eeprom_field *field, char *value)
+{
+	return __eeprom_field_update_bin_delim(field, value, " ");
+}
+
+/**
+ * eeprom_field_print_bin_rev() - print a field which contains binary data in
+ *				  reverse order
+ *
+ * Treat the field data as simple binary data, and print it in reverse order
+ * as two digit hexadecimal values.
+ *
+ * Data in field:
+ *                      0102030405060708090a
+ * Sample output:
+ *      Field Name      0a090807060504030201
+ *
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_bin_rev(const struct eeprom_field *field)
+{
+	__eeprom_field_print_bin(field, "", true);
+}
+
+/**
+ * eeprom_field_update_bin_rev() - Update field with new data in binary form,
+ *				   storing it in reverse
+ *
+ * This function takes a string of byte values, and stores them
+ * in the field in the reverse order. i.e. if the input string was "1234",
+ * "3412" will be written to the field.
+ *
+ * @field:	an initialized field
+ * @value:	a string of byte values
+ */
+int eeprom_field_update_bin_rev(struct eeprom_field *field, char *value)
+{
+	return __eeprom_field_update_bin(field, value, true);
+}
+
+/**
+ * eeprom_field_print_mac_addr() - print a field which contains a mac address
+ *
+ * Treat the field data as simple binary data, and print it formatted as a MAC
+ * address.
+ * Sample output:
+ *      Field Name     01:02:03:04:05:06
+ *
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_mac(const struct eeprom_field *field)
+{
+	__eeprom_field_print_bin(field, ":", false);
+}
+
+/**
+ * eeprom_field_update_mac() - Update a mac address field which contains binary
+ *			       data
+ *
+ * @field:	an initialized field
+ * @value:	a colon delimited string of byte values (i.e. "1:02:3:ff")
+ */
+int eeprom_field_update_mac(struct eeprom_field *field, char *value)
+{
+	return __eeprom_field_update_bin_delim(field, value, ":");
+}
+
+/**
+ * eeprom_field_print_ascii() - print a field which contains ASCII data
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_ascii(const struct eeprom_field *field)
+{
+	char format[8];
+
+	sprintf(format, "%%.%ds\n", field->size);
+	printf(PRINT_FIELD_SEGMENT, field->name);
+	printf(format, field->buf);
+}
+
+/**
+ * eeprom_field_update_ascii() - Update field with new data in ASCII form
+ * @field:	an initialized field
+ * @value:	the new string data
+ *
+ * Returns 0 on success, -1 of failure (new string too long).
+ */
+int eeprom_field_update_ascii(struct eeprom_field *field, char *value)
+{
+	if (strlen(value) >= field->size) {
+		printf("%s: new data too long\n", field->name);
+		return -1;
+	}
+
+	strncpy((char *)field->buf, value, field->size - 1);
+	field->buf[field->size - 1] = '\0';
+
+	return 0;
+}
+
+/**
+ * eeprom_field_print_reserved() - print the "Reserved fields" field
+ *
+ * Print a notice that the following field_size bytes are reserved.
+ *
+ * Sample output:
+ *      Reserved fields              (64 bytes)
+ *
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_reserved(const struct eeprom_field *field)
+{
+	printf(PRINT_FIELD_SEGMENT, "Reserved fields\t");
+	printf("(%d bytes)\n", field->size);
+}
diff --git a/common/eeprom/eeprom_layout.c b/common/eeprom/eeprom_layout.c
new file mode 100644
index 0000000..c059233
--- /dev/null
+++ b/common/eeprom/eeprom_layout.c
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2009-2016 CompuLab, Ltd.
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/kernel.h>
+#include <eeprom_layout.h>
+#include <eeprom_field.h>
+
+#define NO_LAYOUT_FIELDS	"Unknown layout. Dumping raw data\n"
+
+struct eeprom_field layout_unknown[1] = {
+	{ NO_LAYOUT_FIELDS, 256, NULL, eeprom_field_print_bin,
+				       eeprom_field_update_bin },
+};
+
+/*
+ * eeprom_layout_detect() - detect layout based on the contents of the data.
+ * @data: Pointer to the data to be analyzed.
+ *
+ * Returns: the detected layout version.
+ */
+__weak int eeprom_layout_detect(unsigned char *data)
+{
+	return LAYOUT_VERSION_UNRECOGNIZED;
+}
+
+/*
+ * __eeprom_layout_assign() - set the layout fields
+ * @layout:		A pointer to an existing struct layout.
+ * @layout_version:	The version number of the desired layout
+ */
+__weak void __eeprom_layout_assign(struct eeprom_layout *layout,
+				   int layout_version)
+{
+	layout->fields = layout_unknown;
+	layout->num_of_fields = ARRAY_SIZE(layout_unknown);
+}
+void eeprom_layout_assign(struct eeprom_layout *layout, int layout_version) \
+		__attribute__((weak, alias("__eeprom_layout_assign")));
+
+/*
+ * eeprom_layout_print() - print the layout and the data which is assigned to it
+ * @layout: A pointer to an existing struct layout.
+ */
+static void eeprom_layout_print(const struct eeprom_layout *layout)
+{
+	int i;
+	struct eeprom_field *fields = layout->fields;
+
+	for (i = 0; i < layout->num_of_fields; i++)
+		fields[i].print(&fields[i]);
+}
+
+/*
+ * eeprom_layout_update_field() - update a single field in the layout data.
+ * @layout:	A pointer to an existing struct layout.
+ * @field_name:	The name of the field to update.
+ * @new_data:	The new field data (a string. Format depends on the field)
+ *
+ * Returns: 0 on success, negative error value on failure.
+ */
+static int eeprom_layout_update_field(struct eeprom_layout *layout,
+				      char *field_name, char *new_data)
+{
+	int i, err;
+	struct eeprom_field *fields = layout->fields;
+
+	if (new_data == NULL)
+		return 0;
+
+	if (field_name == NULL)
+		return -1;
+
+	for (i = 0; i < layout->num_of_fields; i++) {
+		if (fields[i].name == RESERVED_FIELDS ||
+		    strcmp(fields[i].name, field_name))
+			continue;
+
+		err = fields[i].update(&fields[i], new_data);
+		if (err)
+			printf("Invalid data for field %s\n", field_name);
+
+		return err;
+	}
+
+	printf("No such field '%s'\n", field_name);
+
+	return -1;
+}
+
+/*
+ * eeprom_layout_setup() - setup layout struct with the layout data and
+ *			   metadata as dictated by layout_version
+ * @layout:	A pointer to an existing struct layout.
+ * @buf:	A buffer initialized with the eeprom data.
+ * @buf_size:	Size of buf in bytes.
+ * @layout version: The version number of the layout.
+ */
+void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf,
+			 unsigned int buf_size, int layout_version)
+{
+	int i;
+
+	if (layout_version == LAYOUT_VERSION_AUTODETECT)
+		layout->layout_version = eeprom_layout_detect(buf);
+	else
+		layout->layout_version = layout_version;
+
+	eeprom_layout_assign(layout, layout_version);
+	layout->data = buf;
+	for (i = 0; i < layout->num_of_fields; i++) {
+		layout->fields[i].buf = buf;
+		buf += layout->fields[i].size;
+	}
+
+	layout->data_size = buf_size;
+	layout->print = eeprom_layout_print;
+	layout->update = eeprom_layout_update_field;
+}
diff --git a/common/env_mmc.c b/common/env_mmc.c
index bdb452e..c7fef18 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -86,8 +86,8 @@
 	dev = 0;
 #endif
 
-	env_mmc_orig_hwpart = mmc->block_dev.hwpart;
-	ret = mmc_select_hwpart(dev, part);
+	env_mmc_orig_hwpart = mmc_get_blk_desc(mmc)->hwpart;
+	ret = blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part);
 	if (ret)
 		puts("MMC partition switch failed\n");
 
@@ -119,7 +119,7 @@
 #ifdef CONFIG_SPL_BUILD
 	dev = 0;
 #endif
-	mmc_select_hwpart(dev, env_mmc_orig_hwpart);
+	blk_select_hwpart_devnum(IF_TYPE_MMC, dev, env_mmc_orig_hwpart);
 #endif
 }
 
diff --git a/common/ide.c b/common/ide.c
new file mode 100644
index 0000000..ac5b91c
--- /dev/null
+++ b/common/ide.c
@@ -0,0 +1,1231 @@
+/*
+ * (C) Copyright 2000-2011
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ata.h>
+#include <dm.h>
+#include <ide.h>
+#include <watchdog.h>
+#include <asm/io.h>
+
+#ifdef __PPC__
+# define EIEIO		__asm__ volatile ("eieio")
+# define SYNC		__asm__ volatile ("sync")
+#else
+# define EIEIO		/* nothing */
+# define SYNC		/* nothing */
+#endif
+
+/* Current offset for IDE0 / IDE1 bus access	*/
+ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS] = {
+#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
+	CONFIG_SYS_ATA_IDE0_OFFSET,
+#endif
+#if defined(CONFIG_SYS_ATA_IDE1_OFFSET) && (CONFIG_SYS_IDE_MAXBUS > 1)
+	CONFIG_SYS_ATA_IDE1_OFFSET,
+#endif
+};
+
+static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
+
+struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
+
+#define IDE_TIME_OUT	2000	/* 2 sec timeout */
+
+#define ATAPI_TIME_OUT	7000	/* 7 sec timeout (5 sec seems to work...) */
+
+#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
+
+#ifndef CONFIG_SYS_ATA_PORT_ADDR
+#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
+#endif
+
+#ifndef CONFIG_IDE_LED	/* define LED macros, they are not used anyways */
+# define DEVICE_LED(x) 0
+# define LED_IDE1 1
+# define LED_IDE2 2
+#endif
+
+#ifdef CONFIG_IDE_RESET
+extern void ide_set_reset(int idereset);
+
+static void ide_reset(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
+		ide_bus_ok[i] = 0;
+	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
+		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+
+	ide_set_reset(1);	/* assert reset */
+
+	/* the reset signal shall be asserted for et least 25 us */
+	udelay(25);
+
+	WATCHDOG_RESET();
+
+	/* de-assert RESET signal */
+	ide_set_reset(0);
+
+	/* wait 250 ms */
+	for (i = 0; i < 250; ++i)
+		udelay(1000);
+}
+#else
+#define ide_reset()	/* dummy */
+#endif /* CONFIG_IDE_RESET */
+
+/*
+ * Wait until Busy bit is off, or timeout (in ms)
+ * Return last status
+ */
+static uchar ide_wait(int dev, ulong t)
+{
+	ulong delay = 10 * t;	/* poll every 100 us */
+	uchar c;
+
+	while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
+		udelay(100);
+		if (delay-- == 0)
+			break;
+	}
+	return c;
+}
+
+/*
+ * copy src to dest, skipping leading and trailing blanks and null
+ * terminate the string
+ * "len" is the size of available memory including the terminating '\0'
+ */
+static void ident_cpy(unsigned char *dst, unsigned char *src,
+		      unsigned int len)
+{
+	unsigned char *end, *last;
+
+	last = dst;
+	end = src + len - 1;
+
+	/* reserve space for '\0' */
+	if (len < 2)
+		goto OUT;
+
+	/* skip leading white space */
+	while ((*src) && (src < end) && (*src == ' '))
+		++src;
+
+	/* copy string, omitting trailing white space */
+	while ((*src) && (src < end)) {
+		*dst++ = *src;
+		if (*src++ != ' ')
+			last = dst;
+	}
+OUT:
+	*last = '\0';
+}
+
+#ifdef CONFIG_ATAPI
+/****************************************************************************
+ * ATAPI Support
+ */
+
+#if defined(CONFIG_IDE_SWAP_IO)
+/* since ATAPI may use commands with not 4 bytes alligned length
+ * we have our own transfer functions, 2 bytes alligned */
+__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+	ushort *dbuf;
+	volatile ushort *pbuf;
+
+	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	dbuf = (ushort *)sect_buf;
+
+	debug("in output data shorts base for read is %lx\n",
+	      (unsigned long) pbuf);
+
+	while (shorts--) {
+		EIEIO;
+		*pbuf = *dbuf++;
+	}
+}
+
+__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+	ushort *dbuf;
+	volatile ushort *pbuf;
+
+	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	dbuf = (ushort *)sect_buf;
+
+	debug("in input data shorts base for read is %lx\n",
+	      (unsigned long) pbuf);
+
+	while (shorts--) {
+		EIEIO;
+		*dbuf++ = *pbuf;
+	}
+}
+
+#else  /* ! CONFIG_IDE_SWAP_IO */
+__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
+}
+
+__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
+}
+
+#endif /* CONFIG_IDE_SWAP_IO */
+
+/*
+ * Wait until (Status & mask) == res, or timeout (in ms)
+ * Return last status
+ * This is used since some ATAPI CD ROMs clears their Busy Bit first
+ * and then they set their DRQ Bit
+ */
+static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
+{
+	ulong delay = 10 * t;	/* poll every 100 us */
+	uchar c;
+
+	/* prevents to read the status before valid */
+	c = ide_inb(dev, ATA_DEV_CTL);
+
+	while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
+		/* break if error occurs (doesn't make sense to wait more) */
+		if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
+			break;
+		udelay(100);
+		if (delay-- == 0)
+			break;
+	}
+	return c;
+}
+
+/*
+ * issue an atapi command
+ */
+unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
+			  unsigned char *buffer, int buflen)
+{
+	unsigned char c, err, mask, res;
+	int n;
+
+	ide_led(DEVICE_LED(device), 1);	/* LED on       */
+
+	/* Select device
+	 */
+	mask = ATA_STAT_BUSY | ATA_STAT_DRQ;
+	res = 0;
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+	if ((c & mask) != res) {
+		printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
+		       c);
+		err = 0xFF;
+		goto AI_OUT;
+	}
+	/* write taskfile */
+	ide_outb(device, ATA_ERROR_REG, 0);	/* no DMA, no overlaped */
+	ide_outb(device, ATA_SECT_CNT, 0);
+	ide_outb(device, ATA_SECT_NUM, 0);
+	ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
+	ide_outb(device, ATA_CYL_HIGH,
+		 (unsigned char) ((buflen >> 8) & 0xFF));
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+
+	ide_outb(device, ATA_COMMAND, ATAPI_CMD_PACKET);
+	udelay(50);
+
+	mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
+	res = ATA_STAT_DRQ;
+	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+
+	if ((c & mask) != res) {	/* DRQ must be 1, BSY 0 */
+		printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
+		       device, c);
+		err = 0xFF;
+		goto AI_OUT;
+	}
+
+	/* write command block */
+	ide_output_data_shorts(device, (unsigned short *)ccb, ccblen / 2);
+
+	/* ATAPI Command written wait for completition */
+	udelay(5000);		/* device must set bsy */
+
+	mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
+	/*
+	 * if no data wait for DRQ = 0 BSY = 0
+	 * if data wait for DRQ = 1 BSY = 0
+	 */
+	res = 0;
+	if (buflen)
+		res = ATA_STAT_DRQ;
+	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+	if ((c & mask) != res) {
+		if (c & ATA_STAT_ERR) {
+			err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
+			debug("atapi_issue 1 returned sense key %X status %02X\n",
+			      err, c);
+		} else {
+			printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x)  status 0x%02x\n",
+			       ccb[0], c);
+			err = 0xFF;
+		}
+		goto AI_OUT;
+	}
+	n = ide_inb(device, ATA_CYL_HIGH);
+	n <<= 8;
+	n += ide_inb(device, ATA_CYL_LOW);
+	if (n > buflen) {
+		printf("ERROR, transfer bytes %d requested only %d\n", n,
+		       buflen);
+		err = 0xff;
+		goto AI_OUT;
+	}
+	if ((n == 0) && (buflen < 0)) {
+		printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
+		err = 0xff;
+		goto AI_OUT;
+	}
+	if (n != buflen) {
+		debug("WARNING, transfer bytes %d not equal with requested %d\n",
+		      n, buflen);
+	}
+	if (n != 0) {		/* data transfer */
+		debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
+		/* we transfer shorts */
+		n >>= 1;
+		/* ok now decide if it is an in or output */
+		if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
+			debug("Write to device\n");
+			ide_output_data_shorts(device, (unsigned short *)buffer,
+					       n);
+		} else {
+			debug("Read from device @ %p shorts %d\n", buffer, n);
+			ide_input_data_shorts(device, (unsigned short *)buffer,
+					      n);
+		}
+	}
+	udelay(5000);		/* seems that some CD ROMs need this... */
+	mask = ATA_STAT_BUSY | ATA_STAT_ERR;
+	res = 0;
+	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
+		err = (ide_inb(device, ATA_ERROR_REG) >> 4);
+		debug("atapi_issue 2 returned sense key %X status %X\n", err,
+		      c);
+	} else {
+		err = 0;
+	}
+AI_OUT:
+	ide_led(DEVICE_LED(device), 0);	/* LED off      */
+	return err;
+}
+
+/*
+ * sending the command to atapi_issue. If an status other than good
+ * returns, an request_sense will be issued
+ */
+
+#define ATAPI_DRIVE_NOT_READY	100
+#define ATAPI_UNIT_ATTN		10
+
+unsigned char atapi_issue_autoreq(int device,
+				  unsigned char *ccb,
+				  int ccblen,
+				  unsigned char *buffer, int buflen)
+{
+	unsigned char sense_data[18], sense_ccb[12];
+	unsigned char res, key, asc, ascq;
+	int notready, unitattn;
+
+	unitattn = ATAPI_UNIT_ATTN;
+	notready = ATAPI_DRIVE_NOT_READY;
+
+retry:
+	res = atapi_issue(device, ccb, ccblen, buffer, buflen);
+	if (res == 0)
+		return 0;	/* Ok */
+
+	if (res == 0xFF)
+		return 0xFF;	/* error */
+
+	debug("(auto_req)atapi_issue returned sense key %X\n", res);
+
+	memset(sense_ccb, 0, sizeof(sense_ccb));
+	memset(sense_data, 0, sizeof(sense_data));
+	sense_ccb[0] = ATAPI_CMD_REQ_SENSE;
+	sense_ccb[4] = 18;	/* allocation Length */
+
+	res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
+	key = (sense_data[2] & 0xF);
+	asc = (sense_data[12]);
+	ascq = (sense_data[13]);
+
+	debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
+	debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
+	      sense_data[0], key, asc, ascq);
+
+	if ((key == 0))
+		return 0;	/* ok device ready */
+
+	if ((key == 6) || (asc == 0x29) || (asc == 0x28)) { /* Unit Attention */
+		if (unitattn-- > 0) {
+			udelay(200 * 1000);
+			goto retry;
+		}
+		printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
+		goto error;
+	}
+	if ((asc == 0x4) && (ascq == 0x1)) {
+		/* not ready, but will be ready soon */
+		if (notready-- > 0) {
+			udelay(200 * 1000);
+			goto retry;
+		}
+		printf("Drive not ready, tried %d times\n",
+		       ATAPI_DRIVE_NOT_READY);
+		goto error;
+	}
+	if (asc == 0x3a) {
+		debug("Media not present\n");
+		goto error;
+	}
+
+	printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
+	       ascq);
+error:
+	debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
+	return 0xFF;
+}
+
+/*
+ * atapi_read:
+ * we transfer only one block per command, since the multiple DRQ per
+ * command is not yet implemented
+ */
+#define ATAPI_READ_MAX_BYTES	2048	/* we read max 2kbytes */
+#define ATAPI_READ_BLOCK_SIZE	2048	/* assuming CD part */
+#define ATAPI_READ_MAX_BLOCK	(ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
+
+ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+		 void *buffer)
+{
+	int device = block_dev->devnum;
+	ulong n = 0;
+	unsigned char ccb[12];	/* Command descriptor block */
+	ulong cnt;
+
+	debug("atapi_read dev %d start " LBAF " blocks " LBAF
+	      " buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer);
+
+	do {
+		if (blkcnt > ATAPI_READ_MAX_BLOCK)
+			cnt = ATAPI_READ_MAX_BLOCK;
+		else
+			cnt = blkcnt;
+
+		ccb[0] = ATAPI_CMD_READ_12;
+		ccb[1] = 0;	/* reserved */
+		ccb[2] = (unsigned char) (blknr >> 24) & 0xFF;	/* MSB Block */
+		ccb[3] = (unsigned char) (blknr >> 16) & 0xFF;	/*  */
+		ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
+		ccb[5] = (unsigned char) blknr & 0xFF;	/* LSB Block */
+		ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
+		ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
+		ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
+		ccb[9] = (unsigned char) cnt & 0xFF;	/* LSB Block */
+		ccb[10] = 0;	/* reserved */
+		ccb[11] = 0;	/* reserved */
+
+		if (atapi_issue_autoreq(device, ccb, 12,
+					(unsigned char *)buffer,
+					cnt * ATAPI_READ_BLOCK_SIZE)
+		    == 0xFF) {
+			return n;
+		}
+		n += cnt;
+		blkcnt -= cnt;
+		blknr += cnt;
+		buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
+	} while (blkcnt > 0);
+	return n;
+}
+
+static void atapi_inquiry(struct blk_desc *dev_desc)
+{
+	unsigned char ccb[12];	/* Command descriptor block */
+	unsigned char iobuf[64];	/* temp buf */
+	unsigned char c;
+	int device;
+
+	device = dev_desc->devnum;
+	dev_desc->type = DEV_TYPE_UNKNOWN;	/* not yet valid */
+	dev_desc->block_read = atapi_read;
+
+	memset(ccb, 0, sizeof(ccb));
+	memset(iobuf, 0, sizeof(iobuf));
+
+	ccb[0] = ATAPI_CMD_INQUIRY;
+	ccb[4] = 40;		/* allocation Legnth */
+	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 40);
+
+	debug("ATAPI_CMD_INQUIRY returned %x\n", c);
+	if (c != 0)
+		return;
+
+	/* copy device ident strings */
+	ident_cpy((unsigned char *)dev_desc->vendor, &iobuf[8], 8);
+	ident_cpy((unsigned char *)dev_desc->product, &iobuf[16], 16);
+	ident_cpy((unsigned char *)dev_desc->revision, &iobuf[32], 5);
+
+	dev_desc->lun = 0;
+	dev_desc->lba = 0;
+	dev_desc->blksz = 0;
+	dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
+	dev_desc->type = iobuf[0] & 0x1f;
+
+	if ((iobuf[1] & 0x80) == 0x80)
+		dev_desc->removable = 1;
+	else
+		dev_desc->removable = 0;
+
+	memset(ccb, 0, sizeof(ccb));
+	memset(iobuf, 0, sizeof(iobuf));
+	ccb[0] = ATAPI_CMD_START_STOP;
+	ccb[4] = 0x03;		/* start */
+
+	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
+
+	debug("ATAPI_CMD_START_STOP returned %x\n", c);
+	if (c != 0)
+		return;
+
+	memset(ccb, 0, sizeof(ccb));
+	memset(iobuf, 0, sizeof(iobuf));
+	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
+
+	debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
+	if (c != 0)
+		return;
+
+	memset(ccb, 0, sizeof(ccb));
+	memset(iobuf, 0, sizeof(iobuf));
+	ccb[0] = ATAPI_CMD_READ_CAP;
+	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 8);
+	debug("ATAPI_CMD_READ_CAP returned %x\n", c);
+	if (c != 0)
+		return;
+
+	debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
+	      iobuf[0], iobuf[1], iobuf[2], iobuf[3],
+	      iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
+
+	dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
+		((unsigned long) iobuf[1] << 16) +
+		((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
+	dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
+		((unsigned long) iobuf[5] << 16) +
+		((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
+	dev_desc->log2blksz = LOG2(dev_desc->blksz);
+#ifdef CONFIG_LBA48
+	/* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
+	dev_desc->lba48 = 0;
+#endif
+	return;
+}
+
+#endif /* CONFIG_ATAPI */
+
+static void ide_ident(struct blk_desc *dev_desc)
+{
+	unsigned char c;
+	hd_driveid_t iop;
+
+#ifdef CONFIG_ATAPI
+	int retries = 0;
+#endif
+	int device;
+
+	device = dev_desc->devnum;
+	printf("  Device %d: ", device);
+
+	ide_led(DEVICE_LED(device), 1);	/* LED on       */
+	/* Select device
+	 */
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+	dev_desc->if_type = IF_TYPE_IDE;
+#ifdef CONFIG_ATAPI
+
+	retries = 0;
+
+	/* Warning: This will be tricky to read */
+	while (retries <= 1) {
+		/* check signature */
+		if ((ide_inb(device, ATA_SECT_CNT) == 0x01) &&
+		    (ide_inb(device, ATA_SECT_NUM) == 0x01) &&
+		    (ide_inb(device, ATA_CYL_LOW) == 0x14) &&
+		    (ide_inb(device, ATA_CYL_HIGH) == 0xEB)) {
+			/* ATAPI Signature found */
+			dev_desc->if_type = IF_TYPE_ATAPI;
+			/*
+			 * Start Ident Command
+			 */
+			ide_outb(device, ATA_COMMAND, ATAPI_CMD_IDENT);
+			/*
+			 * Wait for completion - ATAPI devices need more time
+			 * to become ready
+			 */
+			c = ide_wait(device, ATAPI_TIME_OUT);
+		} else
+#endif
+		{
+			/*
+			 * Start Ident Command
+			 */
+			ide_outb(device, ATA_COMMAND, ATA_CMD_IDENT);
+
+			/*
+			 * Wait for completion
+			 */
+			c = ide_wait(device, IDE_TIME_OUT);
+		}
+		ide_led(DEVICE_LED(device), 0);	/* LED off      */
+
+		if (((c & ATA_STAT_DRQ) == 0) ||
+		    ((c & (ATA_STAT_FAULT | ATA_STAT_ERR)) != 0)) {
+#ifdef CONFIG_ATAPI
+			{
+				/*
+				 * Need to soft reset the device
+				 * in case it's an ATAPI...
+				 */
+				debug("Retrying...\n");
+				ide_outb(device, ATA_DEV_HD,
+					 ATA_LBA | ATA_DEVICE(device));
+				udelay(100000);
+				ide_outb(device, ATA_COMMAND, 0x08);
+				udelay(500000);	/* 500 ms */
+			}
+			/*
+			 * Select device
+			 */
+			ide_outb(device, ATA_DEV_HD,
+				 ATA_LBA | ATA_DEVICE(device));
+			retries++;
+#else
+			return;
+#endif
+		}
+#ifdef CONFIG_ATAPI
+		else
+			break;
+	}			/* see above - ugly to read */
+
+	if (retries == 2)	/* Not found */
+		return;
+#endif
+
+	ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
+
+	ident_cpy((unsigned char *)dev_desc->revision, iop.fw_rev,
+		  sizeof(dev_desc->revision));
+	ident_cpy((unsigned char *)dev_desc->vendor, iop.model,
+		  sizeof(dev_desc->vendor));
+	ident_cpy((unsigned char *)dev_desc->product, iop.serial_no,
+		  sizeof(dev_desc->product));
+#ifdef __LITTLE_ENDIAN
+	/*
+	 * firmware revision, model, and serial number have Big Endian Byte
+	 * order in Word. Convert all three to little endian.
+	 *
+	 * See CF+ and CompactFlash Specification Revision 2.0:
+	 * 6.2.1.6: Identify Drive, Table 39 for more details
+	 */
+
+	strswab(dev_desc->revision);
+	strswab(dev_desc->vendor);
+	strswab(dev_desc->product);
+#endif /* __LITTLE_ENDIAN */
+
+	if ((iop.config & 0x0080) == 0x0080)
+		dev_desc->removable = 1;
+	else
+		dev_desc->removable = 0;
+
+#ifdef CONFIG_ATAPI
+	if (dev_desc->if_type == IF_TYPE_ATAPI) {
+		atapi_inquiry(dev_desc);
+		return;
+	}
+#endif /* CONFIG_ATAPI */
+
+#ifdef __BIG_ENDIAN
+	/* swap shorts */
+	dev_desc->lba = (iop.lba_capacity << 16) | (iop.lba_capacity >> 16);
+#else  /* ! __BIG_ENDIAN */
+	/*
+	 * do not swap shorts on little endian
+	 *
+	 * See CF+ and CompactFlash Specification Revision 2.0:
+	 * 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details.
+	 */
+	dev_desc->lba = iop.lba_capacity;
+#endif /* __BIG_ENDIAN */
+
+#ifdef CONFIG_LBA48
+	if (iop.command_set_2 & 0x0400) {	/* LBA 48 support */
+		dev_desc->lba48 = 1;
+		dev_desc->lba = (unsigned long long) iop.lba48_capacity[0] |
+			((unsigned long long) iop.lba48_capacity[1] << 16) |
+			((unsigned long long) iop.lba48_capacity[2] << 32) |
+			((unsigned long long) iop.lba48_capacity[3] << 48);
+	} else {
+		dev_desc->lba48 = 0;
+	}
+#endif /* CONFIG_LBA48 */
+	/* assuming HD */
+	dev_desc->type = DEV_TYPE_HARDDISK;
+	dev_desc->blksz = ATA_BLOCKSIZE;
+	dev_desc->log2blksz = LOG2(dev_desc->blksz);
+	dev_desc->lun = 0;	/* just to fill something in... */
+
+#if 0				/* only used to test the powersaving mode,
+				 * if enabled, the drive goes after 5 sec
+				 * in standby mode */
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+	c = ide_wait(device, IDE_TIME_OUT);
+	ide_outb(device, ATA_SECT_CNT, 1);
+	ide_outb(device, ATA_LBA_LOW, 0);
+	ide_outb(device, ATA_LBA_MID, 0);
+	ide_outb(device, ATA_LBA_HIGH, 0);
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+	ide_outb(device, ATA_COMMAND, 0xe3);
+	udelay(50);
+	c = ide_wait(device, IDE_TIME_OUT);	/* can't take over 500 ms */
+#endif
+}
+
+__weak void ide_led(uchar led, uchar status)
+{
+#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
+	static uchar led_buffer;	/* Buffer for current LED status */
+
+	uchar *led_port = LED_PORT;
+
+	if (status)		/* switch LED on        */
+		led_buffer |= led;
+	else			/* switch LED off       */
+		led_buffer &= ~led;
+
+	*led_port = led_buffer;
+#endif
+}
+
+__weak void ide_outb(int dev, int port, unsigned char val)
+{
+	debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
+	      dev, port, val,
+	      (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+
+#if defined(CONFIG_IDE_AHB)
+	if (port) {
+		/* write command */
+		ide_write_register(dev, port, val);
+	} else {
+		/* write data */
+		outb(val, (ATA_CURR_BASE(dev)));
+	}
+#else
+	outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+#endif
+}
+
+__weak unsigned char ide_inb(int dev, int port)
+{
+	uchar val;
+
+#if defined(CONFIG_IDE_AHB)
+	val = ide_read_register(dev, port);
+#else
+	val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+#endif
+
+	debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
+	      dev, port,
+	      (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
+	return val;
+}
+
+void ide_init(void)
+{
+	unsigned char c;
+	int i, bus;
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+	extern int ide_devices_found;	/* Initialized in check_ide_device() */
+#endif /* CONFIG_IDE_8xx_PCCARD */
+
+#ifdef CONFIG_IDE_PREINIT
+	WATCHDOG_RESET();
+
+	if (ide_preinit()) {
+		puts("ide_preinit failed\n");
+		return;
+	}
+#endif /* CONFIG_IDE_PREINIT */
+
+	WATCHDOG_RESET();
+
+	/*
+	 * Reset the IDE just to be sure.
+	 * Light LED's to show
+	 */
+	ide_led((LED_IDE1 | LED_IDE2), 1);	/* LED's on     */
+
+	/* ATAPI Drives seems to need a proper IDE Reset */
+	ide_reset();
+
+#ifdef CONFIG_IDE_INIT_POSTRESET
+	WATCHDOG_RESET();
+
+	if (ide_init_postreset()) {
+		puts("ide_preinit_postreset failed\n");
+		return;
+	}
+#endif /* CONFIG_IDE_INIT_POSTRESET */
+
+	/*
+	 * Wait for IDE to get ready.
+	 * According to spec, this can take up to 31 seconds!
+	 */
+	for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
+		int dev =
+			bus * (CONFIG_SYS_IDE_MAXDEVICE /
+			       CONFIG_SYS_IDE_MAXBUS);
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+		/* Skip non-ide devices from probing */
+		if ((ide_devices_found & (1 << bus)) == 0) {
+			ide_led((LED_IDE1 | LED_IDE2), 0);	/* LED's off */
+			continue;
+		}
+#endif
+		printf("Bus %d: ", bus);
+
+		ide_bus_ok[bus] = 0;
+
+		/* Select device
+		 */
+		udelay(100000);	/* 100 ms */
+		ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
+		udelay(100000);	/* 100 ms */
+		i = 0;
+		do {
+			udelay(10000);	/* 10 ms */
+
+			c = ide_inb(dev, ATA_STATUS);
+			i++;
+			if (i > (ATA_RESET_TIME * 100)) {
+				puts("** Timeout **\n");
+				/* LED's off */
+				ide_led((LED_IDE1 | LED_IDE2), 0);
+				return;
+			}
+			if ((i >= 100) && ((i % 100) == 0))
+				putc('.');
+
+		} while (c & ATA_STAT_BUSY);
+
+		if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
+			puts("not available  ");
+			debug("Status = 0x%02X ", c);
+#ifndef CONFIG_ATAPI		/* ATAPI Devices do not set DRDY */
+		} else if ((c & ATA_STAT_READY) == 0) {
+			puts("not available  ");
+			debug("Status = 0x%02X ", c);
+#endif
+		} else {
+			puts("OK ");
+			ide_bus_ok[bus] = 1;
+		}
+		WATCHDOG_RESET();
+	}
+
+	putc('\n');
+
+	ide_led((LED_IDE1 | LED_IDE2), 0);	/* LED's off    */
+
+	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
+		int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
+		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+		ide_dev_desc[i].if_type = IF_TYPE_IDE;
+		ide_dev_desc[i].devnum = i;
+		ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+		ide_dev_desc[i].blksz = 0;
+		ide_dev_desc[i].log2blksz =
+			LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
+		ide_dev_desc[i].lba = 0;
+#ifndef CONFIG_BLK
+		ide_dev_desc[i].block_read = ide_read;
+		ide_dev_desc[i].block_write = ide_write;
+#endif
+		if (!ide_bus_ok[IDE_BUS(i)])
+			continue;
+		ide_led(led, 1);	/* LED on       */
+		ide_ident(&ide_dev_desc[i]);
+		ide_led(led, 0);	/* LED off      */
+		dev_print(&ide_dev_desc[i]);
+
+		if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
+			/* initialize partition type */
+			part_init(&ide_dev_desc[i]);
+		}
+	}
+	WATCHDOG_RESET();
+}
+
+/* We only need to swap data if we are running on a big endian cpu. */
+#if defined(__LITTLE_ENDIAN)
+__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+	ide_input_data(dev, sect_buf, words);
+}
+#else
+__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+	volatile ushort *pbuf =
+		(ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	ushort *dbuf = (ushort *)sect_buf;
+
+	debug("in input swap data base for read is %lx\n",
+	      (unsigned long) pbuf);
+
+	while (words--) {
+#ifdef __MIPS__
+		*dbuf++ = swab16p((u16 *)pbuf);
+		*dbuf++ = swab16p((u16 *)pbuf);
+#else
+		*dbuf++ = ld_le16(pbuf);
+		*dbuf++ = ld_le16(pbuf);
+#endif /* !MIPS */
+	}
+}
+#endif /* __LITTLE_ENDIAN */
+
+
+#if defined(CONFIG_IDE_SWAP_IO)
+__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+	ushort *dbuf;
+	volatile ushort *pbuf;
+
+	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	dbuf = (ushort *)sect_buf;
+	while (words--) {
+		EIEIO;
+		*pbuf = *dbuf++;
+		EIEIO;
+		*pbuf = *dbuf++;
+	}
+}
+#else  /* ! CONFIG_IDE_SWAP_IO */
+__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+#if defined(CONFIG_IDE_AHB)
+	ide_write_data(dev, sect_buf, words);
+#else
+	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
+#endif
+}
+#endif /* CONFIG_IDE_SWAP_IO */
+
+#if defined(CONFIG_IDE_SWAP_IO)
+__weak void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+	ushort *dbuf;
+	volatile ushort *pbuf;
+
+	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	dbuf = (ushort *)sect_buf;
+
+	debug("in input data base for read is %lx\n", (unsigned long) pbuf);
+
+	while (words--) {
+		EIEIO;
+		*dbuf++ = *pbuf;
+		EIEIO;
+		*dbuf++ = *pbuf;
+	}
+}
+#else  /* ! CONFIG_IDE_SWAP_IO */
+__weak void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+#if defined(CONFIG_IDE_AHB)
+	ide_read_data(dev, sect_buf, words);
+#else
+	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
+#endif
+}
+
+#endif /* CONFIG_IDE_SWAP_IO */
+
+#ifdef CONFIG_BLK
+ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+	       void *buffer)
+#else
+ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+	       void *buffer)
+#endif
+{
+#ifdef CONFIG_BLK
+	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
+	int device = block_dev->devnum;
+	ulong n = 0;
+	unsigned char c;
+	unsigned char pwrsave = 0;	/* power save */
+
+#ifdef CONFIG_LBA48
+	unsigned char lba48 = 0;
+
+	if (blknr & 0x0000fffff0000000ULL) {
+		/* more than 28 bits used, use 48bit mode */
+		lba48 = 1;
+	}
+#endif
+	debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n",
+	      device, blknr, blkcnt, (ulong) buffer);
+
+	ide_led(DEVICE_LED(device), 1);	/* LED on       */
+
+	/* Select device
+	 */
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+	c = ide_wait(device, IDE_TIME_OUT);
+
+	if (c & ATA_STAT_BUSY) {
+		printf("IDE read: device %d not ready\n", device);
+		goto IDE_READ_E;
+	}
+
+	/* first check if the drive is in Powersaving mode, if yes,
+	 * increase the timeout value */
+	ide_outb(device, ATA_COMMAND, ATA_CMD_CHK_PWR);
+	udelay(50);
+
+	c = ide_wait(device, IDE_TIME_OUT);	/* can't take over 500 ms */
+
+	if (c & ATA_STAT_BUSY) {
+		printf("IDE read: device %d not ready\n", device);
+		goto IDE_READ_E;
+	}
+	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
+		printf("No Powersaving mode %X\n", c);
+	} else {
+		c = ide_inb(device, ATA_SECT_CNT);
+		debug("Powersaving %02X\n", c);
+		if (c == 0)
+			pwrsave = 1;
+	}
+
+
+	while (blkcnt-- > 0) {
+		c = ide_wait(device, IDE_TIME_OUT);
+
+		if (c & ATA_STAT_BUSY) {
+			printf("IDE read: device %d not ready\n", device);
+			break;
+		}
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			/* write high bits */
+			ide_outb(device, ATA_SECT_CNT, 0);
+			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
+#ifdef CONFIG_SYS_64BIT_LBA
+			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
+			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+#else
+			ide_outb(device, ATA_LBA_MID, 0);
+			ide_outb(device, ATA_LBA_HIGH, 0);
+#endif
+		}
+#endif
+		ide_outb(device, ATA_SECT_CNT, 1);
+		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
+		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
+		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
+
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			ide_outb(device, ATA_DEV_HD,
+				 ATA_LBA | ATA_DEVICE(device));
+			ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT);
+
+		} else
+#endif
+		{
+			ide_outb(device, ATA_DEV_HD, ATA_LBA |
+				 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
+			ide_outb(device, ATA_COMMAND, ATA_CMD_READ);
+		}
+
+		udelay(50);
+
+		if (pwrsave) {
+			/* may take up to 4 sec */
+			c = ide_wait(device, IDE_SPIN_UP_TIME_OUT);
+			pwrsave = 0;
+		} else {
+			/* can't take over 500 ms */
+			c = ide_wait(device, IDE_TIME_OUT);
+		}
+
+		if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
+		    ATA_STAT_DRQ) {
+			printf("Error (no IRQ) dev %d blk " LBAF
+			       ": status %#02x\n", device, blknr, c);
+			break;
+		}
+
+		ide_input_data(device, buffer, ATA_SECTORWORDS);
+		(void) ide_inb(device, ATA_STATUS);	/* clear IRQ */
+
+		++n;
+		++blknr;
+		buffer += ATA_BLOCKSIZE;
+	}
+IDE_READ_E:
+	ide_led(DEVICE_LED(device), 0);	/* LED off      */
+	return n;
+}
+
+#ifdef CONFIG_BLK
+ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+		const void *buffer)
+#else
+ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+		const void *buffer)
+#endif
+{
+#ifdef CONFIG_BLK
+	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
+	int device = block_dev->devnum;
+	ulong n = 0;
+	unsigned char c;
+
+#ifdef CONFIG_LBA48
+	unsigned char lba48 = 0;
+
+	if (blknr & 0x0000fffff0000000ULL) {
+		/* more than 28 bits used, use 48bit mode */
+		lba48 = 1;
+	}
+#endif
+
+	ide_led(DEVICE_LED(device), 1);	/* LED on       */
+
+	/* Select device
+	 */
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+
+	while (blkcnt-- > 0) {
+		c = ide_wait(device, IDE_TIME_OUT);
+
+		if (c & ATA_STAT_BUSY) {
+			printf("IDE read: device %d not ready\n", device);
+			goto WR_OUT;
+		}
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			/* write high bits */
+			ide_outb(device, ATA_SECT_CNT, 0);
+			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
+#ifdef CONFIG_SYS_64BIT_LBA
+			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
+			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+#else
+			ide_outb(device, ATA_LBA_MID, 0);
+			ide_outb(device, ATA_LBA_HIGH, 0);
+#endif
+		}
+#endif
+		ide_outb(device, ATA_SECT_CNT, 1);
+		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
+		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
+		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
+
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			ide_outb(device, ATA_DEV_HD,
+				 ATA_LBA | ATA_DEVICE(device));
+			ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
+
+		} else
+#endif
+		{
+			ide_outb(device, ATA_DEV_HD, ATA_LBA |
+				 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
+			ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE);
+		}
+
+		udelay(50);
+
+		/* can't take over 500 ms */
+		c = ide_wait(device, IDE_TIME_OUT);
+
+		if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
+		    ATA_STAT_DRQ) {
+			printf("Error (no IRQ) dev %d blk " LBAF
+			       ": status %#02x\n", device, blknr, c);
+			goto WR_OUT;
+		}
+
+		ide_output_data(device, buffer, ATA_SECTORWORDS);
+		c = ide_inb(device, ATA_STATUS);	/* clear IRQ */
+		++n;
+		++blknr;
+		buffer += ATA_BLOCKSIZE;
+	}
+WR_OUT:
+	ide_led(DEVICE_LED(device), 0);	/* LED off      */
+	return n;
+}
+
+#if defined(CONFIG_OF_IDE_FIXUP)
+int ide_device_present(int dev)
+{
+	if (dev >= CONFIG_SYS_IDE_MAXBUS)
+		return 0;
+	return ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1;
+}
+#endif
+
+#ifdef CONFIG_BLK
+static const struct blk_ops ide_blk_ops = {
+	.read	= ide_read,
+	.write	= ide_write,
+};
+
+U_BOOT_DRIVER(ide_blk) = {
+	.name		= "ide_blk",
+	.id		= UCLASS_BLK,
+	.ops		= &ide_blk_ops,
+};
+#else
+U_BOOT_LEGACY_BLK(ide) = {
+	.if_typename	= "ide",
+	.if_type	= IF_TYPE_IDE,
+	.max_devs	= CONFIG_SYS_IDE_MAXDEVICE,
+	.desc		= ide_dev_desc,
+};
+#endif
diff --git a/common/image-fit.c b/common/image-fit.c
index 25f8a11..9873957 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -422,7 +422,8 @@
 	}
 
 	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
-	    (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK)) {
+	    (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK) ||
+	    (type == IH_TYPE_FPGA)) {
 		ret = fit_image_get_load(fit, image_noffset, &load);
 		printf("%s  Load Address: ", p);
 		if (ret)
@@ -886,9 +887,9 @@
 	ret = fdt_setprop(fit, noffset, FIT_TIMESTAMP_PROP, &t,
 				sizeof(uint32_t));
 	if (ret) {
-		printf("Can't set '%s' property for '%s' node (%s)\n",
-		       FIT_TIMESTAMP_PROP, fit_get_name(fit, noffset, NULL),
-		       fdt_strerror(ret));
+		debug("Can't set '%s' property for '%s' node (%s)\n",
+		      FIT_TIMESTAMP_PROP, fit_get_name(fit, noffset, NULL),
+		      fdt_strerror(ret));
 		return ret == -FDT_ERR_NOSPACE ? -ENOSPC : -1;
 	}
 
@@ -1483,6 +1484,10 @@
 	if (uname)
 		printf("%s  FDT:          %s\n", p, uname);
 
+	uname = (char *)fdt_getprop(fit, noffset, FIT_FPGA_PROP, NULL);
+	if (uname)
+		printf("%s  FPGA:         %s\n", p, uname);
+
 	/* Print out all of the specified loadables */
 	for (loadables_index = 0;
 	     fdt_get_string_index(fit, noffset,
@@ -1567,6 +1572,8 @@
 		return FIT_SETUP_PROP;
 	case IH_TYPE_LOADABLE:
 		return FIT_LOADABLE_PROP;
+	case IH_TYPE_FPGA:
+		return FIT_FPGA_PROP;
 	}
 
 	return "unknown";
@@ -1681,7 +1688,7 @@
 			fit_image_check_type(fit, noffset,
 					     IH_TYPE_KERNEL_NOLOAD));
 
-	os_ok = image_type == IH_TYPE_FLATDT ||
+	os_ok = image_type == IH_TYPE_FLATDT || IH_TYPE_FPGA ||
 		fit_image_check_os(fit, noffset, IH_OS_LINUX) ||
 		fit_image_check_os(fit, noffset, IH_OS_OPENRTOS);
 
diff --git a/common/image.c b/common/image.c
index 26d6c9a..0be09e5 100644
--- a/common/image.c
+++ b/common/image.c
@@ -32,6 +32,8 @@
 #if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <fpga.h>
+#include <xilinx.h>
 #endif
 
 #include <u-boot/md5.h>
@@ -159,6 +161,8 @@
 	{	IH_TYPE_RKSD,       "rksd",       "Rockchip SD Boot Image" },
 	{	IH_TYPE_RKSPI,      "rkspi",      "Rockchip SPI Boot Image" },
 	{	IH_TYPE_ZYNQIMAGE,  "zynqimage",  "Xilinx Zynq Boot Image" },
+	{	IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" },
+	{	IH_TYPE_FPGA,       "fpga",       "FPGA Image" },
 	{	-1,		    "",		  "",			},
 };
 
@@ -1210,6 +1214,96 @@
 }
 
 #if IMAGE_ENABLE_FIT
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
+		  uint8_t arch, const ulong *ld_start, ulong * const ld_len)
+{
+	ulong tmp_img_addr, img_data, img_len;
+	void *buf;
+	int conf_noffset;
+	int fit_img_result;
+	char *uname, *name;
+	int err;
+	int devnum = 0; /* TODO support multi fpga platforms */
+	const fpga_desc * const desc = fpga_get_desc(devnum);
+	xilinx_desc *desc_xilinx = desc->devdesc;
+
+	/* Check to see if the images struct has a FIT configuration */
+	if (!genimg_has_config(images)) {
+		debug("## FIT configuration was not specified\n");
+		return 0;
+	}
+
+	/*
+	 * Obtain the os FIT header from the images struct
+	 * copy from dataflash if needed
+	 */
+	tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
+	tmp_img_addr = genimg_get_image(tmp_img_addr);
+	buf = map_sysmem(tmp_img_addr, 0);
+	/*
+	 * Check image type. For FIT images get FIT node
+	 * and attempt to locate a generic binary.
+	 */
+	switch (genimg_get_format(buf)) {
+	case IMAGE_FORMAT_FIT:
+		conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
+
+		err = fdt_get_string_index(buf, conf_noffset, FIT_FPGA_PROP, 0,
+					   (const char **)&uname);
+		if (err < 0) {
+			debug("## FPGA image is not specified\n");
+			return 0;
+		}
+		fit_img_result = fit_image_load(images,
+						tmp_img_addr,
+						(const char **)&uname,
+						&(images->fit_uname_cfg),
+						arch,
+						IH_TYPE_FPGA,
+						BOOTSTAGE_ID_FPGA_INIT,
+						FIT_LOAD_OPTIONAL_NON_ZERO,
+						&img_data, &img_len);
+
+		debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n",
+		      uname, img_data, img_len);
+
+		if (fit_img_result < 0) {
+			/* Something went wrong! */
+			return fit_img_result;
+		}
+
+		if (img_len >= desc_xilinx->size) {
+			name = "full";
+			err = fpga_loadbitstream(devnum, (char *)img_data,
+						 img_len, BIT_FULL);
+			if (err)
+				err = fpga_load(devnum, (const void *)img_data,
+						img_len, BIT_FULL);
+		} else {
+			name = "partial";
+			err = fpga_loadbitstream(devnum, (char *)img_data,
+						 img_len, BIT_PARTIAL);
+			if (err)
+				err = fpga_load(devnum, (const void *)img_data,
+						img_len, BIT_PARTIAL);
+		}
+
+		printf("   Programming %s bitstream... ", name);
+		if (err)
+			printf("failed\n");
+		else
+			printf("OK\n");
+		break;
+	default:
+		printf("The given image format is not supported (corrupt?)\n");
+		return 1;
+	}
+
+	return 0;
+}
+#endif
+
 int boot_get_loadable(int argc, char * const argv[], bootm_headers_t *images,
 		uint8_t arch, const ulong *ld_start, ulong * const ld_len)
 {
diff --git a/common/sata.c b/common/sata.c
new file mode 100644
index 0000000..88f08c9
--- /dev/null
+++ b/common/sata.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2000-2005, DENX Software Engineering
+ *		Wolfgang Denk <wd@denx.de>
+ * Copyright (C) Procsys. All rights reserved.
+ *		Mushtaq Khan <mushtaq_k@procsys.com>
+ *			<mushtaqk_921@yahoo.co.in>
+ * Copyright (C) 2008 Freescale Semiconductor, Inc.
+ *		Dave Liu <daveliu@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <sata.h>
+
+struct blk_desc sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
+
+#ifdef CONFIG_PARTITIONS
+struct blk_desc *sata_get_dev(int dev)
+{
+	return (dev < CONFIG_SYS_SATA_MAX_DEVICE) ? &sata_dev_desc[dev] : NULL;
+}
+#endif
+
+#ifdef CONFIG_BLK
+static unsigned long sata_bread(struct udevice *dev, lbaint_t start,
+				lbaint_t blkcnt, void *dst)
+{
+	return -ENOSYS;
+}
+
+static unsigned long sata_bwrite(struct udevice *dev, lbaint_t start,
+				 lbaint_t blkcnt, const void *buffer)
+{
+	return -ENOSYS;
+}
+#else
+static unsigned long sata_bread(struct blk_desc *block_dev, lbaint_t start,
+				lbaint_t blkcnt, void *dst)
+{
+	return sata_read(block_dev->devnum, start, blkcnt, dst);
+}
+
+static unsigned long sata_bwrite(struct blk_desc *block_dev, lbaint_t start,
+				 lbaint_t blkcnt, const void *buffer)
+{
+	return sata_write(block_dev->devnum, start, blkcnt, buffer);
+}
+#endif
+
+int __sata_initialize(void)
+{
+	int rc;
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) {
+		memset(&sata_dev_desc[i], 0, sizeof(struct blk_desc));
+		sata_dev_desc[i].if_type = IF_TYPE_SATA;
+		sata_dev_desc[i].devnum = i;
+		sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+		sata_dev_desc[i].type = DEV_TYPE_HARDDISK;
+		sata_dev_desc[i].lba = 0;
+		sata_dev_desc[i].blksz = 512;
+		sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz);
+#ifndef CONFIG_BLK
+		sata_dev_desc[i].block_read = sata_bread;
+		sata_dev_desc[i].block_write = sata_bwrite;
+#endif
+		rc = init_sata(i);
+		if (!rc) {
+			rc = scan_sata(i);
+			if (!rc && sata_dev_desc[i].lba > 0 &&
+			    sata_dev_desc[i].blksz > 0)
+				part_init(&sata_dev_desc[i]);
+		}
+	}
+
+	return rc;
+}
+int sata_initialize(void) __attribute__((weak, alias("__sata_initialize")));
+
+__weak int __sata_stop(void)
+{
+	int i, err = 0;
+
+	for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++)
+		err |= reset_sata(i);
+
+	if (err)
+		printf("Could not reset some SATA devices\n");
+
+	return err;
+}
+int sata_stop(void) __attribute__((weak, alias("__sata_stop")));
+
+#ifdef CONFIG_BLK
+static const struct blk_ops sata_blk_ops = {
+	.read	= sata_bread,
+	.write	= sata_bwrite,
+};
+
+U_BOOT_DRIVER(sata_blk) = {
+	.name		= "sata_blk",
+	.id		= UCLASS_BLK,
+	.ops		= &sata_blk_ops,
+};
+#else
+U_BOOT_LEGACY_BLK(sata) = {
+	.if_typename	= "sata",
+	.if_type	= IF_TYPE_SATA,
+	.max_devs	= CONFIG_SYS_SATA_MAX_DEVICE,
+	.desc		= sata_dev_desc,
+};
+#endif
diff --git a/common/scsi.c b/common/scsi.c
new file mode 100644
index 0000000..8ac28dd
--- /dev/null
+++ b/common/scsi.c
@@ -0,0 +1,592 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <inttypes.h>
+#include <pci.h>
+#include <scsi.h>
+
+#ifdef CONFIG_SCSI_DEV_LIST
+#define SCSI_DEV_LIST CONFIG_SCSI_DEV_LIST
+#else
+#ifdef CONFIG_SCSI_SYM53C8XX
+#define SCSI_VEND_ID	0x1000
+#ifndef CONFIG_SCSI_DEV_ID
+#define SCSI_DEV_ID		0x0001
+#else
+#define SCSI_DEV_ID		CONFIG_SCSI_DEV_ID
+#endif
+#elif defined CONFIG_SATA_ULI5288
+
+#define SCSI_VEND_ID 0x10b9
+#define SCSI_DEV_ID  0x5288
+
+#elif !defined(CONFIG_SCSI_AHCI_PLAT)
+#error no scsi device defined
+#endif
+#define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
+#endif
+
+#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
+const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST };
+#endif
+static ccb tempccb;	/* temporary scsi command buffer */
+
+static unsigned char tempbuff[512]; /* temporary data buffer */
+
+static int scsi_max_devs; /* number of highest available scsi device */
+
+static int scsi_curr_dev; /* current device */
+
+static struct blk_desc scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
+
+/* almost the maximum amount of the scsi_ext command.. */
+#define SCSI_MAX_READ_BLK 0xFFFF
+#define SCSI_LBA48_READ	0xFFFFFFF
+
+#ifdef CONFIG_SYS_64BIT_LBA
+void scsi_setup_read16(ccb *pccb, lbaint_t start, unsigned long blocks)
+{
+	pccb->cmd[0] = SCSI_READ16;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = (unsigned char)(start >> 56) & 0xff;
+	pccb->cmd[3] = (unsigned char)(start >> 48) & 0xff;
+	pccb->cmd[4] = (unsigned char)(start >> 40) & 0xff;
+	pccb->cmd[5] = (unsigned char)(start >> 32) & 0xff;
+	pccb->cmd[6] = (unsigned char)(start >> 24) & 0xff;
+	pccb->cmd[7] = (unsigned char)(start >> 16) & 0xff;
+	pccb->cmd[8] = (unsigned char)(start >> 8) & 0xff;
+	pccb->cmd[9] = (unsigned char)start & 0xff;
+	pccb->cmd[10] = 0;
+	pccb->cmd[11] = (unsigned char)(blocks >> 24) & 0xff;
+	pccb->cmd[12] = (unsigned char)(blocks >> 16) & 0xff;
+	pccb->cmd[13] = (unsigned char)(blocks >> 8) & 0xff;
+	pccb->cmd[14] = (unsigned char)blocks & 0xff;
+	pccb->cmd[15] = 0;
+	pccb->cmdlen = 16;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+	debug("scsi_setup_read16: cmd: %02X %02X startblk %02X%02X%02X%02X%02X%02X%02X%02X blccnt %02X%02X%02X%02X\n",
+	      pccb->cmd[0], pccb->cmd[1],
+	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+	      pccb->cmd[6], pccb->cmd[7], pccb->cmd[8], pccb->cmd[9],
+	      pccb->cmd[11], pccb->cmd[12], pccb->cmd[13], pccb->cmd[14]);
+}
+#endif
+
+void scsi_setup_read_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
+{
+	pccb->cmd[0] = SCSI_READ10;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff;
+	pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff;
+	pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff;
+	pccb->cmd[5] = (unsigned char)start & 0xff;
+	pccb->cmd[6] = 0;
+	pccb->cmd[7] = (unsigned char)(blocks >> 8) & 0xff;
+	pccb->cmd[8] = (unsigned char)blocks & 0xff;
+	pccb->cmd[6] = 0;
+	pccb->cmdlen = 10;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+	debug("scsi_setup_read_ext: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
+	      pccb->cmd[0], pccb->cmd[1],
+	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+	      pccb->cmd[7], pccb->cmd[8]);
+}
+
+void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
+{
+	pccb->cmd[0] = SCSI_WRITE10;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff;
+	pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff;
+	pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff;
+	pccb->cmd[5] = (unsigned char)start & 0xff;
+	pccb->cmd[6] = 0;
+	pccb->cmd[7] = ((unsigned char)(blocks >> 8)) & 0xff;
+	pccb->cmd[8] = (unsigned char)blocks & 0xff;
+	pccb->cmd[9] = 0;
+	pccb->cmdlen = 10;
+	pccb->msgout[0] = SCSI_IDENTIFY;  /* NOT USED */
+	debug("%s: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
+	      __func__,
+	      pccb->cmd[0], pccb->cmd[1],
+	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+	      pccb->cmd[7], pccb->cmd[8]);
+}
+
+void scsi_setup_read6(ccb *pccb, lbaint_t start, unsigned short blocks)
+{
+	pccb->cmd[0] = SCSI_READ6;
+	pccb->cmd[1] = pccb->lun << 5 | ((unsigned char)(start >> 16) & 0x1f);
+	pccb->cmd[2] = (unsigned char)(start >> 8) & 0xff;
+	pccb->cmd[3] = (unsigned char)start & 0xff;
+	pccb->cmd[4] = (unsigned char)blocks & 0xff;
+	pccb->cmd[5] = 0;
+	pccb->cmdlen = 6;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+	debug("scsi_setup_read6: cmd: %02X %02X startblk %02X%02X blccnt %02X\n",
+	      pccb->cmd[0], pccb->cmd[1],
+	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4]);
+}
+
+
+void scsi_setup_inquiry(ccb *pccb)
+{
+	pccb->cmd[0] = SCSI_INQUIRY;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = 0;
+	pccb->cmd[3] = 0;
+	if (pccb->datalen > 255)
+		pccb->cmd[4] = 255;
+	else
+		pccb->cmd[4] = (unsigned char)pccb->datalen;
+	pccb->cmd[5] = 0;
+	pccb->cmdlen = 6;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+}
+
+#ifdef CONFIG_BLK
+static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+		       void *buffer)
+#else
+static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
+		       lbaint_t blkcnt, void *buffer)
+#endif
+{
+#ifdef CONFIG_BLK
+	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
+	int device = block_dev->devnum;
+	lbaint_t start, blks;
+	uintptr_t buf_addr;
+	unsigned short smallblks = 0;
+	ccb *pccb = (ccb *)&tempccb;
+	device &= 0xff;
+
+	/* Setup device */
+	pccb->target = scsi_dev_desc[device].target;
+	pccb->lun = scsi_dev_desc[device].lun;
+	buf_addr = (unsigned long)buffer;
+	start = blknr;
+	blks = blkcnt;
+	debug("\nscsi_read: dev %d startblk " LBAF
+	      ", blccnt " LBAF " buffer %lx\n",
+	      device, start, blks, (unsigned long)buffer);
+	do {
+		pccb->pdata = (unsigned char *)buf_addr;
+#ifdef CONFIG_SYS_64BIT_LBA
+		if (start > SCSI_LBA48_READ) {
+			unsigned long blocks;
+			blocks = min_t(lbaint_t, blks, SCSI_MAX_READ_BLK);
+			pccb->datalen = scsi_dev_desc[device].blksz * blocks;
+			scsi_setup_read16(pccb, start, blocks);
+			start += blocks;
+			blks -= blocks;
+		} else
+#endif
+		if (blks > SCSI_MAX_READ_BLK) {
+			pccb->datalen = scsi_dev_desc[device].blksz *
+				SCSI_MAX_READ_BLK;
+			smallblks = SCSI_MAX_READ_BLK;
+			scsi_setup_read_ext(pccb, start, smallblks);
+			start += SCSI_MAX_READ_BLK;
+			blks -= SCSI_MAX_READ_BLK;
+		} else {
+			pccb->datalen = scsi_dev_desc[device].blksz * blks;
+			smallblks = (unsigned short)blks;
+			scsi_setup_read_ext(pccb, start, smallblks);
+			start += blks;
+			blks = 0;
+		}
+		debug("scsi_read_ext: startblk " LBAF
+		      ", blccnt %x buffer %" PRIXPTR "\n",
+		      start, smallblks, buf_addr);
+		if (scsi_exec(pccb) != true) {
+			scsi_print_error(pccb);
+			blkcnt -= blks;
+			break;
+		}
+		buf_addr += pccb->datalen;
+	} while (blks != 0);
+	debug("scsi_read_ext: end startblk " LBAF
+	      ", blccnt %x buffer %" PRIXPTR "\n", start, smallblks, buf_addr);
+	return blkcnt;
+}
+
+/*******************************************************************************
+ * scsi_write
+ */
+
+/* Almost the maximum amount of the scsi_ext command.. */
+#define SCSI_MAX_WRITE_BLK 0xFFFF
+
+#ifdef CONFIG_BLK
+static ulong scsi_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+			const void *buffer)
+#else
+static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr,
+			lbaint_t blkcnt, const void *buffer)
+#endif
+{
+#ifdef CONFIG_BLK
+	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
+	int device = block_dev->devnum;
+	lbaint_t start, blks;
+	uintptr_t buf_addr;
+	unsigned short smallblks;
+	ccb *pccb = (ccb *)&tempccb;
+
+	device &= 0xff;
+
+	/* Setup device */
+	pccb->target = scsi_dev_desc[device].target;
+	pccb->lun = scsi_dev_desc[device].lun;
+	buf_addr = (unsigned long)buffer;
+	start = blknr;
+	blks = blkcnt;
+	debug("\n%s: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n",
+	      __func__, device, start, blks, (unsigned long)buffer);
+	do {
+		pccb->pdata = (unsigned char *)buf_addr;
+		if (blks > SCSI_MAX_WRITE_BLK) {
+			pccb->datalen = (scsi_dev_desc[device].blksz *
+					 SCSI_MAX_WRITE_BLK);
+			smallblks = SCSI_MAX_WRITE_BLK;
+			scsi_setup_write_ext(pccb, start, smallblks);
+			start += SCSI_MAX_WRITE_BLK;
+			blks -= SCSI_MAX_WRITE_BLK;
+		} else {
+			pccb->datalen = scsi_dev_desc[device].blksz * blks;
+			smallblks = (unsigned short)blks;
+			scsi_setup_write_ext(pccb, start, smallblks);
+			start += blks;
+			blks = 0;
+		}
+		debug("%s: startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
+		      __func__, start, smallblks, buf_addr);
+		if (scsi_exec(pccb) != true) {
+			scsi_print_error(pccb);
+			blkcnt -= blks;
+			break;
+		}
+		buf_addr += pccb->datalen;
+	} while (blks != 0);
+	debug("%s: end startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
+	      __func__, start, smallblks, buf_addr);
+	return blkcnt;
+}
+
+int scsi_get_disk_count(void)
+{
+	return scsi_max_devs;
+}
+
+#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
+void scsi_init(void)
+{
+	int busdevfunc = -1;
+	int i;
+	/*
+	 * Find a device from the list, this driver will support a single
+	 * controller.
+	 */
+	for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
+		/* get PCI Device ID */
+#ifdef CONFIG_DM_PCI
+		struct udevice *dev;
+		int ret;
+
+		ret = dm_pci_find_device(scsi_device_list[i].vendor,
+					 scsi_device_list[i].device, 0, &dev);
+		if (!ret) {
+			busdevfunc = dm_pci_get_bdf(dev);
+			break;
+		}
+#else
+		busdevfunc = pci_find_device(scsi_device_list[i].vendor,
+					     scsi_device_list[i].device,
+					     0);
+#endif
+		if (busdevfunc != -1)
+			break;
+	}
+
+	if (busdevfunc == -1) {
+		printf("Error: SCSI Controller(s) ");
+		for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
+			printf("%04X:%04X ",
+			       scsi_device_list[i].vendor,
+			       scsi_device_list[i].device);
+		}
+		printf("not found\n");
+		return;
+	}
+#ifdef DEBUG
+	else {
+		printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n",
+		       scsi_device_list[i].vendor,
+		       scsi_device_list[i].device,
+		       (busdevfunc >> 16) & 0xFF,
+		       (busdevfunc >> 11) & 0x1F,
+		       (busdevfunc >> 8) & 0x7);
+	}
+#endif
+	bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
+	scsi_low_level_init(busdevfunc);
+	scsi_scan(1);
+	bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);
+}
+#endif
+
+/* copy src to dest, skipping leading and trailing blanks
+ * and null terminate the string
+ */
+void scsi_ident_cpy(unsigned char *dest, unsigned char *src, unsigned int len)
+{
+	int start, end;
+
+	start = 0;
+	while (start < len) {
+		if (src[start] != ' ')
+			break;
+		start++;
+	}
+	end = len-1;
+	while (end > start) {
+		if (src[end] != ' ')
+			break;
+		end--;
+	}
+	for (; start <= end; start++)
+		*dest ++= src[start];
+	*dest = '\0';
+}
+
+
+/* Trim trailing blanks, and NUL-terminate string
+ */
+void scsi_trim_trail(unsigned char *str, unsigned int len)
+{
+	unsigned char *p = str + len - 1;
+
+	while (len-- > 0) {
+		*p-- = '\0';
+		if (*p != ' ')
+			return;
+	}
+}
+
+int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz)
+{
+	*capacity = 0;
+
+	memset(pccb->cmd, '\0', sizeof(pccb->cmd));
+	pccb->cmd[0] = SCSI_RD_CAPAC10;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmdlen = 10;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+
+	pccb->datalen = 8;
+	if (scsi_exec(pccb) != true)
+		return 1;
+
+	*capacity = ((lbaint_t)pccb->pdata[0] << 24) |
+		    ((lbaint_t)pccb->pdata[1] << 16) |
+		    ((lbaint_t)pccb->pdata[2] << 8)  |
+		    ((lbaint_t)pccb->pdata[3]);
+
+	if (*capacity != 0xffffffff) {
+		/* Read capacity (10) was sufficient for this drive. */
+		*blksz = ((unsigned long)pccb->pdata[4] << 24) |
+			 ((unsigned long)pccb->pdata[5] << 16) |
+			 ((unsigned long)pccb->pdata[6] << 8)  |
+			 ((unsigned long)pccb->pdata[7]);
+		return 0;
+	}
+
+	/* Read capacity (10) was insufficient. Use read capacity (16). */
+	memset(pccb->cmd, '\0', sizeof(pccb->cmd));
+	pccb->cmd[0] = SCSI_RD_CAPAC16;
+	pccb->cmd[1] = 0x10;
+	pccb->cmdlen = 16;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+
+	pccb->datalen = 16;
+	if (scsi_exec(pccb) != true)
+		return 1;
+
+	*capacity = ((uint64_t)pccb->pdata[0] << 56) |
+		    ((uint64_t)pccb->pdata[1] << 48) |
+		    ((uint64_t)pccb->pdata[2] << 40) |
+		    ((uint64_t)pccb->pdata[3] << 32) |
+		    ((uint64_t)pccb->pdata[4] << 24) |
+		    ((uint64_t)pccb->pdata[5] << 16) |
+		    ((uint64_t)pccb->pdata[6] << 8)  |
+		    ((uint64_t)pccb->pdata[7]);
+
+	*blksz = ((uint64_t)pccb->pdata[8]  << 56) |
+		 ((uint64_t)pccb->pdata[9]  << 48) |
+		 ((uint64_t)pccb->pdata[10] << 40) |
+		 ((uint64_t)pccb->pdata[11] << 32) |
+		 ((uint64_t)pccb->pdata[12] << 24) |
+		 ((uint64_t)pccb->pdata[13] << 16) |
+		 ((uint64_t)pccb->pdata[14] << 8)  |
+		 ((uint64_t)pccb->pdata[15]);
+
+	return 0;
+}
+
+
+/*
+ * Some setup (fill-in) routines
+ */
+void scsi_setup_test_unit_ready(ccb *pccb)
+{
+	pccb->cmd[0] = SCSI_TST_U_RDY;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = 0;
+	pccb->cmd[3] = 0;
+	pccb->cmd[4] = 0;
+	pccb->cmd[5] = 0;
+	pccb->cmdlen = 6;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+}
+
+/*
+ * (re)-scan the scsi bus and reports scsi device info
+ * to the user if mode = 1
+ */
+void scsi_scan(int mode)
+{
+	unsigned char i, perq, modi, lun;
+	lbaint_t capacity;
+	unsigned long blksz;
+	ccb *pccb = (ccb *)&tempccb;
+
+	if (mode == 1)
+		printf("scanning bus for devices...\n");
+	for (i = 0; i < CONFIG_SYS_SCSI_MAX_DEVICE; i++) {
+		scsi_dev_desc[i].target = 0xff;
+		scsi_dev_desc[i].lun = 0xff;
+		scsi_dev_desc[i].lba = 0;
+		scsi_dev_desc[i].blksz = 0;
+		scsi_dev_desc[i].log2blksz =
+			LOG2_INVALID(typeof(scsi_dev_desc[i].log2blksz));
+		scsi_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+		scsi_dev_desc[i].vendor[0] = 0;
+		scsi_dev_desc[i].product[0] = 0;
+		scsi_dev_desc[i].revision[0] = 0;
+		scsi_dev_desc[i].removable = false;
+		scsi_dev_desc[i].if_type = IF_TYPE_SCSI;
+		scsi_dev_desc[i].devnum = i;
+		scsi_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+#ifndef CONFIG_BLK
+		scsi_dev_desc[i].block_read = scsi_read;
+		scsi_dev_desc[i].block_write = scsi_write;
+#endif
+	}
+	scsi_max_devs = 0;
+	for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
+		pccb->target = i;
+		for (lun = 0; lun < CONFIG_SYS_SCSI_MAX_LUN; lun++) {
+			pccb->lun = lun;
+			pccb->pdata = (unsigned char *)&tempbuff;
+			pccb->datalen = 512;
+			scsi_setup_inquiry(pccb);
+			if (scsi_exec(pccb) != true) {
+				if (pccb->contr_stat == SCSI_SEL_TIME_OUT) {
+					/*
+					 * selection timeout => assuming no
+					 * device present
+					 */
+					debug("Selection timeout ID %d\n",
+					      pccb->target);
+					continue;
+				}
+				scsi_print_error(pccb);
+				continue;
+			}
+			perq = tempbuff[0];
+			modi = tempbuff[1];
+			if ((perq & 0x1f) == 0x1f)
+				continue; /* skip unknown devices */
+			if ((modi & 0x80) == 0x80) /* drive is removable */
+				scsi_dev_desc[scsi_max_devs].removable = true;
+			/* get info for this device */
+			scsi_ident_cpy((unsigned char *)&scsi_dev_desc
+						[scsi_max_devs].vendor[0],
+				       &tempbuff[8], 8);
+			scsi_ident_cpy((unsigned char *)&scsi_dev_desc
+						[scsi_max_devs].product[0],
+				       &tempbuff[16], 16);
+			scsi_ident_cpy((unsigned char *)&scsi_dev_desc
+						[scsi_max_devs].revision[0],
+				       &tempbuff[32], 4);
+			scsi_dev_desc[scsi_max_devs].target = pccb->target;
+			scsi_dev_desc[scsi_max_devs].lun = pccb->lun;
+
+			pccb->datalen = 0;
+			scsi_setup_test_unit_ready(pccb);
+			if (scsi_exec(pccb) != true) {
+				if (scsi_dev_desc[scsi_max_devs].removable) {
+					scsi_dev_desc[scsi_max_devs].type =
+							perq;
+					goto removable;
+				}
+				scsi_print_error(pccb);
+				continue;
+			}
+			if (scsi_read_capacity(pccb, &capacity, &blksz)) {
+				scsi_print_error(pccb);
+				continue;
+			}
+			scsi_dev_desc[scsi_max_devs].lba = capacity;
+			scsi_dev_desc[scsi_max_devs].blksz = blksz;
+			scsi_dev_desc[scsi_max_devs].log2blksz =
+				LOG2(scsi_dev_desc[scsi_max_devs].blksz);
+			scsi_dev_desc[scsi_max_devs].type = perq;
+			part_init(&scsi_dev_desc[scsi_max_devs]);
+removable:
+			if (mode == 1) {
+				printf("  Device %d: ", scsi_max_devs);
+				dev_print(&scsi_dev_desc[scsi_max_devs]);
+			} /* if mode */
+			scsi_max_devs++;
+		} /* next LUN */
+	}
+	if (scsi_max_devs > 0)
+		scsi_curr_dev = 0;
+	else
+		scsi_curr_dev = -1;
+
+	printf("Found %d device(s).\n", scsi_max_devs);
+#ifndef CONFIG_SPL_BUILD
+	setenv_ulong("scsidevs", scsi_max_devs);
+#endif
+}
+
+#ifdef CONFIG_BLK
+static const struct blk_ops scsi_blk_ops = {
+	.read	= scsi_read,
+	.write	= scsi_write,
+};
+
+U_BOOT_DRIVER(scsi_blk) = {
+	.name		= "scsi_blk",
+	.id		= UCLASS_BLK,
+	.ops		= &scsi_blk_ops,
+};
+#else
+U_BOOT_LEGACY_BLK(scsi) = {
+	.if_typename	= "sata",
+	.if_type	= IF_TYPE_SCSI,
+	.max_devs	= CONFIG_SYS_SCSI_MAX_DEVICE,
+	.desc		= scsi_dev_desc,
+};
+#endif
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 82e7f58..bdde716 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -64,6 +64,11 @@
 	/* Nothing to do! */
 }
 
+__weak void spl_board_prepare_for_boot(void)
+{
+	/* Nothing to do! */
+}
+
 void spl_set_header_raw_uboot(void)
 {
 	spl_image.size = CONFIG_SYS_MONITOR_LEN;
@@ -73,7 +78,7 @@
 	spl_image.name = "U-Boot";
 }
 
-void spl_parse_image_header(const struct image_header *header)
+int spl_parse_image_header(const struct image_header *header)
 {
 	u32 header_size = sizeof(struct image_header);
 
@@ -111,6 +116,9 @@
 		 * is bad, and thus should be skipped silently.
 		 */
 		panic("** no mkimage signature but raw image not supported");
+#elif defined(CONFIG_SPL_ABORT_ON_RAW_IMAGE)
+		/* Signature not found, proceed to other boot methods. */
+		return -EINVAL;
 #else
 		/* Signature not found - assume u-boot.bin */
 		debug("mkimage signature not found - ih_magic = %x\n",
@@ -118,6 +126,7 @@
 		spl_set_header_raw_uboot();
 #endif
 	}
+	return 0;
 }
 
 __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
@@ -131,20 +140,47 @@
 	image_entry();
 }
 
+#ifndef CONFIG_SPL_LOAD_FIT_ADDRESS
+# define CONFIG_SPL_LOAD_FIT_ADDRESS	0
+#endif
+
 #ifdef CONFIG_SPL_RAM_DEVICE
+static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
+			       ulong count, void *buf)
+{
+	debug("%s: sector %lx, count %lx, buf %lx\n",
+	      __func__, sector, count, (ulong)buf);
+	memcpy(buf, (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + sector), count);
+	return count;
+}
+
 static int spl_ram_load_image(void)
 {
-	const struct image_header *header;
+	struct image_header *header;
 
-	/*
-	 * Get the header.  It will point to an address defined by handoff
-	 * which will tell where the image located inside the flash. For
-	 * now, it will temporary fixed to address pointed by U-Boot.
-	 */
-	header = (struct image_header *)
-		(CONFIG_SYS_TEXT_BASE -	sizeof(struct image_header));
+	header = (struct image_header *)CONFIG_SPL_LOAD_FIT_ADDRESS;
 
-	spl_parse_image_header(header);
+	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	    image_get_magic(header) == FDT_MAGIC) {
+		struct spl_load_info load;
+
+		debug("Found FIT\n");
+		load.bl_len = 1;
+		load.read = spl_ram_load_read;
+		spl_load_simple_fit(&load, 0, header);
+	} else {
+		debug("Legacy image\n");
+		/*
+		 * Get the header.  It will point to an address defined by
+		 * handoff which will tell where the image located inside
+		 * the flash. For now, it will temporary fixed to address
+		 * pointed by U-Boot.
+		 */
+		header = (struct image_header *)
+			(CONFIG_SYS_TEXT_BASE -	sizeof(struct image_header));
+
+		spl_parse_image_header(header);
+	}
 
 	return 0;
 }
@@ -400,6 +436,7 @@
 #endif
 
 	debug("loaded - jumping to U-Boot...");
+	spl_board_prepare_for_boot();
 	jump_to_image_no_args(&spl_image);
 }
 
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index b77dbf4..ade5496 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -48,7 +48,11 @@
 		goto end;
 	}
 
-	spl_parse_image_header(header);
+	err = spl_parse_image_header(header);
+	if (err < 0) {
+		puts("spl: ext4fs_read failed\n");
+		goto end;
+	}
 
 	err = ext4fs_read((char *)spl_image.load_addr, filelen, &actlen);
 
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index d761b26..5b0d969 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -57,7 +57,9 @@
 	if (err <= 0)
 		goto end;
 
-	spl_parse_image_header(header);
+	err = spl_parse_image_header(header);
+	if (err)
+		goto end;
 
 	err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
 
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 1a5c027..26842ba 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -39,8 +39,13 @@
 	     node >= 0;
 	     node = fdt_next_subnode(fdt, node)) {
 		name = fdt_getprop(fdt, node, "description", &len);
-		if (!name)
+		if (!name) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+			printf("%s: Missing FDT description in DTB\n",
+			       __func__);
+#endif
 			return -EINVAL;
+		}
 		if (board_fit_config_name_match(name))
 			continue;
 
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 8d588d1..5676acd 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -23,8 +23,12 @@
 {
 	u32 image_size_sectors;
 	unsigned long count;
+	int ret;
 
-	spl_parse_image_header(header);
+	ret = spl_parse_image_header(header);
+	if (ret)
+		return ret;
+
 	/* convert size to sectors - round up */
 	image_size_sectors = (spl_image.size + mmc->read_bl_len - 1) /
 			     mmc->read_bl_len;
@@ -296,7 +300,7 @@
 			if (part == 7)
 				part = 0;
 
-			err = mmc_switch_part(0, part);
+			err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
 			if (err) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
 				puts("spl: mmc partition switch failed\n");
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 79388ff..bbd9546 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -32,7 +32,10 @@
 	if (err)
 		return err;
 
-	spl_parse_image_header(header);
+	err = spl_parse_image_header(header);
+	if (err)
+		return err;
+
 	return nand_spl_load_image(offset, spl_image.size,
 				   (void *)(unsigned long)spl_image.load_addr);
 }
@@ -77,7 +80,9 @@
 		/* load linux */
 		nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
 			sizeof(*header), (void *)header);
-		spl_parse_image_header(header);
+		err = spl_parse_image_header(header);
+		if (err)
+			return err;
 		if (header->ih_os == IH_OS_LINUX) {
 			/* happy - was a linux */
 			err = nand_spl_load_image(
diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c
index 63b20d8..ae71d26 100644
--- a/common/spl/spl_net.c
+++ b/common/spl/spl_net.c
@@ -34,7 +34,5 @@
 		printf("Problem booting with BOOTP\n");
 		return rv;
 	}
-	spl_parse_image_header((struct image_header *)load_addr);
-
-	return 0;
+	return spl_parse_image_header((struct image_header *)load_addr);
 }
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index d0bd0b0..da2422f 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -9,6 +9,7 @@
 
 int spl_nor_load_image(void)
 {
+	int ret;
 	/*
 	 * Loading of the payload to SDRAM is done with skipping of
 	 * the mkimage header in this SPL NOR driver
@@ -28,7 +29,9 @@
 		if (image_get_os(header) == IH_OS_LINUX) {
 			/* happy - was a Linux */
 
-			spl_parse_image_header(header);
+			ret = spl_parse_image_header(header);
+			if (ret)
+				return ret;
 
 			memcpy((void *)spl_image.load_addr,
 			       (void *)(CONFIG_SYS_OS_BASE +
@@ -56,8 +59,10 @@
 	 * Load real U-Boot from its location in NOR flash to its
 	 * defined location in SDRAM
 	 */
-	spl_parse_image_header(
+	ret = spl_parse_image_header(
 			(const struct image_header *)CONFIG_SYS_UBOOT_BASE);
+	if (ret)
+		return ret;
 
 	memcpy((void *)(unsigned long)spl_image.load_addr,
 	       (void *)(CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header)),
diff --git a/common/spl/spl_onenand.c b/common/spl/spl_onenand.c
index af7d82e..1a28a84 100644
--- a/common/spl/spl_onenand.c
+++ b/common/spl/spl_onenand.c
@@ -17,6 +17,7 @@
 int spl_onenand_load_image(void)
 {
 	struct image_header *header;
+	int ret;
 
 	debug("spl: onenand\n");
 
@@ -25,7 +26,9 @@
 	/* Load u-boot */
 	onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS,
 		CONFIG_SYS_ONENAND_PAGE_SIZE, (void *)header);
-	spl_parse_image_header(header);
+	ret = spl_parse_image_header(header);
+	if (ret)
+		return ret;
 	onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS,
 		spl_image.size, (void *)spl_image.load_addr);
 
diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c
index 1719946..9d8cc7c 100644
--- a/common/spl/spl_sata.c
+++ b/common/spl/spl_sata.c
@@ -34,7 +34,7 @@
 	} else {
 		/* try to recognize storage devices immediately */
 		scsi_scan(0);
-		stor_dev = scsi_get_dev(0);
+		stor_dev = blk_get_devnum_by_type(IF_TYPE_SCSI, 0);
 		if (!stor_dev)
 			return -ENODEV;
 	}
diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c
index c42848e..04fa667 100644
--- a/common/spl/spl_usb.c
+++ b/common/spl/spl_usb.c
@@ -39,7 +39,7 @@
 #ifdef CONFIG_USB_STORAGE
 	/* try to recognize storage devices immediately */
 	usb_stor_curr_dev = usb_stor_scan(1);
-	stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+	stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, usb_stor_curr_dev);
 	if (!stor_dev)
 		return -ENODEV;
 #endif
diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index 380d8dd..4f26ea5 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -40,8 +40,11 @@
 	if (!ret) {
 		while ((res =
 			xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
-			if (addr == 0)
-				spl_parse_image_header((struct image_header *)buf);
+			if (addr == 0) {
+				ret = spl_parse_image_header((struct image_header *)buf);
+				if (ret)
+					return ret;
+			}
 			store_addr = addr + spl_image.load_addr;
 			size += res;
 			addr += res;
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 9285c95..7e6e52d 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -136,23 +136,6 @@
 #endif
 void uhci_show_temp_int_td(void);
 
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *usb_stor_get_dev(int index)
-{
-#ifdef CONFIG_BLK
-	struct udevice *dev;
-	int ret;
-
-	ret = blk_get_device(IF_TYPE_USB, index, &dev);
-	if (ret)
-		return NULL;
-	return dev_get_uclass_platdata(dev);
-#else
-	return (index < usb_max_devs) ? &usb_dev_desc[index] : NULL;
-#endif
-}
-#endif
-
 static void usb_show_progress(void)
 {
 	debug(".");
@@ -217,7 +200,6 @@
 
 #ifdef CONFIG_BLK
 	struct us_data *data;
-	char dev_name[30], *str;
 	int ret;
 #else
 	int start;
@@ -240,14 +222,12 @@
 	for (lun = 0; lun <= max_lun; lun++) {
 		struct blk_desc *blkdev;
 		struct udevice *dev;
+		char str[10];
 
-		snprintf(dev_name, sizeof(dev_name), "%s.lun%d",
-			 udev->dev->name, lun);
-		str = strdup(dev_name);
-		if (!str)
-			return -ENOMEM;
-		ret = blk_create_device(udev->dev, "usb_storage_blk", str,
-				IF_TYPE_USB, usb_max_devs, 512, 0, &dev);
+		snprintf(str, sizeof(str), "lun%d", lun);
+		ret = blk_create_devicef(udev->dev, "usb_storage_blk", str,
+					 IF_TYPE_USB, usb_max_devs, 512, 0,
+					 &dev);
 		if (ret) {
 			debug("Cannot bind driver\n");
 			return ret;
@@ -1555,4 +1535,11 @@
 	.id		= UCLASS_BLK,
 	.ops		= &usb_storage_ops,
 };
+#else
+U_BOOT_LEGACY_BLK(usb) = {
+	.if_typename	= "usb",
+	.if_type	= IF_TYPE_USB,
+	.max_devs	= USB_MAX_STOR_DEV,
+	.desc		= usb_dev_desc,
+};
 #endif
diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index 03b02ac..f098fd3 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -47,3 +47,4 @@
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_DM_ETH=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index 48ec91f..8be0412 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -51,3 +51,4 @@
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_DM_ETH=y
diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig
new file mode 100644
index 0000000..7604e2e
--- /dev/null
+++ b/configs/ap121_defconfig
@@ -0,0 +1,47 @@
+CONFIG_MIPS=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ARCH_ATH79=y
+CONFIG_DEFAULT_DEVICE_TREE="ap121"
+CONFIG_SYS_PROMPT="ap121 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_AR933X_PINCTRL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_AR933X=y
+CONFIG_DEBUG_UART_BASE=0xb8020000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_AR933X_UART=y
+CONFIG_ATH79_SPI=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig
new file mode 100644
index 0000000..1aa6e5d
--- /dev/null
+++ b/configs/ap143_defconfig
@@ -0,0 +1,47 @@
+CONFIG_MIPS=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ARCH_ATH79=y
+CONFIG_TARGET_AP143=y
+CONFIG_DEFAULT_DEVICE_TREE="ap143"
+CONFIG_SYS_PROMPT="ap143 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_QCA953X_PINCTRL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xb8020000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_SYS_NS16550=y
+CONFIG_ATH79_SPI=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index 85af09e..07a6a18 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -18,6 +18,7 @@
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index aa9bf33..01a5143 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -18,6 +18,7 @@
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index ce1f519..9f1d7fb 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -9,6 +9,8 @@
 CONFIG_VGA_BIOS_ADDR=0xfffa0000
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 5186345..64fd7c9 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -8,6 +8,8 @@
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 7c6b692..8e086c5 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -8,8 +8,6 @@
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_FIT=y
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -24,7 +22,6 @@
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index a11dcd5..32ffce7 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -50,3 +50,4 @@
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_DM_ETH=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 17b1458..f8d3c3b8 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -4,10 +4,12 @@
 CONFIG_TARGET_GALILEO=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
@@ -30,6 +32,7 @@
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 9930d56..28b837d 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -8,6 +8,8 @@
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index cc49dc9..d46cd3b 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_PICO_IMX6UL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx6ul/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 53b1ff6..45bb3ec 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -20,6 +20,7 @@
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_QFW=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
diff --git a/configs/sama5d2_ptc_nandflash_defconfig b/configs/sama5d2_ptc_nandflash_defconfig
new file mode 100644
index 0000000..7425184
--- /dev/null
+++ b/configs/sama5d2_ptc_nandflash_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_PTC=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
diff --git a/configs/sama5d2_ptc_spiflash_defconfig b/configs/sama5d2_ptc_spiflash_defconfig
new file mode 100644
index 0000000..27fc394
--- /dev/null
+++ b/configs/sama5d2_ptc_spiflash_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_PTC=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index 7fd37d6..1880256 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -21,3 +21,4 @@
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index de4e6bc..de8f4d9 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -21,3 +21,4 @@
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index 189a3e9..1dabc5f 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -19,3 +19,4 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 16e3f22..458a486 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -19,3 +19,4 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 8d3c3cf..488d950 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -21,3 +21,4 @@
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 8e15286..12f28f2 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -21,3 +21,4 @@
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index ffbafae..42fcc1e 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -21,3 +21,4 @@
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 1ea5cda..3110269 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -22,3 +22,4 @@
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 5384917..3ea4bd7 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -22,3 +22,4 @@
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index b709cf6..dbec4ad 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -22,3 +22,4 @@
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 45128e9..f2a5844 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -22,3 +22,4 @@
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index 9c1c232..58186ce 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -22,3 +22,4 @@
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index 59eb4dd..ab23e95 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -22,3 +22,4 @@
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index afdf4a3..9e4a92d 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_MMC=y
 CONFIG_PCI=y
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
 CONFIG_I8042_KEYB=y
@@ -47,6 +48,7 @@
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_SOUND=y
+CONFIG_CMD_QFW=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
@@ -97,6 +99,7 @@
 CONFIG_SPL_PWRSEQ=y
 CONFIG_RESET=y
 CONFIG_DM_MMC=y
+CONFIG_SANDBOX_MMC=y
 CONFIG_SPI_FLASH_SANDBOX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
new file mode 100644
index 0000000..93167c2
--- /dev/null
+++ b/configs/sandbox_noblk_defconfig
@@ -0,0 +1,168 @@
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_PCI=y
+CONFIG_DEFAULT_DEVICE_TREE="sandbox"
+CONFIG_I8042_KEYB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_BOOTSTAGE_USER_COUNT=0x20
+CONFIG_BOOTSTAGE_FDT=y
+CONFIG_BOOTSTAGE_STASH=y
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
+CONFIG_CONSOLE_RECORD=y
+CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_LOOPW=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_DEMO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_SOUND=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_HOSTFILE=y
+CONFIG_NETCONSOLE=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_DEVRES=y
+CONFIG_DEBUG_DEVRES=y
+CONFIG_ADC=y
+CONFIG_ADC_SANDBOX=y
+CONFIG_CLK=y
+CONFIG_CPU=y
+CONFIG_DM_DEMO=y
+CONFIG_DM_DEMO_SIMPLE=y
+CONFIG_DM_DEMO_SHAPE=y
+CONFIG_PM8916_GPIO=y
+CONFIG_SANDBOX_GPIO=y
+CONFIG_DM_I2C_COMPAT=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_I2C_CROS_EC_LDO=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_SANDBOX=y
+CONFIG_I2C_MUX=y
+CONFIG_SPL_I2C_MUX=y
+CONFIG_I2C_ARB_GPIO_CHALLENGE=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_I2C=y
+CONFIG_CROS_EC_LPC=y
+CONFIG_CROS_EC_SANDBOX=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_PWRSEQ=y
+CONFIG_SPL_PWRSEQ=y
+CONFIG_RESET=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH_SANDBOX=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_SANDBOX=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_3036_PINCTRL=y
+CONFIG_PINCTRL_SANDBOX=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_ACT8846=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_PMIC_MAX77686=y
+CONFIG_PMIC_PM8916=y
+CONFIG_PMIC_RK808=y
+CONFIG_PMIC_S2MPS11=y
+CONFIG_DM_PMIC_SANDBOX=y
+CONFIG_PMIC_S5M8767=y
+CONFIG_PMIC_TPS65090=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_ACT8846=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_MAX77686=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR_S5M8767=y
+CONFIG_DM_REGULATOR_SANDBOX=y
+CONFIG_REGULATOR_TPS65090=y
+CONFIG_RAM=y
+CONFIG_REMOTEPROC_SANDBOX=y
+CONFIG_DM_RTC=y
+CONFIG_SANDBOX_SERIAL=y
+CONFIG_SOUND=y
+CONFIG_SOUND_SANDBOX=y
+CONFIG_SANDBOX_SPI=y
+CONFIG_SPMI=y
+CONFIG_SPMI_SANDBOX=y
+CONFIG_TIMER=y
+CONFIG_TIMER_EARLY=y
+CONFIG_SANDBOX_TIMER=y
+CONFIG_TPM_TIS_SANDBOX=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EMUL=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL=y
+CONFIG_DM_VIDEO=y
+CONFIG_CONSOLE_ROTATION=y
+CONFIG_CONSOLE_TRUETYPE=y
+CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
+CONFIG_VIDEO_SANDBOX_SDL=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_TPM=y
+CONFIG_LZ4=y
+CONFIG_ERRNO_STR=y
+CONFIG_UNIT_TEST=y
+CONFIG_UT_TIME=y
+CONFIG_UT_DM=y
+CONFIG_UT_ENV=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 9a7c091..a662e72 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -33,6 +33,7 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index ac81854..b2933f7 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -33,6 +33,7 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 405d9d4..f197b6d 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -32,6 +32,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 3615490..6624f9e 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -32,6 +32,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index bdc8e6b..c6414f8 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -33,6 +33,7 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index a17e9d0..b47a560 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -34,6 +34,7 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index c4b215a..aab4498 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -32,6 +32,7 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/spear300_defconfig b/configs/spear300_defconfig
index af2f544..db3b6ea 100644
--- a/configs/spear300_defconfig
+++ b/configs/spear300_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear300_nand_defconfig b/configs/spear300_nand_defconfig
index 6c53e1f..ea4e8d7 100644
--- a/configs/spear300_nand_defconfig
+++ b/configs/spear300_nand_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear300_usbtty_defconfig b/configs/spear300_usbtty_defconfig
index 6827701..a2b56f3 100644
--- a/configs/spear300_usbtty_defconfig
+++ b/configs/spear300_usbtty_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear300_usbtty_nand_defconfig b/configs/spear300_usbtty_nand_defconfig
index 477a226..1738489 100644
--- a/configs/spear300_usbtty_nand_defconfig
+++ b/configs/spear300_usbtty_nand_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_defconfig b/configs/spear310_defconfig
index 0991f8e..a6064a5 100644
--- a/configs/spear310_defconfig
+++ b/configs/spear310_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_nand_defconfig b/configs/spear310_nand_defconfig
index ef30a67..85944c6 100644
--- a/configs/spear310_nand_defconfig
+++ b/configs/spear310_nand_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_pnor_defconfig b/configs/spear310_pnor_defconfig
index 6cfe220..48efe3d 100644
--- a/configs/spear310_pnor_defconfig
+++ b/configs/spear310_pnor_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_usbtty_defconfig b/configs/spear310_usbtty_defconfig
index c0d8edf..8edbe0c 100644
--- a/configs/spear310_usbtty_defconfig
+++ b/configs/spear310_usbtty_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_usbtty_nand_defconfig b/configs/spear310_usbtty_nand_defconfig
index e9d14ce..b622f74 100644
--- a/configs/spear310_usbtty_nand_defconfig
+++ b/configs/spear310_usbtty_nand_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_usbtty_pnor_defconfig b/configs/spear310_usbtty_pnor_defconfig
index 2e46e64..241a72a 100644
--- a/configs/spear310_usbtty_pnor_defconfig
+++ b/configs/spear310_usbtty_pnor_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_defconfig b/configs/spear320_defconfig
index 8dba79a..49d7c04 100644
--- a/configs/spear320_defconfig
+++ b/configs/spear320_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_nand_defconfig b/configs/spear320_nand_defconfig
index 7f33c78..70b3025 100644
--- a/configs/spear320_nand_defconfig
+++ b/configs/spear320_nand_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_pnor_defconfig b/configs/spear320_pnor_defconfig
index f7d3725..5ced0e1 100644
--- a/configs/spear320_pnor_defconfig
+++ b/configs/spear320_pnor_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_usbtty_defconfig b/configs/spear320_usbtty_defconfig
index 9e41253..de75b17 100644
--- a/configs/spear320_usbtty_defconfig
+++ b/configs/spear320_usbtty_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_usbtty_nand_defconfig b/configs/spear320_usbtty_nand_defconfig
index e61c74e..2202d2e 100644
--- a/configs/spear320_usbtty_nand_defconfig
+++ b/configs/spear320_usbtty_nand_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_usbtty_pnor_defconfig b/configs/spear320_usbtty_pnor_defconfig
index 7410093..35bb036 100644
--- a/configs/spear320_usbtty_pnor_defconfig
+++ b/configs/spear320_usbtty_pnor_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig
index f0e041f..f540839 100644
--- a/configs/spear600_defconfig
+++ b/configs/spear600_defconfig
@@ -9,5 +9,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_nand_defconfig b/configs/spear600_nand_defconfig
index cc4067d..de416d9 100644
--- a/configs/spear600_nand_defconfig
+++ b/configs/spear600_nand_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig
index df21355..8b6e0d0 100644
--- a/configs/spear600_usbtty_defconfig
+++ b/configs/spear600_usbtty_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig
index 48140aa..e8b4b0a 100644
--- a/configs/spear600_usbtty_nand_defconfig
+++ b/configs/spear600_usbtty_nand_defconfig
@@ -6,5 +6,6 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig
new file mode 100644
index 0000000..b1af2f6
--- /dev/null
+++ b/configs/tplink_wdr4300_defconfig
@@ -0,0 +1,43 @@
+CONFIG_MIPS=y
+CONFIG_ARCH_ATH79=y
+CONFIG_BOARD_TPLINK_WDR4300=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_NET=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_ETH=y
+CONFIG_AG7XXX=y
+CONFIG_CLK=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_ATH79_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index 1a07b9d..ace620b 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -17,6 +17,7 @@
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index b185593..37b8052 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -40,12 +40,21 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_NAND_ARASAN=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index cc08b03..fa761e5 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -8,6 +8,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
@@ -30,6 +31,8 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
@@ -40,6 +43,11 @@
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 14d24a0..2811d4b 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -8,6 +8,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
@@ -29,6 +30,8 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_NAND_ARASAN=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index e1e11b7..3711084 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
@@ -25,6 +26,8 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 6f1cff8..46a5dd0 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
@@ -29,6 +30,8 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
@@ -38,6 +41,11 @@
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index a8982a0..96a2be1 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
@@ -29,6 +30,8 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
@@ -38,6 +41,11 @@
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 7c66247..d0b1ec9 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_microzed"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_MICROZED=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index b46ab44..3624424 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_picozed"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_PICOZED=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 052679a..e1b1fc9 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
 CONFIG_SPL=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 3539f05..63d32d9 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC706=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 6a4726c..6ccbb8c 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index 46dd6be..e6c646b 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 12f0e2c..a8cfeb8 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index 8c7efe5..f2d00ca 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 7976e07..7783eeb 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zed"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZED=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index cd222c5..9236c5e 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zybo"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZYBO=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/disk/part.c b/disk/part.c
index 543cab8..6a1c02d 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -21,35 +21,6 @@
 #define PRINTF(fmt,args...)
 #endif
 
-const struct block_drvr block_drvr[] = {
-#if defined(CONFIG_CMD_IDE)
-	{ .name = "ide", .get_dev = ide_get_dev, },
-#endif
-#if defined(CONFIG_CMD_SATA)
-	{.name = "sata", .get_dev = sata_get_dev, },
-#endif
-#if defined(CONFIG_CMD_SCSI)
-	{ .name = "scsi", .get_dev = scsi_get_dev, },
-#endif
-#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
-	{ .name = "usb", .get_dev = usb_stor_get_dev, },
-#endif
-#if defined(CONFIG_MMC)
-	{
-		.name = "mmc",
-		.get_dev = mmc_get_dev,
-		.select_hwpart = mmc_select_hwpart,
-	},
-#endif
-#if defined(CONFIG_SYSTEMACE)
-	{ .name = "ace", .get_dev = systemace_get_dev, },
-#endif
-#if defined(CONFIG_SANDBOX)
-	{ .name = "host", .get_dev = host_get_dev, },
-#endif
-	{ },
-};
-
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef HAVE_BLOCK_DEVICE
@@ -71,45 +42,23 @@
 
 static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
 {
-	const struct block_drvr *drvr = block_drvr;
-	struct blk_desc* (*reloc_get_dev)(int dev);
-	int (*select_hwpart)(int dev_num, int hwpart);
-	char *name;
+	struct blk_desc *dev_desc;
 	int ret;
 
-	if (!ifname)
+	dev_desc = blk_get_devnum_by_typename(ifname, dev);
+	if (!dev_desc) {
+		debug("%s: No device for iface '%s', dev %d\n", __func__,
+		      ifname, dev);
 		return NULL;
-
-	name = drvr->name;
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-	name += gd->reloc_off;
-#endif
-	while (drvr->name) {
-		name = drvr->name;
-		reloc_get_dev = drvr->get_dev;
-		select_hwpart = drvr->select_hwpart;
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-		name += gd->reloc_off;
-		reloc_get_dev += gd->reloc_off;
-		if (select_hwpart)
-			select_hwpart += gd->reloc_off;
-#endif
-		if (strncmp(ifname, name, strlen(name)) == 0) {
-			struct blk_desc *dev_desc = reloc_get_dev(dev);
-			if (!dev_desc)
-				return NULL;
-			if (hwpart == 0 && !select_hwpart)
-				return dev_desc;
-			if (!select_hwpart)
-				return NULL;
-			ret = select_hwpart(dev_desc->devnum, hwpart);
-			if (ret < 0)
-				return NULL;
-			return dev_desc;
-		}
-		drvr++;
 	}
-	return NULL;
+	ret = blk_dselect_hwpart(dev_desc, hwpart);
+	if (ret) {
+		debug("%s: Failed to select h/w partition: err-%d\n", __func__,
+		      ret);
+		return NULL;
+	}
+
+	return dev_desc;
 }
 
 struct blk_desc *blk_get_dev(const char *ifname, int dev)
@@ -401,7 +350,7 @@
 	if (*ep) {
 		printf("** Bad device specification %s %s **\n",
 		       ifname, dev_str);
-		dev = -1;
+		dev = -EINVAL;
 		goto cleanup;
 	}
 
@@ -410,7 +359,7 @@
 		if (*ep) {
 			printf("** Bad HW partition specification %s %s **\n",
 			    ifname, hwpart_str);
-			dev = -1;
+			dev = -EINVAL;
 			goto cleanup;
 		}
 	}
@@ -418,7 +367,7 @@
 	*dev_desc = get_dev_hwpart(ifname, dev, hwpart);
 	if (!(*dev_desc) || ((*dev_desc)->type == DEV_TYPE_UNKNOWN)) {
 		printf("** Bad device %s %s **\n", ifname, dev_hwpart_str);
-		dev = -1;
+		dev = -ENOENT;
 		goto cleanup;
 	}
 
diff --git a/doc/README.x86 b/doc/README.x86
index c5c3010..4d50feb 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -23,7 +23,8 @@
 'bare metal', U-Boot acts like a BIOS replacement. The following platforms
 are supported:
 
-   - Bayley Bay
+   - Bayley Bay CRB
+   - Congatec QEVAL 2.0 & conga-QA3/E3845
    - Cougar Canyon 2 CRB
    - Crown Bay CRB
    - Galileo
@@ -303,12 +304,12 @@
 000000   descriptor.bin      Hard-coded to 0 in ifdtool
 001000   me.bin              Set by the descriptor
 500000   <spare>
+6ef000   Environment         CONFIG_ENV_OFFSET
 6f0000   MRC cache           CONFIG_ENABLE_MRC_CACHE
 700000   u-boot-dtb.bin      CONFIG_SYS_TEXT_BASE
 790000   vga.bin             CONFIG_VGA_BIOS_ADDR
 7c0000   fsp.bin             CONFIG_FSP_ADDR
 7f8000   <spare>             (depends on size of fsp.bin)
-7fe000   Environment         CONFIG_ENV_OFFSET
 7ff800   U-Boot 16-bit boot  CONFIG_SYS_X86_START16
 
 Overall ROM image size is controlled by CONFIG_ROM_SIZE.
@@ -412,18 +413,19 @@
 Multicore is also supported by QEMU via '-smp n' where n is the number of cores
 to instantiate. Note, the maximum supported CPU number in QEMU is 255.
 
-The fw_cfg interface in QEMU also provides information about kernel data, initrd,
-command-line arguments and more. U-Boot supports directly accessing these informtion
-from fw_cfg interface, this saves the time of loading them from hard disk or
-network again, through emulated devices. To use it , simply providing them in
-QEMU command line:
+The fw_cfg interface in QEMU also provides information about kernel data,
+initrd, command-line arguments and more. U-Boot supports directly accessing
+these informtion from fw_cfg interface, which saves the time of loading them
+from hard disk or network again, through emulated devices. To use it , simply
+providing them in QEMU command line:
 
 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 -kernel /path/to/bzImage
     -append 'root=/dev/ram console=ttyS0' -initrd /path/to/initrd -smp 8
 
 Note: -initrd and -smp are both optional
 
-Then start QEMU, in U-Boot command line use the following U-Boot command to setup kernel:
+Then start QEMU, in U-Boot command line use the following U-Boot command to
+setup kernel:
 
  => qfw
 qfw - QEMU firmware interface
@@ -437,8 +439,8 @@
 => qfw load
 loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
 
-Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then, 'zboot'
-can be used to boot the kernel:
+Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
+'zboot' can be used to boot the kernel:
 
 => zboot 02000000 - 04000000 1b1ab50
 
@@ -490,8 +492,8 @@
 --------------
 As an example of how to set up your boot flow with U-Boot, here are
 instructions for starting Ubuntu from U-Boot. These instructions have been
-tested on Minnowboard MAX with a SATA driver but are equally applicable on
-other platforms and other media. There are really only four steps and its a
+tested on Minnowboard MAX with a SATA drive but are equally applicable on
+other platforms and other media. There are really only four steps and it's a
 very simple script, but a more detailed explanation is provided here for
 completeness.
 
@@ -499,7 +501,7 @@
 It could also use the grub.cfg file (/efi/ubuntu/grub.cfg) to obtain the
 GUID. If you figure these out, please post patches to this README.
 
-Firstly, you will need Ubunutu installed on an available disk. It should be
+Firstly, you will need Ubuntu installed on an available disk. It should be
 possible to make U-Boot start a USB start-up disk but for now let's assume
 that you used another boot loader to install Ubuntu.
 
@@ -659,7 +661,7 @@
    Loading bzImage at address 100000 (5805728 bytes)
    Magic signature found
    Initial RAM disk at linear address 0x04000000, size 19215259 bytes
-   Kernel command line: "console=ttyS0,115200 root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
+   Kernel command line: "root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
 
    Starting kernel ...
 
@@ -679,13 +681,14 @@
                   240,329  ahci
                 1,422,704  vesa display
 
-Now the kernel actually starts:
+Now the kernel actually starts: (if you want to examine kernel boot up message
+on the serial console, append "console=ttyS0,115200" to the kernel command line)
 
    [    0.000000] Initializing cgroup subsys cpuset
    [    0.000000] Initializing cgroup subsys cpu
    [    0.000000] Initializing cgroup subsys cpuacct
    [    0.000000] Linux version 3.13.0-58-generic (buildd@allspice) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015 (Ubuntu 3.13.0-58.97-generic 3.13.11-ckt22)
-   [    0.000000] Command line: console=ttyS0,115200 root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro
+   [    0.000000] Command line: root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro console=ttyS0,115200
 
 It continues for a long time. Along the way you will see it pick up your
 ramdisk:
@@ -736,14 +739,6 @@
 The \ is to tell the shell not to evaluate ${filesize} as part of the setenv
 command.
 
-You will also need to add this to your board configuration file, e.g.
-include/configs/minnowmax.h:
-
-   #define CONFIG_BOOTDELAY	2
-
-Now when you reset your board it wait a few seconds (in case you want to
-interrupt) and then should boot straight into Ubuntu.
-
 You can also bake this behaviour into your build by hard-coding the
 environment variables if you add this to minnowmax.h:
 
@@ -812,6 +807,30 @@
 This is also tested on Intel Crown Bay board with a PCIe graphics card, booting
 SeaBIOS then chain-loading a GRUB on a USB drive, then Linux kernel finally.
 
+If you are using Intel Integrated Graphics Device (IGD) as the primary display
+device on your board, SeaBIOS needs to be patched manually to get its VGA ROM
+loaded and run by SeaBIOS. SeaBIOS locates VGA ROM via the PCI expansion ROM
+register, but IGD device does not have its VGA ROM mapped by this register.
+Its VGA ROM is packaged as part of u-boot.rom at a configurable flash address
+which is unknown to SeaBIOS. An example patch is needed for SeaBIOS below:
+
+diff --git a/src/optionroms.c b/src/optionroms.c
+index 65f7fe0..c7b6f5e 100644
+--- a/src/optionroms.c
++++ b/src/optionroms.c
+@@ -324,6 +324,8 @@ init_pcirom(struct pci_device *pci, int isvga, u64 *sources)
+         rom = deploy_romfile(file);
+     else if (RunPCIroms > 1 || (RunPCIroms == 1 && isvga))
+         rom = map_pcirom(pci);
++    if (pci->bdf == pci_to_bdf(0, 2, 0))
++        rom = (struct rom_header *)0xfff90000;
+     if (! rom)
+         // No ROM present.
+         return;
+
+Note: the patch above expects IGD device is at PCI b.d.f 0.2.0 and its VGA ROM
+is at 0xfff90000 which corresponds to CONFIG_VGA_BIOS_ADDR on Minnowboard MAX.
+Change these two accordingly if this is not the case on your board.
 
 Development Flow
 ----------------
@@ -963,12 +982,62 @@
 to U-Boot. This should go at the top of each file and list the coreboot
 filename where the code originated.
 
+Debugging ACPI issues with Windows:
+
+Windows might cache system information and only detect ACPI changes if you
+modify the ACPI table versions. So tweak them liberally when debugging ACPI
+issues with Windows.
+
+ACPI Support Status
+-------------------
+Advanced Configuration and Power Interface (ACPI) [16] aims to establish
+industry-standard interfaces enabling OS-directed configuration, power
+management, and thermal management of mobile, desktop, and server platforms.
+
+Linux can boot without ACPI with "acpi=off" command line parameter, but
+with ACPI the kernel gains the capabilities to handle power management.
+For Windows, ACPI is a must-have firmware feature since Windows Vista.
+CONFIG_GENERATE_ACPI_TABLE is the config option to turn on ACPI support in
+U-Boot. This requires Intel ACPI compiler to be installed on your host to
+compile ACPI DSDT table written in ASL format to AML format. You can get
+the compiler via "apt-get install iasl" if you are on Ubuntu or download
+the source from [17] to compile one by yourself.
+
+Current ACPI support in U-Boot is not complete. More features will be added
+in the future. The status as of today is:
+
+ * Support generating RSDT, XSDT, FACS, FADT, MADT, MCFG tables.
+ * Support one static DSDT table only, compiled by Intel ACPI compiler.
+ * Support S0/S5, reboot and shutdown from OS.
+ * Support booting a pre-installed Ubuntu distribution via 'zboot' command.
+ * Support installing and booting Ubuntu 14.04 (or above) from U-Boot with
+   the help of SeaBIOS using legacy interface (non-UEFI mode).
+ * Support installing and booting Windows 8.1/10 from U-Boot with the help
+   of SeaBIOS using legacy interface (non-UEFI mode).
+ * Support ACPI interrupts with SCI only.
+
+Features not supported so far (to make it a complete ACPI solution):
+ * S3 (Suspend to RAM), S4 (Suspend to Disk).
+
+Features that are optional:
+ * ACPI global NVS support. We may need it to simplify ASL code logic if
+   utilizing NVS variables. Most likely we will need this sooner or later.
+ * Dynamic AML bytecodes insertion at run-time. We may need this to support
+   SSDT table generation and DSDT fix up.
+ * SMI support. Since U-Boot is a modern bootloader, we don't want to bring
+   those legacy stuff into U-Boot. ACPI spec allows a system that does not
+   support SMI (a legacy-free system).
+
+So far ACPI is enabled on BayTrail based boards. Testing was done by booting
+a pre-installed Ubuntu 14.04 from a SATA drive. Installing Ubuntu 14.04 and
+Windows 8.1/10 to a SATA drive and booting from there is also tested. Most
+devices seem to work correctly and the board can respond a reboot/shutdown
+command from the OS.
 
 TODO List
 ---------
 - Audio
 - Chrome OS verified boot
-- SMI and ACPI support, to provide platform info and facilities to Linux
 
 References
 ----------
@@ -987,3 +1056,5 @@
 [13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
 [14] http://www.seabios.org/SeaBIOS
 [15] doc/device-tree-bindings/misc/intel,irq-router.txt
+[16] http://www.acpi.info
+[17] https://www.acpica.org/downloads
diff --git a/doc/device-tree-bindings/misc/intel,irq-router.txt b/doc/device-tree-bindings/misc/intel,irq-router.txt
index e4d8ead..04ad346 100644
--- a/doc/device-tree-bindings/misc/intel,irq-router.txt
+++ b/doc/device-tree-bindings/misc/intel,irq-router.txt
@@ -14,6 +14,11 @@
       "ibase": IRQ routing is in the memory-mapped IBASE register block
 - intel,ibase-offset : IBASE register offset in the interrupt router's PCI
     configuration space, required only if intel,pirq-config = "ibase".
+- intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must
+    be specified. The 8-bit ACTL register is seen on ICH series chipset, like
+    ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register.
+- intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either
+    in the interrupt router's PCI configuration space, or IBASE.
 - intel,pirq-link : Specifies the PIRQ link information with two cells. The
     first cell is the register offset that controls the first PIRQ link routing.
     The second cell is the total number of PIRQ links the router supports.
diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt
new file mode 100644
index 0000000..cb77fdf
--- /dev/null
+++ b/doc/device-tree-bindings/net/ti,dp83867.txt
@@ -0,0 +1,25 @@
+* Texas Instruments - dp83867 Giga bit ethernet phy
+
+Required properties:
+	- reg - The ID number for the phy, usually a small integer
+	- ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
+		for applicable values
+	- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
+		for applicable values
+	- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
+		for applicable values
+
+Default child nodes are standard Ethernet PHY device
+nodes as described in doc/devicetree/bindings/net/ethernet.txt
+
+Example:
+
+	ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+	};
+
+Datasheet can be found:
+http://www.ti.com/product/DP83867IR/datasheet
diff --git a/doc/device-tree-bindings/serial/qca,ar9330-uart.txt b/doc/device-tree-bindings/serial/qca,ar9330-uart.txt
new file mode 100644
index 0000000..ec576a1
--- /dev/null
+++ b/doc/device-tree-bindings/serial/qca,ar9330-uart.txt
@@ -0,0 +1,24 @@
+* Qualcomm Atheros AR9330 High-Speed UART
+
+Required properties:
+
+- compatible: Must be "qca,ar9330-uart"
+
+- reg: Specifies the physical base address of the controller and
+  the length of the memory mapped region.
+
+Additional requirements:
+
+  Each UART port must have an alias correctly numbered in "aliases"
+  node.
+
+Example:
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	uart0: uart@18020000 {
+		compatible = "qca,ar9330-uart";
+		reg = <0x18020000 0x14>;
+	};
diff --git a/doc/device-tree-bindings/spi/spi-ath79.txt b/doc/device-tree-bindings/spi/spi-ath79.txt
new file mode 100644
index 0000000..3fd9d67
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-ath79.txt
@@ -0,0 +1,19 @@
+Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
+
+Required properties:
+- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
+- reg: Base address and size of the controllers memory area
+- #address-cells: <1>, as required by generic SPI binding.
+- #size-cells: <0>, also as required by generic SPI binding.
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+	spi@1f000000 {
+		compatible = "qca,ar9132-spi", "qca,ar7100-spi";
+		reg = <0x1f000000 0x10>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
diff --git a/doc/uImage.FIT/multi-with-fpga.its b/doc/uImage.FIT/multi-with-fpga.its
new file mode 100644
index 0000000..0cdb31f
--- /dev/null
+++ b/doc/uImage.FIT/multi-with-fpga.its
@@ -0,0 +1,67 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ * This example makes use of the 'loadables' field
+ */
+
+/dts-v1/;
+
+/ {
+	description = "Configuration to load fpga before Kernel";
+	#address-cells = <1>;
+
+	images {
+		fdt@1 {
+			description = "zc706";
+			data = /incbin/("/tftpboot/devicetree.dtb");
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+			load = <0x10000000>;
+			hash@1 {
+				algo = "md5";
+			};
+		};
+
+		fpga@1 {
+			description = "FPGA";
+			data = /incbin/("/tftpboot/download.bit");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+			load = <0x30000000>;
+			hash@1 {
+				algo = "md5";
+			};
+		};
+
+		linux_kernel@1 {
+			description = "Linux";
+			data = /incbin/("/tftpboot/zImage");
+			type = "kernel";
+			arch = "arm";
+			os = "linux";
+			compression = "none";
+			load = <0x8000>;
+			entry = <0x8000>;
+			hash@1 {
+				algo = "md5";
+			};
+		};
+	};
+
+	configurations {
+		default = "config@2";
+		config@1 {
+			description = "Linux";
+			kernel = "linux_kernel@1";
+			fdt = "fdt@1";
+		};
+
+		config@2 {
+			description = "Linux with fpga";
+			kernel = "linux_kernel@1";
+			fdt = "fdt@1";
+			fpga = "fpga@1";
+		};
+	};
+};
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index 9c527c3..3f54180 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -236,6 +236,7 @@
   |- kernel = "kernel sub-node unit name"
   |- ramdisk = "ramdisk sub-node unit name"
   |- fdt = "fdt sub-node unit-name"
+  |- fpga = "fpga sub-node unit-name"
   |- loadables = "loadables sub-node unit-name"
 
 
@@ -251,6 +252,8 @@
     "fdt type").
   - setup : Unit name of the corresponding setup binary (used for booting
     an x86 kernel). This contains the setup.bin file built by the kernel.
+  - fpga : Unit name of the corresponding fpga bitstream blob
+    (component image node of a "fpga type").
   - loadables : Unit name containing a list of additional binaries to be
     loaded at their given locations.  "loadables" is a comma-separated list
     of strings. U-Boot will load each binary at its given start-address.
diff --git a/drivers/Makefile b/drivers/Makefile
index 6900097..99dd07f 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -36,6 +36,8 @@
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/
 obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
 obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
+obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
+obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
 
 else
 
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index fcc9ccd..80eea84 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -9,10 +9,9 @@
 	  be partitioned into several areas, called 'partitions' in U-Boot.
 	  A filesystem can be placed in each partition.
 
-config DISK
-	bool "Support disk controllers with driver model"
+config AHCI
+	bool "Support SATA controllers with driver model"
 	depends on DM
-	default y if DM
 	help
 	  This enables a uclass for disk controllers in U-Boot. Various driver
 	  types can use this, such as AHCI/SATA. It does not provide any standard
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index a43492f..436b79f 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -7,7 +7,11 @@
 
 obj-$(CONFIG_BLK) += blk-uclass.o
 
-obj-$(CONFIG_DISK) += disk-uclass.o
+ifndef CONFIG_BLK
+obj-y += blk_legacy.o
+endif
+
+obj-$(CONFIG_AHCI) += ahci-uclass.o
 obj-$(CONFIG_SCSI_AHCI) += ahci.o
 obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
 obj-$(CONFIG_FSL_SATA) += fsl_sata.o
@@ -22,7 +26,7 @@
 obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
 obj-$(CONFIG_SATA_SIL) += sata_sil.o
 obj-$(CONFIG_IDE_SIL680) += sil680.o
-obj-$(CONFIG_SANDBOX) += sandbox.o
+obj-$(CONFIG_SANDBOX) += sandbox.o sandbox_scsi.o sata_sandbox.o
 obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
 obj-$(CONFIG_SYSTEMACE) += systemace.o
 obj-$(CONFIG_BLOCK_CACHE) += blkcache.o
diff --git a/drivers/block/disk-uclass.c b/drivers/block/ahci-uclass.c
similarity index 72%
rename from drivers/block/disk-uclass.c
rename to drivers/block/ahci-uclass.c
index d665b35..7b8c326 100644
--- a/drivers/block/disk-uclass.c
+++ b/drivers/block/ahci-uclass.c
@@ -8,7 +8,7 @@
 #include <common.h>
 #include <dm.h>
 
-UCLASS_DRIVER(disk) = {
-	.id		= UCLASS_DISK,
-	.name		= "disk",
+UCLASS_DRIVER(ahci) = {
+	.id		= UCLASS_AHCI,
+	.name		= "ahci",
 };
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index 617db22..6ba1026 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -11,6 +11,315 @@
 #include <dm/device-internal.h>
 #include <dm/lists.h>
 
+static const char *if_typename_str[IF_TYPE_COUNT] = {
+	[IF_TYPE_IDE]		= "ide",
+	[IF_TYPE_SCSI]		= "scsi",
+	[IF_TYPE_ATAPI]		= "atapi",
+	[IF_TYPE_USB]		= "usb",
+	[IF_TYPE_DOC]		= "doc",
+	[IF_TYPE_MMC]		= "mmc",
+	[IF_TYPE_SD]		= "sd",
+	[IF_TYPE_SATA]		= "sata",
+	[IF_TYPE_HOST]		= "host",
+	[IF_TYPE_SYSTEMACE]	= "ace",
+};
+
+static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = {
+	[IF_TYPE_IDE]		= UCLASS_INVALID,
+	[IF_TYPE_SCSI]		= UCLASS_INVALID,
+	[IF_TYPE_ATAPI]		= UCLASS_INVALID,
+	[IF_TYPE_USB]		= UCLASS_MASS_STORAGE,
+	[IF_TYPE_DOC]		= UCLASS_INVALID,
+	[IF_TYPE_MMC]		= UCLASS_MMC,
+	[IF_TYPE_SD]		= UCLASS_INVALID,
+	[IF_TYPE_SATA]		= UCLASS_AHCI,
+	[IF_TYPE_HOST]		= UCLASS_ROOT,
+	[IF_TYPE_SYSTEMACE]	= UCLASS_INVALID,
+};
+
+static enum if_type if_typename_to_iftype(const char *if_typename)
+{
+	int i;
+
+	for (i = 0; i < IF_TYPE_COUNT; i++) {
+		if (if_typename_str[i] &&
+		    !strcmp(if_typename, if_typename_str[i]))
+			return i;
+	}
+
+	return IF_TYPE_UNKNOWN;
+}
+
+static enum uclass_id if_type_to_uclass_id(enum if_type if_type)
+{
+	return if_type_uclass_id[if_type];
+}
+
+struct blk_desc *blk_get_devnum_by_type(enum if_type if_type, int devnum)
+{
+	struct blk_desc *desc;
+	struct udevice *dev;
+	int ret;
+
+	ret = blk_get_device(if_type, devnum, &dev);
+	if (ret)
+		return NULL;
+	desc = dev_get_uclass_platdata(dev);
+
+	return desc;
+}
+
+/*
+ * This function is complicated with driver model. We look up the interface
+ * name in a local table. This gives us an interface type which we can match
+ * against the uclass of the block device's parent.
+ */
+struct blk_desc *blk_get_devnum_by_typename(const char *if_typename, int devnum)
+{
+	enum uclass_id uclass_id;
+	enum if_type if_type;
+	struct udevice *dev;
+	struct uclass *uc;
+	int ret;
+
+	if_type = if_typename_to_iftype(if_typename);
+	if (if_type == IF_TYPE_UNKNOWN) {
+		debug("%s: Unknown interface type '%s'\n", __func__,
+		      if_typename);
+		return NULL;
+	}
+	uclass_id = if_type_to_uclass_id(if_type);
+	if (uclass_id == UCLASS_INVALID) {
+		debug("%s: Unknown uclass for interface type'\n",
+		      if_typename_str[if_type]);
+		return NULL;
+	}
+
+	ret = uclass_get(UCLASS_BLK, &uc);
+	if (ret)
+		return NULL;
+	uclass_foreach_dev(dev, uc) {
+		struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+		debug("%s: if_type=%d, devnum=%d: %s, %d, %d\n", __func__,
+		      if_type, devnum, dev->name, desc->if_type, desc->devnum);
+		if (desc->devnum != devnum)
+			continue;
+
+		/* Find out the parent device uclass */
+		if (device_get_uclass_id(dev->parent) != uclass_id) {
+			debug("%s: parent uclass %d, this dev %d\n", __func__,
+			      device_get_uclass_id(dev->parent), uclass_id);
+			continue;
+		}
+
+		if (device_probe(dev))
+			return NULL;
+
+		debug("%s: Device desc %p\n", __func__, desc);
+		return desc;
+	}
+	debug("%s: No device found\n", __func__);
+
+	return NULL;
+}
+
+/**
+ * get_desc() - Get the block device descriptor for the given device number
+ *
+ * @if_type:	Interface type
+ * @devnum:	Device number (0 = first)
+ * @descp:	Returns block device descriptor on success
+ * @return 0 on success, -ENODEV if there is no such device and no device
+ * with a higher device number, -ENOENT if there is no such device but there
+ * is one with a higher number, or other -ve on other error.
+ */
+static int get_desc(enum if_type if_type, int devnum, struct blk_desc **descp)
+{
+	bool found_more = false;
+	struct udevice *dev;
+	struct uclass *uc;
+	int ret;
+
+	*descp = NULL;
+	ret = uclass_get(UCLASS_BLK, &uc);
+	if (ret)
+		return ret;
+	uclass_foreach_dev(dev, uc) {
+		struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+		debug("%s: if_type=%d, devnum=%d: %s, %d, %d\n", __func__,
+		      if_type, devnum, dev->name, desc->if_type, desc->devnum);
+		if (desc->if_type == if_type) {
+			if (desc->devnum == devnum) {
+				ret = device_probe(dev);
+				if (ret)
+					return ret;
+
+			} else if (desc->devnum > devnum) {
+				found_more = true;
+			}
+		}
+	}
+
+	return found_more ? -ENOENT : -ENODEV;
+}
+
+int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = blk_get_device(if_type, devnum, &dev);
+	if (ret)
+		return ret;
+
+	return blk_select_hwpart(dev, hwpart);
+}
+
+int blk_list_part(enum if_type if_type)
+{
+	struct blk_desc *desc;
+	int devnum, ok;
+	int ret;
+
+	for (ok = 0, devnum = 0;; ++devnum) {
+		ret = get_desc(if_type, devnum, &desc);
+		if (ret == -ENODEV)
+			break;
+		else if (ret)
+			continue;
+		if (desc->part_type != PART_TYPE_UNKNOWN) {
+			++ok;
+			if (devnum)
+				putc('\n');
+			part_print(desc);
+		}
+	}
+	if (!ok)
+		return -ENODEV;
+
+	return 0;
+}
+
+int blk_print_part_devnum(enum if_type if_type, int devnum)
+{
+	struct blk_desc *desc;
+	int ret;
+
+	ret = get_desc(if_type, devnum, &desc);
+	if (ret)
+		return ret;
+	if (desc->type == DEV_TYPE_UNKNOWN)
+		return -ENOENT;
+	part_print(desc);
+
+	return 0;
+}
+
+void blk_list_devices(enum if_type if_type)
+{
+	struct blk_desc *desc;
+	int ret;
+	int i;
+
+	for (i = 0;; ++i) {
+		ret = get_desc(if_type, i, &desc);
+		if (ret == -ENODEV)
+			break;
+		else if (ret)
+			continue;
+		if (desc->type == DEV_TYPE_UNKNOWN)
+			continue;  /* list only known devices */
+		printf("Device %d: ", i);
+		dev_print(desc);
+	}
+}
+
+int blk_print_device_num(enum if_type if_type, int devnum)
+{
+	struct blk_desc *desc;
+	int ret;
+
+	ret = get_desc(if_type, devnum, &desc);
+	if (ret)
+		return ret;
+	printf("\nIDE device %d: ", devnum);
+	dev_print(desc);
+
+	return 0;
+}
+
+int blk_show_device(enum if_type if_type, int devnum)
+{
+	struct blk_desc *desc;
+	int ret;
+
+	printf("\nDevice %d: ", devnum);
+	ret = get_desc(if_type, devnum, &desc);
+	if (ret == -ENODEV || ret == -ENOENT) {
+		printf("unknown device\n");
+		return -ENODEV;
+	}
+	if (ret)
+		return ret;
+	dev_print(desc);
+
+	if (desc->type == DEV_TYPE_UNKNOWN)
+		return -ENOENT;
+
+	return 0;
+}
+
+ulong blk_read_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		      lbaint_t blkcnt, void *buffer)
+{
+	struct blk_desc *desc;
+	ulong n;
+	int ret;
+
+	ret = get_desc(if_type, devnum, &desc);
+	if (ret)
+		return ret;
+	n = blk_dread(desc, start, blkcnt, buffer);
+	if (IS_ERR_VALUE(n))
+		return n;
+
+	/* flush cache after read */
+	flush_cache((ulong)buffer, blkcnt * desc->blksz);
+
+	return n;
+}
+
+ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		       lbaint_t blkcnt, const void *buffer)
+{
+	struct blk_desc *desc;
+	int ret;
+
+	ret = get_desc(if_type, devnum, &desc);
+	if (ret)
+		return ret;
+	return blk_dwrite(desc, start, blkcnt, buffer);
+}
+
+int blk_select_hwpart(struct udevice *dev, int hwpart)
+{
+	const struct blk_ops *ops = blk_get_ops(dev);
+
+	if (!ops)
+		return -ENOSYS;
+	if (!ops->select_hwpart)
+		return 0;
+
+	return ops->select_hwpart(dev, hwpart);
+}
+
+int blk_dselect_hwpart(struct blk_desc *desc, int hwpart)
+{
+	return blk_select_hwpart(desc->bdev, hwpart);
+}
+
 int blk_first_device(int if_type, struct udevice **devp)
 {
 	struct blk_desc *desc;
@@ -131,6 +440,26 @@
 	return 0;
 }
 
+int blk_find_max_devnum(enum if_type if_type)
+{
+	struct udevice *dev;
+	int max_devnum = -ENODEV;
+	struct uclass *uc;
+	int ret;
+
+	ret = uclass_get(UCLASS_BLK, &uc);
+	if (ret)
+		return ret;
+	uclass_foreach_dev(dev, uc) {
+		struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+		if (desc->if_type == if_type && desc->devnum > max_devnum)
+			max_devnum = desc->devnum;
+	}
+
+	return max_devnum;
+}
+
 int blk_create_device(struct udevice *parent, const char *drv_name,
 		      const char *name, int if_type, int devnum, int blksz,
 		      lbaint_t size, struct udevice **devp)
@@ -139,6 +468,15 @@
 	struct udevice *dev;
 	int ret;
 
+	if (devnum == -1) {
+		ret = blk_find_max_devnum(if_type);
+		if (ret == -ENODEV)
+			devnum = 0;
+		else if (ret < 0)
+			return ret;
+		else
+			devnum = ret + 1;
+	}
 	ret = device_bind_driver(parent, drv_name, name, &dev);
 	if (ret)
 		return ret;
@@ -154,6 +492,29 @@
 	return 0;
 }
 
+int blk_create_devicef(struct udevice *parent, const char *drv_name,
+		       const char *name, int if_type, int devnum, int blksz,
+		       lbaint_t size, struct udevice **devp)
+{
+	char dev_name[30], *str;
+	int ret;
+
+	snprintf(dev_name, sizeof(dev_name), "%s.%s", parent->name, name);
+	str = strdup(dev_name);
+	if (!str)
+		return -ENOMEM;
+
+	ret = blk_create_device(parent, drv_name, str, if_type, devnum,
+				blksz, size, devp);
+	if (ret) {
+		free(str);
+		return ret;
+	}
+	device_set_name_alloced(*devp);
+
+	return ret;
+}
+
 int blk_unbind_all(int if_type)
 {
 	struct uclass *uc;
diff --git a/drivers/block/blk_legacy.c b/drivers/block/blk_legacy.c
new file mode 100644
index 0000000..7b90a8a
--- /dev/null
+++ b/drivers/block/blk_legacy.c
@@ -0,0 +1,261 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+
+struct blk_driver *blk_driver_lookup_type(int if_type)
+{
+	struct blk_driver *drv = ll_entry_start(struct blk_driver, blk_driver);
+	const int n_ents = ll_entry_count(struct blk_driver, blk_driver);
+	struct blk_driver *entry;
+
+	for (entry = drv; entry != drv + n_ents; entry++) {
+		if (if_type == entry->if_type)
+			return entry;
+	}
+
+	/* Not found */
+	return NULL;
+}
+
+static struct blk_driver *blk_driver_lookup_typename(const char *if_typename)
+{
+	struct blk_driver *drv = ll_entry_start(struct blk_driver, blk_driver);
+	const int n_ents = ll_entry_count(struct blk_driver, blk_driver);
+	struct blk_driver *entry;
+
+	for (entry = drv; entry != drv + n_ents; entry++) {
+		if (!strcmp(if_typename, entry->if_typename))
+			return entry;
+	}
+
+	/* Not found */
+	return NULL;
+}
+
+/**
+ * get_desc() - Get the block device descriptor for the given device number
+ *
+ * @drv:	Legacy block driver
+ * @devnum:	Device number (0 = first)
+ * @descp:	Returns block device descriptor on success
+ * @return 0 on success, -ENODEV if there is no such device, -ENOSYS if the
+ * driver does not provide a way to find a device, or other -ve on other
+ * error.
+ */
+static int get_desc(struct blk_driver *drv, int devnum, struct blk_desc **descp)
+{
+	if (drv->desc) {
+		if (devnum < 0 || devnum >= drv->max_devs)
+			return -ENODEV;
+		*descp = &drv->desc[devnum];
+		return 0;
+	}
+	if (!drv->get_dev)
+		return -ENOSYS;
+
+	return drv->get_dev(devnum, descp);
+}
+
+#ifdef HAVE_BLOCK_DEVICE
+int blk_list_part(enum if_type if_type)
+{
+	struct blk_driver *drv;
+	struct blk_desc *desc;
+	int devnum, ok;
+	bool first = true;
+
+	drv = blk_driver_lookup_type(if_type);
+	if (!drv)
+		return -ENOSYS;
+	for (ok = 0, devnum = 0; devnum < drv->max_devs; ++devnum) {
+		if (get_desc(drv, devnum, &desc))
+			continue;
+		if (desc->part_type != PART_TYPE_UNKNOWN) {
+			++ok;
+			if (!first)
+				putc('\n');
+			part_print(desc);
+			first = false;
+		}
+	}
+	if (!ok)
+		return -ENODEV;
+
+	return 0;
+}
+
+int blk_print_part_devnum(enum if_type if_type, int devnum)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+	int ret;
+
+	if (!drv)
+		return -ENOSYS;
+	ret = get_desc(drv, devnum, &desc);
+	if (ret)
+		return ret;
+	if (desc->type == DEV_TYPE_UNKNOWN)
+		return -ENOENT;
+	part_print(desc);
+
+	return 0;
+}
+
+void blk_list_devices(enum if_type if_type)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+	int i;
+
+	if (!drv)
+		return;
+	for (i = 0; i < drv->max_devs; ++i) {
+		if (get_desc(drv, i, &desc))
+			continue;
+		if (desc->type == DEV_TYPE_UNKNOWN)
+			continue;  /* list only known devices */
+		printf("Device %d: ", i);
+		dev_print(desc);
+	}
+}
+
+int blk_print_device_num(enum if_type if_type, int devnum)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+	int ret;
+
+	if (!drv)
+		return -ENOSYS;
+	ret = get_desc(drv, devnum, &desc);
+	if (ret)
+		return ret;
+	printf("\n%s device %d: ", drv->if_typename, devnum);
+	dev_print(desc);
+
+	return 0;
+}
+
+int blk_show_device(enum if_type if_type, int devnum)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+	int ret;
+
+	if (!drv)
+		return -ENOSYS;
+	printf("\nDevice %d: ", devnum);
+	if (devnum >= drv->max_devs) {
+		puts("unknown device\n");
+		return -ENODEV;
+	}
+	ret = get_desc(drv, devnum, &desc);
+	if (ret)
+		return ret;
+	dev_print(desc);
+
+	if (desc->type == DEV_TYPE_UNKNOWN)
+		return -ENOENT;
+
+	return 0;
+}
+#endif /* HAVE_BLOCK_DEVICE */
+
+struct blk_desc *blk_get_devnum_by_type(enum if_type if_type, int devnum)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+
+	if (!drv)
+		return NULL;
+
+	if (get_desc(drv, devnum, &desc))
+		return NULL;
+
+	return desc;
+}
+
+int blk_dselect_hwpart(struct blk_desc *desc, int hwpart)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(desc->if_type);
+
+	if (!drv)
+		return -ENOSYS;
+	if (drv->select_hwpart)
+		return drv->select_hwpart(desc, hwpart);
+
+	return 0;
+}
+
+struct blk_desc *blk_get_devnum_by_typename(const char *if_typename, int devnum)
+{
+	struct blk_driver *drv = blk_driver_lookup_typename(if_typename);
+	struct blk_desc *desc;
+
+	if (!drv)
+		return NULL;
+
+	if (get_desc(drv, devnum, &desc))
+		return NULL;
+
+	return desc;
+}
+
+ulong blk_read_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		      lbaint_t blkcnt, void *buffer)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+	ulong n;
+	int ret;
+
+	if (!drv)
+		return -ENOSYS;
+	ret = get_desc(drv, devnum, &desc);
+	if (ret)
+		return ret;
+	n = desc->block_read(desc, start, blkcnt, buffer);
+	if (IS_ERR_VALUE(n))
+		return n;
+
+	/* flush cache after read */
+	flush_cache((ulong)buffer, blkcnt * desc->blksz);
+
+	return n;
+}
+
+ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		       lbaint_t blkcnt, const void *buffer)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+	int ret;
+
+	if (!drv)
+		return -ENOSYS;
+	ret = get_desc(drv, devnum, &desc);
+	if (ret)
+		return ret;
+	return desc->block_write(desc, start, blkcnt, buffer);
+}
+
+int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+	int ret;
+
+	if (!drv)
+		return -ENOSYS;
+	ret = get_desc(drv, devnum, &desc);
+	if (ret)
+		return ret;
+	return drv->select_hwpart(desc, hwpart);
+}
diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
index 2d340ef..ac28f83 100644
--- a/drivers/block/sandbox.c
+++ b/drivers/block/sandbox.c
@@ -17,6 +17,19 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_BLK
+static struct host_block_dev host_devices[CONFIG_HOST_MAX_DEVICES];
+
+static struct host_block_dev *find_host_device(int dev)
+{
+	if (dev >= 0 && dev < CONFIG_HOST_MAX_DEVICES)
+		return &host_devices[dev];
+
+	return NULL;
+}
+#endif
+
+#ifdef CONFIG_BLK
 static unsigned long host_block_read(struct udevice *dev,
 				     unsigned long start, lbaint_t blkcnt,
 				     void *buffer)
@@ -24,6 +37,18 @@
 	struct host_block_dev *host_dev = dev_get_priv(dev);
 	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
 
+#else
+static unsigned long host_block_read(struct blk_desc *block_dev,
+				     unsigned long start, lbaint_t blkcnt,
+				     void *buffer)
+{
+	int dev = block_dev->devnum;
+	struct host_block_dev *host_dev = find_host_device(dev);
+
+	if (!host_dev)
+		return -1;
+#endif
+
 	if (os_lseek(host_dev->fd, start * block_dev->blksz, OS_SEEK_SET) ==
 			-1) {
 		printf("ERROR: Invalid block %lx\n", start);
@@ -35,12 +60,21 @@
 	return -1;
 }
 
+#ifdef CONFIG_BLK
 static unsigned long host_block_write(struct udevice *dev,
 				      unsigned long start, lbaint_t blkcnt,
 				      const void *buffer)
 {
 	struct host_block_dev *host_dev = dev_get_priv(dev);
 	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#else
+static unsigned long host_block_write(struct blk_desc *block_dev,
+				      unsigned long start, lbaint_t blkcnt,
+				      const void *buffer)
+{
+	int dev = block_dev->devnum;
+	struct host_block_dev *host_dev = find_host_device(dev);
+#endif
 
 	if (os_lseek(host_dev->fd, start * block_dev->blksz, OS_SEEK_SET) ==
 			-1) {
@@ -53,6 +87,7 @@
 	return -1;
 }
 
+#ifdef CONFIG_BLK
 int host_dev_bind(int devnum, char *filename)
 {
 	struct host_block_dev *host_dev;
@@ -115,9 +150,51 @@
 	free(str);
 	return ret;
 }
+#else
+int host_dev_bind(int dev, char *filename)
+{
+	struct host_block_dev *host_dev = find_host_device(dev);
+
+	if (!host_dev)
+		return -1;
+	if (host_dev->blk_dev.priv) {
+		os_close(host_dev->fd);
+		host_dev->blk_dev.priv = NULL;
+	}
+	if (host_dev->filename)
+		free(host_dev->filename);
+	if (filename && *filename) {
+		host_dev->filename = strdup(filename);
+	} else {
+		host_dev->filename = NULL;
+		return 0;
+	}
+
+	host_dev->fd = os_open(host_dev->filename, OS_O_RDWR);
+	if (host_dev->fd == -1) {
+		printf("Failed to access host backing file '%s'\n",
+		       host_dev->filename);
+		return 1;
+	}
+
+	struct blk_desc *blk_dev = &host_dev->blk_dev;
+	blk_dev->if_type = IF_TYPE_HOST;
+	blk_dev->priv = host_dev;
+	blk_dev->blksz = 512;
+	blk_dev->lba = os_lseek(host_dev->fd, 0, OS_SEEK_END) / blk_dev->blksz;
+	blk_dev->block_read = host_block_read;
+	blk_dev->block_write = host_block_write;
+	blk_dev->devnum = dev;
+	blk_dev->part_type = PART_TYPE_UNKNOWN;
+	part_init(blk_dev);
+
+	return 0;
+}
+#endif
 
 int host_get_dev_err(int devnum, struct blk_desc **blk_devp)
 {
+#ifdef CONFIG_BLK
 	struct udevice *dev;
 	int ret;
 
@@ -125,20 +202,22 @@
 	if (ret)
 		return ret;
 	*blk_devp = dev_get_uclass_platdata(dev);
+#else
+	struct host_block_dev *host_dev = find_host_device(devnum);
+
+	if (!host_dev)
+		return -ENODEV;
+
+	if (!host_dev->blk_dev.priv)
+		return -ENOENT;
+
+	*blk_devp = &host_dev->blk_dev;
+#endif
 
 	return 0;
 }
 
-struct blk_desc *host_get_dev(int dev)
-{
-	struct blk_desc *blk_dev;
-
-	if (host_get_dev_err(dev, &blk_dev))
-		return NULL;
-
-	return blk_dev;
-}
-
+#ifdef CONFIG_BLK
 static const struct blk_ops sandbox_host_blk_ops = {
 	.read	= host_block_read,
 	.write	= host_block_write,
@@ -150,3 +229,11 @@
 	.ops		= &sandbox_host_blk_ops,
 	.priv_auto_alloc_size	= sizeof(struct host_block_dev),
 };
+#else
+U_BOOT_LEGACY_BLK(sandbox_host) = {
+	.if_typename	= "host",
+	.if_type	= IF_TYPE_HOST,
+	.max_devs	= CONFIG_HOST_MAX_DEVICES,
+	.get_dev	= host_get_dev_err,
+};
+#endif
diff --git a/drivers/block/sandbox_scsi.c b/drivers/block/sandbox_scsi.c
new file mode 100644
index 0000000..ad961bd
--- /dev/null
+++ b/drivers/block/sandbox_scsi.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * This file contains dummy implementations of SCSI functions requried so
+ * that CONFIG_SCSI can be enabled for sandbox.
+ */
+
+#include <common.h>
+#include <scsi.h>
+
+void scsi_bus_reset(void)
+{
+}
+
+void scsi_init(void)
+{
+}
+
+int scsi_exec(ccb *pccb)
+{
+	return 0;
+}
+
+void scsi_print_error(ccb *pccb)
+{
+}
diff --git a/drivers/block/sata_sandbox.c b/drivers/block/sata_sandbox.c
new file mode 100644
index 0000000..bd967d2
--- /dev/null
+++ b/drivers/block/sata_sandbox.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+int init_sata(int dev)
+{
+	return 0;
+}
+
+int reset_sata(int dev)
+{
+	return 0;
+}
+
+int scan_sata(int dev)
+{
+	return 0;
+}
+
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
+{
+	return 0;
+}
+
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
+{
+	return 0;
+}
diff --git a/drivers/block/sym53c8xx.c b/drivers/block/sym53c8xx.c
index c7c40af..5daede7 100644
--- a/drivers/block/sym53c8xx.c
+++ b/drivers/block/sym53c8xx.c
@@ -33,7 +33,7 @@
 #define PRINTF(fmt,args...)
 #endif
 
-#if defined(CONFIG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX)
+#if defined(CONFIG_SCSI) && defined(CONFIG_SCSI_SYM53C8XX)
 
 #undef SCSI_SINGLE_STEP
 /*
diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c
index 09fe834..9392bea 100644
--- a/drivers/block/systemace.c
+++ b/drivers/block/systemace.c
@@ -27,7 +27,7 @@
 
 #include <common.h>
 #include <command.h>
-#include <systemace.h>
+#include <dm.h>
 #include <part.h>
 #include <asm/io.h>
 
@@ -69,11 +69,9 @@
 	return in16(base + off);
 }
 
-static unsigned long systemace_read(struct blk_desc *block_dev,
-				    unsigned long start, lbaint_t blkcnt,
-				    void *buffer);
-
+#ifndef CONFIG_BLK
 static struct blk_desc systemace_dev = { 0 };
+#endif
 
 static int get_cf_lock(void)
 {
@@ -104,42 +102,19 @@
 	ace_writew((val & 0xffff), 0x18);
 }
 
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *systemace_get_dev(int dev)
-{
-	/* The first time through this, the systemace_dev object is
-	   not yet initialized. In that case, fill it in. */
-	if (systemace_dev.blksz == 0) {
-		systemace_dev.if_type = IF_TYPE_UNKNOWN;
-		systemace_dev.devnum = 0;
-		systemace_dev.part_type = PART_TYPE_UNKNOWN;
-		systemace_dev.type = DEV_TYPE_HARDDISK;
-		systemace_dev.blksz = 512;
-		systemace_dev.log2blksz = LOG2(systemace_dev.blksz);
-		systemace_dev.removable = 1;
-		systemace_dev.block_read = systemace_read;
-
-		/*
-		 * Ensure the correct bus mode (8/16 bits) gets enabled
-		 */
-		ace_writew(width == 8 ? 0 : 0x0001, 0);
-
-		part_init(&systemace_dev);
-
-	}
-
-	return &systemace_dev;
-}
-#endif
-
 /*
  * This function is called (by dereferencing the block_read pointer in
  * the dev_desc) to read blocks of data. The return value is the
  * number of blocks read. A zero return indicates an error.
  */
+#ifdef CONFIG_BLK
+static unsigned long systemace_read(struct udevice *dev, unsigned long start,
+				    lbaint_t blkcnt, void *buffer)
+#else
 static unsigned long systemace_read(struct blk_desc *block_dev,
 				    unsigned long start, lbaint_t blkcnt,
 				    void *buffer)
+#endif
 {
 	int retry;
 	unsigned blk_countdown;
@@ -257,3 +232,72 @@
 
 	return blkcnt;
 }
+
+#ifdef CONFIG_BLK
+static int systemace_bind(struct udevice *dev)
+{
+	struct blk_desc *bdesc;
+	struct udevice *bdev;
+	int ret;
+
+	ret = blk_create_devicef(dev, "systemace_blk", "blk", IF_TYPE_SYSTEMACE,
+				 -1, 512, 0, &bdev);
+	if (ret) {
+		debug("Cannot create block device\n");
+		return ret;
+	}
+	bdesc = dev_get_uclass_platdata(bdev);
+	bdesc->removable = 1;
+	bdesc->part_type = PART_TYPE_UNKNOWN;
+	bdesc->log2blksz = LOG2(bdesc->blksz);
+
+	/* Ensure the correct bus mode (8/16 bits) gets enabled */
+	ace_writew(width == 8 ? 0 : 0x0001, 0);
+
+	return 0;
+}
+
+static const struct blk_ops systemace_blk_ops = {
+	.read	= systemace_read,
+};
+
+U_BOOT_DRIVER(systemace_blk) = {
+	.name		= "systemace_blk",
+	.id		= UCLASS_BLK,
+	.ops		= &systemace_blk_ops,
+	.bind		= systemace_bind,
+};
+#else
+static int systemace_get_dev(int dev, struct blk_desc **descp)
+{
+	/* The first time through this, the systemace_dev object is
+	   not yet initialized. In that case, fill it in. */
+	if (systemace_dev.blksz == 0) {
+		systemace_dev.if_type = IF_TYPE_UNKNOWN;
+		systemace_dev.devnum = 0;
+		systemace_dev.part_type = PART_TYPE_UNKNOWN;
+		systemace_dev.type = DEV_TYPE_HARDDISK;
+		systemace_dev.blksz = 512;
+		systemace_dev.log2blksz = LOG2(systemace_dev.blksz);
+		systemace_dev.removable = 1;
+		systemace_dev.block_read = systemace_read;
+
+		/*
+		 * Ensure the correct bus mode (8/16 bits) gets enabled
+		 */
+		ace_writew(width == 8 ? 0 : 0x0001, 0);
+
+		part_init(&systemace_dev);
+	}
+	*descp = &systemace_dev;
+
+	return 0;
+}
+
+U_BOOT_LEGACY_BLK(systemace) = {
+	.if_typename	= "ace",
+	.if_type	= IF_TYPE_SYSTEMACE,
+	.max_devs	= 1,
+	.get_dev	= systemace_get_dev,
+};
+#endif
diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
index e1714b2..0e56b23 100644
--- a/drivers/core/device-remove.c
+++ b/drivers/core/device-remove.c
@@ -112,6 +112,8 @@
 
 	devres_release_all(dev);
 
+	if (dev->flags & DM_NAME_ALLOCED)
+		free((char *)dev->name);
 	free(dev);
 
 	return 0;
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 1322991..45d5e3e 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -657,8 +657,8 @@
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 	int index;
 
-	index = fdt_find_string(gd->fdt_blob, dev->parent->of_offset,
-				"reg-names", name);
+	index = fdt_find_string(gd->fdt_blob, dev->of_offset, "reg-names",
+				name);
 	if (index < 0)
 		return index;
 
@@ -706,12 +706,32 @@
 	return list_is_last(&dev->sibling_node, &parent->child_head);
 }
 
+void device_set_name_alloced(struct udevice *dev)
+{
+	dev->flags |= DM_NAME_ALLOCED;
+}
+
 int device_set_name(struct udevice *dev, const char *name)
 {
 	name = strdup(name);
 	if (!name)
 		return -ENOMEM;
 	dev->name = name;
+	device_set_name_alloced(dev);
 
 	return 0;
 }
+
+bool of_device_is_compatible(struct udevice *dev, const char *compat)
+{
+	const void *fdt = gd->fdt_blob;
+
+	return !fdt_node_check_compatible(fdt, dev->of_offset, compat);
+}
+
+bool of_machine_is_compatible(const char *compat)
+{
+	const void *fdt = gd->fdt_blob;
+
+	return !fdt_node_check_compatible(fdt, 0, compat);
+}
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index c4fc216..a72db13 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -171,6 +171,10 @@
 
 		dm_dbg("   - found match at '%s'\n", entry->name);
 		ret = device_bind(parent, entry, name, NULL, offset, &dev);
+		if (ret == -ENODEV) {
+			dm_dbg("Driver '%s' refuses to bind\n", entry->name);
+			continue;
+		}
 		if (ret) {
 			dm_warn("Error binding driver '%s': %d\n", entry->name,
 				ret);
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c
index ee05f57..55baad4 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -678,7 +678,7 @@
 	return (device_width == 0) ? 8 : 16;
 }
 
-float ddr3_get_device_size(u32 cs)
+static int ddr3_get_device_size(u32 cs)
 {
 	u32 device_size_low, device_size_high, device_size;
 	u32 data, cs_low_offset, cs_high_offset;
@@ -695,15 +695,15 @@
 
 	switch (device_size) {
 	case 0:
-		return 2;
+		return 2048;
 	case 2:
-		return 0.5;
+		return 512;
 	case 3:
-		return 1;
+		return 1024;
 	case 4:
-		return 4;
+		return 4096;
 	case 5:
-		return 8;
+		return 8192;
 	case 1:
 	default:
 		DEBUG_INIT_C("Error: Wrong device size of Cs: ", cs, 1);
@@ -711,13 +711,13 @@
 		 * Small value will give wrong emem size in
 		 * ddr3_calc_mem_cs_size
 		 */
-		return 0.01;
+		return 0;
 	}
 }
 
 int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size)
 {
-	float cs_mem_size;
+	int cs_mem_size;
 
 	/* Calculate in GiB */
 	cs_mem_size = ((ddr3_get_bus_width() / ddr3_get_device_width(cs)) *
@@ -731,21 +731,12 @@
 	 */
 	cs_mem_size *= DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER;
 
-	if (cs_mem_size == 0.125) {
-		*cs_size = 128 << 20;
-	} else if (cs_mem_size == 0.25) {
-		*cs_size = 256 << 20;
-	} else if (cs_mem_size == 0.5) {
-		*cs_size = 512 << 20;
-	} else if (cs_mem_size == 1) {
-		*cs_size = 1 << 30;
-	} else if (cs_mem_size == 2) {
-		*cs_size = 2 << 30;
-	} else {
+	if (!cs_mem_size || (cs_mem_size == 64) || (cs_mem_size == 4096)) {
 		DEBUG_INIT_C("Error: Wrong Memory size of Cs: ", cs, 1);
 		return MV_BAD_VALUE;
 	}
 
+	*cs_size = cs_mem_size << 20;
 	return MV_OK;
 }
 
diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c
index faece88..78724e4 100644
--- a/drivers/dfu/dfu_mmc.c
+++ b/drivers/dfu/dfu_mmc.c
@@ -50,8 +50,9 @@
 
 	if (dfu->data.mmc.hw_partition >= 0) {
 		part_num_bkp = mmc->block_dev.hwpart;
-		ret = mmc_select_hwpart(dfu->data.mmc.dev_num,
-					dfu->data.mmc.hw_partition);
+		ret = blk_select_hwpart_devnum(IF_TYPE_MMC,
+					       dfu->data.mmc.dev_num,
+					       dfu->data.mmc.hw_partition);
 		if (ret)
 			return ret;
 	}
@@ -75,12 +76,16 @@
 	if (n != blk_count) {
 		error("MMC operation failed");
 		if (dfu->data.mmc.hw_partition >= 0)
-			mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp);
+			blk_select_hwpart_devnum(IF_TYPE_MMC,
+						 dfu->data.mmc.dev_num,
+						 part_num_bkp);
 		return -EIO;
 	}
 
 	if (dfu->data.mmc.hw_partition >= 0) {
-		ret = mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp);
+		ret = blk_select_hwpart_devnum(IF_TYPE_MMC,
+					       dfu->data.mmc.dev_num,
+					       part_num_bkp);
 		if (ret)
 			return ret;
 	}
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index d94eb5c..7e2f3e1 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -120,7 +120,7 @@
 }
 
 /*
- * fgpa_init is usually called from misc_init_r() and MUST be called
+ * fpga_init is usually called from misc_init_r() and MUST be called
  * before any of the other fpga functions are used.
  */
 void fpga_init(void)
diff --git a/drivers/gpio/74x164_gpio.c b/drivers/gpio/74x164_gpio.c
new file mode 100644
index 0000000..9ac10a7
--- /dev/null
+++ b/drivers/gpio/74x164_gpio.c
@@ -0,0 +1,193 @@
+/*
+ * Take drivers/gpio/gpio-74x164.c as reference.
+ *
+ * 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
+ *
+ * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * struct gen_74x164_chip - Data for 74Hx164
+ *
+ * @oe: OE pin
+ * @nregs: number of registers
+ * @buffer: buffer for chained chips
+ */
+#define GEN_74X164_NUMBER_GPIOS 8
+
+struct gen_74x164_priv {
+	struct gpio_desc oe;
+	u32 nregs;
+	/*
+	 * Since the nregs are chained, every byte sent will make
+	 * the previous byte shift to the next register in the
+	 * chain. Thus, the first byte sent will end up in the last
+	 * register at the end of the transfer. So, to have a logical
+	 * numbering, store the bytes in reverse order.
+	 */
+	u8 *buffer;
+};
+
+static int gen_74x164_write_conf(struct udevice *dev)
+{
+	struct gen_74x164_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = dm_spi_claim_bus(dev);
+	if (ret)
+		return ret;
+
+	ret = dm_spi_xfer(dev, priv->nregs * 8, priv->buffer, NULL,
+			  SPI_XFER_BEGIN | SPI_XFER_END);
+
+	dm_spi_release_bus(dev);
+
+	return ret;
+}
+
+static int gen_74x164_get_value(struct udevice *dev, unsigned offset)
+{
+	struct gen_74x164_priv *priv = dev_get_priv(dev);
+	uint bank = priv->nregs - 1 - offset / 8;
+	uint pin = offset % 8;
+
+	return (priv->buffer[bank] >> pin) & 0x1;
+}
+
+static int gen_74x164_set_value(struct udevice *dev, unsigned offset,
+				int value)
+{
+	struct gen_74x164_priv *priv = dev_get_priv(dev);
+	uint bank = priv->nregs - 1 - offset / 8;
+	uint pin = offset % 8;
+	int ret;
+
+	if (value)
+		priv->buffer[bank] |= 1 << pin;
+	else
+		priv->buffer[bank] &= ~(1 << pin);
+
+	ret = gen_74x164_write_conf(dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int gen_74x164_direction_input(struct udevice *dev, unsigned offset)
+{
+	return -ENOSYS;
+}
+
+static int gen_74x164_direction_output(struct udevice *dev, unsigned offset,
+				      int value)
+{
+	return gen_74x164_set_value(dev, offset, value);
+}
+
+static int gen_74x164_get_function(struct udevice *dev, unsigned offset)
+{
+	return GPIOF_OUTPUT;
+}
+
+static int gen_74x164_xlate(struct udevice *dev, struct gpio_desc *desc,
+			    struct fdtdec_phandle_args *args)
+{
+	desc->offset = args->args[0];
+	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops gen_74x164_ops = {
+	.direction_input	= gen_74x164_direction_input,
+	.direction_output	= gen_74x164_direction_output,
+	.get_value		= gen_74x164_get_value,
+	.set_value		= gen_74x164_set_value,
+	.get_function		= gen_74x164_get_function,
+	.xlate			= gen_74x164_xlate,
+};
+
+static int gen_74x164_probe(struct udevice *dev)
+{
+	struct gen_74x164_priv *priv = dev_get_priv(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	char *str, name[32];
+	int ret;
+	const void *fdt = gd->fdt_blob;
+	int node = dev->of_offset;
+
+	snprintf(name, sizeof(name), "%s_", dev->name);
+	str = strdup(name);
+	if (!str)
+		return -ENOMEM;
+
+	/*
+	 * See Linux kernel:
+	 * Documentation/devicetree/bindings/gpio/gpio-74x164.txt
+	 */
+	priv->nregs = fdtdec_get_int(fdt, node, "registers-number", 1);
+	priv->buffer = calloc(priv->nregs, sizeof(u8));
+	if (!priv->buffer) {
+		ret = -ENOMEM;
+		goto free_str;
+	}
+
+	ret = fdtdec_get_byte_array(fdt, node, "registers-default",
+				    priv->buffer, priv->nregs);
+	if (ret)
+		dev_dbg(dev, "No registers-default property\n");
+
+	ret = gpio_request_by_name(dev, "oe-gpios", 0, &priv->oe,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	if (ret) {
+		dev_err(dev, "No oe-pins property\n");
+		goto free_buf;
+	}
+
+	uc_priv->bank_name = str;
+	uc_priv->gpio_count = priv->nregs * 8;
+
+	ret = gen_74x164_write_conf(dev);
+	if (ret)
+		goto free_buf;
+
+	dev_dbg(dev, "%s is ready\n", dev->name);
+
+	return 0;
+
+free_buf:
+	free(priv->buffer);
+free_str:
+	free(str);
+	return ret;
+}
+
+static const struct udevice_id gen_74x164_ids[] = {
+	{ .compatible = "fairchild,74hc595" },
+	{ }
+};
+
+U_BOOT_DRIVER(74x164) = {
+	.name		= "74x164",
+	.id		= UCLASS_GPIO,
+	.ops		= &gen_74x164_ops,
+	.probe		= gen_74x164_probe,
+	.priv_auto_alloc_size = sizeof(struct gen_74x164_priv),
+	.of_match	= gen_74x164_ids,
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 2b4624d..93a7e8c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -143,4 +143,34 @@
 	help
 	  Supports GPIO access on Zynq SoC.
 
+config DM_74X164
+	bool "74x164 serial-in/parallel-out 8-bits shift register"
+	depends on DM_GPIO
+	help
+	  Driver for 74x164 compatible serial-in/parallel-out 8-outputs
+	  shift registers, such as 74lv165, 74hc595.
+	  This driver can be used to provide access to more gpio outputs.
+
+config DM_PCA953X
+	bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports"
+	depends on DM_GPIO
+	help
+	  Say yes here to provide access to several register-oriented
+	  SMBus I/O expanders, made mostly by NXP or TI.  Compatible
+	  models include:
+
+	  4 bits:	pca9536, pca9537
+
+	  8 bits:	max7310, max7315, pca6107, pca9534, pca9538, pca9554,
+			pca9556, pca9557, pca9574, tca6408, xra1202
+
+	  16 bits:	max7312, max7313, pca9535, pca9539, pca9555, pca9575,
+			tca6416
+
+	  24 bits:	tca6424
+
+	  40 bits:	pca9505, pca9698
+
+	  Now, max 24 bits chips and PCA953X compatible chips are
+	  supported
 endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 4f071c4..ddec1ef 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -11,6 +11,9 @@
 endif
 obj-$(CONFIG_DM_GPIO)		+= gpio-uclass.o
 
+obj-$(CONFIG_DM_PCA953X)	+= pca953x_gpio.o
+obj-$(CONFIG_DM_74X164)		+= 74x164_gpio.o
+
 obj-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
 obj-$(CONFIG_ATMEL_PIO4)	+= atmel_pio4.o
 obj-$(CONFIG_INTEL_ICH6_GPIO)	+= intel_ich6_gpio.o
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index b58d4e6..732b6c2 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <dt-bindings/gpio/gpio.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <malloc.h>
@@ -113,19 +114,33 @@
 	return 0;
 }
 
+int gpio_xlate_offs_flags(struct udevice *dev,
+					 struct gpio_desc *desc,
+					 struct fdtdec_phandle_args *args)
+{
+	if (args->args_count < 1)
+		return -EINVAL;
+
+	desc->offset = args->args[0];
+
+	if (args->args_count < 2)
+		return 0;
+
+	if (args->args[1] & GPIO_ACTIVE_LOW)
+		desc->flags = GPIOD_ACTIVE_LOW;
+
+	return 0;
+}
+
 static int gpio_find_and_xlate(struct gpio_desc *desc,
 			       struct fdtdec_phandle_args *args)
 {
 	struct dm_gpio_ops *ops = gpio_get_ops(desc->dev);
 
-	/* Use the first argument as the offset by default */
-	if (args->args_count > 0)
-		desc->offset = args->args[0];
+	if (ops->xlate)
+		return ops->xlate(desc->dev, desc, args);
 	else
-		desc->offset = -1;
-	desc->flags = 0;
-
-	return ops->xlate ? ops->xlate(desc->dev, desc, args) : 0;
+		return gpio_xlate_offs_flags(desc->dev, desc, args);
 }
 
 int dm_gpio_request(struct gpio_desc *desc, const char *label)
@@ -605,6 +620,7 @@
 
 	desc->dev = NULL;
 	desc->offset = 0;
+	desc->flags = 0;
 	ret = fdtdec_parse_phandle_with_args(blob, node, list_name,
 					     "#gpio-cells", 0, index, &args);
 	if (ret) {
diff --git a/drivers/gpio/intel_broadwell_gpio.c b/drivers/gpio/intel_broadwell_gpio.c
index 8cf76f9..81ce446 100644
--- a/drivers/gpio/intel_broadwell_gpio.c
+++ b/drivers/gpio/intel_broadwell_gpio.c
@@ -162,15 +162,6 @@
 	return 0;
 }
 
-static int broadwell_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
-				struct fdtdec_phandle_args *args)
-{
-	desc->offset = args->args[0];
-	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
-	return 0;
-}
-
 static const struct dm_gpio_ops gpio_broadwell_ops = {
 	.request		= broadwell_gpio_request,
 	.direction_input	= broadwell_gpio_direction_input,
@@ -178,7 +169,6 @@
 	.get_value		= broadwell_gpio_get_value,
 	.set_value		= broadwell_gpio_set_value,
 	.get_function		= broadwell_gpio_get_function,
-	.xlate			= broadwell_gpio_xlate,
 };
 
 static const struct udevice_id intel_broadwell_gpio_ids[] = {
diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
index 93d18e4..cd960dc 100644
--- a/drivers/gpio/omap_gpio.c
+++ b/drivers/gpio/omap_gpio.c
@@ -25,7 +25,6 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <malloc.h>
-#include <dt-bindings/gpio/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -277,22 +276,12 @@
 		return GPIOF_INPUT;
 }
 
-static int omap_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
-			   struct fdtdec_phandle_args *args)
-{
-	desc->offset = args->args[0];
-	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
-	return 0;
-}
-
 static const struct dm_gpio_ops gpio_omap_ops = {
 	.direction_input	= omap_gpio_direction_input,
 	.direction_output	= omap_gpio_direction_output,
 	.get_value		= omap_gpio_get_value,
 	.set_value		= omap_gpio_set_value,
 	.get_function		= omap_gpio_get_function,
-	.xlate			= omap_gpio_xlate,
 };
 
 static int omap_gpio_probe(struct udevice *dev)
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
new file mode 100644
index 0000000..987d10e
--- /dev/null
+++ b/drivers/gpio/pca953x_gpio.c
@@ -0,0 +1,351 @@
+/*
+ * Take linux kernel driver drivers/gpio/gpio-pca953x.c for reference.
+ *
+ * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+/*
+ * Note:
+ * The driver's compatible table is borrowed from Linux Kernel,
+ * but now max supported gpio pins is 24 and only PCA953X_TYPE
+ * is supported. PCA957X_TYPE is not supported now.
+ * Also the Polarity Inversion feature is not supported now.
+ *
+ * TODO:
+ * 1. Support PCA957X_TYPE
+ * 2. Support max 40 gpio pins
+ * 3. Support Plolarity Inversion
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#define PCA953X_INPUT           0
+#define PCA953X_OUTPUT          1
+#define PCA953X_INVERT          2
+#define PCA953X_DIRECTION       3
+
+#define PCA_GPIO_MASK           0x00FF
+#define PCA_INT                 0x0100
+#define PCA953X_TYPE            0x1000
+#define PCA957X_TYPE            0x2000
+#define PCA_TYPE_MASK           0xF000
+#define PCA_CHIP_TYPE(x)        ((x) & PCA_TYPE_MASK)
+
+enum {
+	PCA953X_DIRECTION_IN,
+	PCA953X_DIRECTION_OUT,
+};
+
+#define MAX_BANK 3
+#define BANK_SZ 8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * struct pca953x_info - Data for pca953x
+ *
+ * @dev: udevice structure for the device
+ * @addr: i2c slave address
+ * @invert: Polarity inversion or not
+ * @gpio_count: the number of gpio pins that the device supports
+ * @chip_type: indicate the chip type,PCA953X or PCA957X
+ * @bank_count: the number of banks that the device supports
+ * @reg_output: array to hold the value of output registers
+ * @reg_direction: array to hold the value of direction registers
+ */
+struct pca953x_info {
+	struct udevice *dev;
+	int addr;
+	int invert;
+	int gpio_count;
+	int chip_type;
+	int bank_count;
+	u8 reg_output[MAX_BANK];
+	u8 reg_direction[MAX_BANK];
+};
+
+static int pca953x_write_single(struct udevice *dev, int reg, u8 val,
+				int offset)
+{
+	struct pca953x_info *info = dev_get_platdata(dev);
+	int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
+	int off = offset / BANK_SZ;
+	int ret = 0;
+
+	ret = dm_i2c_write(dev, (reg << bank_shift) + off, &val, 1);
+	if (ret) {
+		dev_err(dev, "%s error\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int pca953x_read_single(struct udevice *dev, int reg, u8 *val,
+			       int offset)
+{
+	struct pca953x_info *info = dev_get_platdata(dev);
+	int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
+	int off = offset / BANK_SZ;
+	int ret;
+	u8 byte;
+
+	ret = dm_i2c_read(dev, (reg << bank_shift) + off, &byte, 1);
+	if (ret) {
+		dev_err(dev, "%s error\n", __func__);
+		return ret;
+	}
+
+	*val = byte;
+
+	return 0;
+}
+
+static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val)
+{
+	struct pca953x_info *info = dev_get_platdata(dev);
+	int ret = 0;
+
+	if (info->gpio_count <= 8) {
+		ret = dm_i2c_read(dev, reg, val, 1);
+	} else if (info->gpio_count <= 16) {
+		ret = dm_i2c_read(dev, reg << 1, val, info->bank_count);
+	} else {
+		dev_err(dev, "Unsupported now\n");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static int pca953x_is_output(struct udevice *dev, int offset)
+{
+	struct pca953x_info *info = dev_get_platdata(dev);
+
+	int bank = offset / BANK_SZ;
+	int off = offset % BANK_SZ;
+
+	/*0: output; 1: input */
+	return !(info->reg_direction[bank] & (1 << off));
+}
+
+static int pca953x_get_value(struct udevice *dev, unsigned offset)
+{
+	int ret;
+	u8 val = 0;
+
+	ret = pca953x_read_single(dev, PCA953X_INPUT, &val, offset);
+	if (ret)
+		return ret;
+
+	return (val >> offset) & 0x1;
+}
+
+static int pca953x_set_value(struct udevice *dev, unsigned offset,
+			     int value)
+{
+	struct pca953x_info *info = dev_get_platdata(dev);
+	int bank = offset / BANK_SZ;
+	int off = offset % BANK_SZ;
+	u8 val;
+	int ret;
+
+	if (value)
+		val = info->reg_output[bank] | (1 << off);
+	else
+		val = info->reg_output[bank] & ~(1 << off);
+
+	ret = pca953x_write_single(dev, PCA953X_OUTPUT, val, offset);
+	if (ret)
+		return ret;
+
+	info->reg_output[bank] = val;
+
+	return 0;
+}
+
+static int pca953x_set_direction(struct udevice *dev, unsigned offset, int dir)
+{
+	struct pca953x_info *info = dev_get_platdata(dev);
+	int bank = offset / BANK_SZ;
+	int off = offset % BANK_SZ;
+	u8 val;
+	int ret;
+
+	if (dir == PCA953X_DIRECTION_IN)
+		val = info->reg_direction[bank] | (1 << off);
+	else
+		val = info->reg_direction[bank] & ~(1 << off);
+
+	ret = pca953x_write_single(dev, PCA953X_DIRECTION, val, offset);
+	if (ret)
+		return ret;
+
+	info->reg_direction[bank] = val;
+
+	return 0;
+}
+
+static int pca953x_direction_input(struct udevice *dev, unsigned offset)
+{
+	return pca953x_set_direction(dev, offset, PCA953X_DIRECTION_IN);
+}
+
+static int pca953x_direction_output(struct udevice *dev, unsigned offset,
+				    int value)
+{
+	/* Configure output value. */
+	pca953x_set_value(dev, offset, value);
+
+	/* Configure direction as output. */
+	pca953x_set_direction(dev, offset, PCA953X_DIRECTION_OUT);
+
+	return 0;
+}
+
+static int pca953x_get_function(struct udevice *dev, unsigned offset)
+{
+	if (pca953x_is_output(dev, offset))
+		return GPIOF_OUTPUT;
+	else
+		return GPIOF_INPUT;
+}
+
+static int pca953x_xlate(struct udevice *dev, struct gpio_desc *desc,
+			 struct fdtdec_phandle_args *args)
+{
+	desc->offset = args->args[0];
+	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops pca953x_ops = {
+	.direction_input	= pca953x_direction_input,
+	.direction_output	= pca953x_direction_output,
+	.get_value		= pca953x_get_value,
+	.set_value		= pca953x_set_value,
+	.get_function		= pca953x_get_function,
+	.xlate			= pca953x_xlate,
+};
+
+static int pca953x_probe(struct udevice *dev)
+{
+	struct pca953x_info *info = dev_get_platdata(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+	char name[32], *str;
+	int addr;
+	ulong driver_data;
+	int ret;
+
+	if (!info) {
+		dev_err(dev, "platdata not ready\n");
+		return -ENOMEM;
+	}
+
+	if (!chip) {
+		dev_err(dev, "i2c not ready\n");
+		return -ENODEV;
+	}
+
+	addr = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", 0);
+	if (addr == 0)
+		return -ENODEV;
+
+	info->addr = addr;
+
+	driver_data = dev_get_driver_data(dev);
+
+	info->gpio_count = driver_data & PCA_GPIO_MASK;
+	if (info->gpio_count > MAX_BANK * BANK_SZ) {
+		dev_err(dev, "Max support %d pins now\n", MAX_BANK * BANK_SZ);
+		return -EINVAL;
+	}
+
+	info->chip_type = PCA_CHIP_TYPE(driver_data);
+	if (info->chip_type != PCA953X_TYPE) {
+		dev_err(dev, "Only support PCA953X chip type now.\n");
+		return -EINVAL;
+	}
+
+	info->bank_count = DIV_ROUND_UP(info->gpio_count, BANK_SZ);
+
+	ret = pca953x_read_regs(dev, PCA953X_OUTPUT, info->reg_output);
+	if (ret) {
+		dev_err(dev, "Error reading output register\n");
+		return ret;
+	}
+
+	ret = pca953x_read_regs(dev, PCA953X_DIRECTION, info->reg_direction);
+	if (ret) {
+		dev_err(dev, "Error reading direction register\n");
+		return ret;
+	}
+
+	snprintf(name, sizeof(name), "gpio@%x_", info->addr);
+	str = strdup(name);
+	if (!str)
+		return -ENOMEM;
+	uc_priv->bank_name = str;
+	uc_priv->gpio_count = info->gpio_count;
+
+	dev_dbg(dev, "%s is ready\n", str);
+
+	return 0;
+}
+
+#define OF_953X(__nrgpio, __int) (ulong)(__nrgpio | PCA953X_TYPE | __int)
+#define OF_957X(__nrgpio, __int) (ulong)(__nrgpio | PCA957X_TYPE | __int)
+
+static const struct udevice_id pca953x_ids[] = {
+	{ .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
+	{ .compatible = "nxp,pca9534", .data = OF_953X(8, PCA_INT), },
+	{ .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
+	{ .compatible = "nxp,pca9536", .data = OF_953X(4, 0), },
+	{ .compatible = "nxp,pca9537", .data = OF_953X(4, PCA_INT), },
+	{ .compatible = "nxp,pca9538", .data = OF_953X(8, PCA_INT), },
+	{ .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
+	{ .compatible = "nxp,pca9554", .data = OF_953X(8, PCA_INT), },
+	{ .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
+	{ .compatible = "nxp,pca9556", .data = OF_953X(8, 0), },
+	{ .compatible = "nxp,pca9557", .data = OF_953X(8, 0), },
+	{ .compatible = "nxp,pca9574", .data = OF_957X(8, PCA_INT), },
+	{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
+	{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
+
+	{ .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
+	{ .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
+	{ .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
+	{ .compatible = "maxim,max7315", .data = OF_953X(8, PCA_INT), },
+
+	{ .compatible = "ti,pca6107", .data = OF_953X(8, PCA_INT), },
+	{ .compatible = "ti,tca6408", .data = OF_953X(8, PCA_INT), },
+	{ .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
+	{ .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
+
+	{ .compatible = "onsemi,pca9654", .data = OF_953X(8, PCA_INT), },
+
+	{ .compatible = "exar,xra1202", .data = OF_953X(8, 0), },
+	{ }
+};
+
+U_BOOT_DRIVER(pca953x) = {
+	.name		= "pca953x",
+	.id		= UCLASS_GPIO,
+	.ops		= &pca953x_ops,
+	.probe		= pca953x_probe,
+	.platdata_auto_alloc_size = sizeof(struct pca953x_info),
+	.of_match	= pca953x_ids,
+};
diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c
index 499b4fa..7a037f3 100644
--- a/drivers/gpio/pic32_gpio.c
+++ b/drivers/gpio/pic32_gpio.c
@@ -12,7 +12,6 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <linux/compat.h>
-#include <dt-bindings/gpio/gpio.h>
 #include <mach/pic32.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -99,14 +98,6 @@
 	return 0;
 }
 
-static int pic32_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
-			    struct fdtdec_phandle_args *args)
-{
-	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
-	return 0;
-}
-
 static int pic32_gpio_get_function(struct udevice *dev, unsigned offset)
 {
 	int ret = GPIOF_UNUSED;
@@ -131,7 +122,6 @@
 	.get_value		= pic32_gpio_get_value,
 	.set_value		= pic32_gpio_set_value,
 	.get_function		= pic32_gpio_get_function,
-	.xlate			= pic32_gpio_xlate,
 };
 
 static int pic32_gpio_probe(struct udevice *dev)
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index 40e87bd..fefe3ca 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -16,7 +16,6 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <dm/pinctrl.h>
-#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/rk3288-cru.h>
 
 enum {
@@ -98,15 +97,6 @@
 #endif
 }
 
-static int rockchip_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
-			    struct fdtdec_phandle_args *args)
-{
-	desc->offset = args->args[0];
-	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
-	return 0;
-}
-
 static int rockchip_gpio_probe(struct udevice *dev)
 {
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
@@ -135,7 +125,6 @@
 	.get_value		= rockchip_gpio_get_value,
 	.set_value		= rockchip_gpio_set_value,
 	.get_function		= rockchip_gpio_get_function,
-	.xlate			= rockchip_gpio_xlate,
 };
 
 static const struct udevice_id rockchip_gpio_ids[] = {
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index 0f22b23..377fed4 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -13,7 +13,6 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <dm/device-internal.h>
-#include <dt-bindings/gpio/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -276,22 +275,12 @@
 		return GPIOF_FUNC;
 }
 
-static int exynos_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
-			     struct fdtdec_phandle_args *args)
-{
-	desc->offset = args->args[0];
-	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
-	return 0;
-}
-
 static const struct dm_gpio_ops gpio_exynos_ops = {
 	.direction_input	= exynos_gpio_direction_input,
 	.direction_output	= exynos_gpio_direction_output,
 	.get_value		= exynos_gpio_get_value,
 	.set_value		= exynos_gpio_set_value,
 	.get_function		= exynos_gpio_get_function,
-	.xlate			= exynos_gpio_xlate,
 };
 
 static int gpio_exynos_probe(struct udevice *dev)
diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
index 3a995f6..4ab2356 100644
--- a/drivers/gpio/zynq_gpio.c
+++ b/drivers/gpio/zynq_gpio.c
@@ -299,11 +299,33 @@
 	return 0;
 }
 
+static int zynq_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	u32 reg;
+	unsigned int bank_num, bank_pin_num;
+	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+
+	if (check_gpio(offset, dev) < 0)
+		return -1;
+
+	zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
+
+	/* set the GPIO pin as output */
+	reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+	reg &= BIT(bank_pin_num);
+	if (reg)
+		return GPIOF_OUTPUT;
+	else
+		return GPIOF_INPUT;
+}
+
 static const struct dm_gpio_ops gpio_zynq_ops = {
 	.direction_input	= zynq_gpio_direction_input,
 	.direction_output	= zynq_gpio_direction_output,
 	.get_value		= zynq_gpio_get_value,
 	.set_value		= zynq_gpio_set_value,
+	.get_function		= zynq_gpio_get_function,
+
 };
 
 static const struct udevice_id zynq_gpio_ids[] = {
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 9324c6c..6e22bba 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -58,6 +58,13 @@
 	  bindings are supported.
 	  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
 
+config SYS_I2C_FSL
+       bool "Freescale I2C bus driver"
+       depends on DM_I2C
+       help
+	  Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
+	  MPC85xx processors.
+
 config SYS_I2C_CADENCE
 	tristate "Cadence I2C Controller"
 	depends on DM_I2C && (ARCH_ZYNQ || ARM64)
@@ -65,6 +72,24 @@
 	  Say yes here to select Cadence I2C Host Controller. This controller is
 	  e.g. used by Xilinx Zynq.
 
+config SYS_I2C_DW
+	bool "Designware I2C Controller"
+	default n
+	help
+	  Say yes here to select the Designware I2C Host Controller. This
+	  controller is used in various SoCs, e.g. the ST SPEAr, Altera
+	  SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
+
+config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
+	bool "DW I2C Enable Status Register not supported"
+	depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
+		TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
+	default y
+	help
+	  Some versions of the Designware I2C controller do not support the
+	  enable status register. This config option can be enabled in such
+	  cases.
+
 config SYS_I2C_INTEL
 	bool "Intel I2C/SMBUS driver"
 	depends on DM_I2C
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 0c7cd0b..e60fd0a 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -36,6 +36,14 @@
 	struct dw_scl_sda_cfg *scl_sda_cfg;
 };
 
+#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
+static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
+{
+	u32 ena = enable ? IC_ENABLE_0B : 0;
+
+	writel(ena, &i2c_base->ic_enable);
+}
+#else
 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
 {
 	u32 ena = enable ? IC_ENABLE_0B : 0;
@@ -56,6 +64,7 @@
 
 	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
 }
+#endif
 
 /*
  * i2c_set_bus_speed - Set the i2c speed
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index b56a1c2..b8cc647 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -12,6 +12,8 @@
 #include <i2c.h>		/* Functional interface */
 #include <asm/io.h>
 #include <asm/fsl_i2c.h>	/* HW definitions */
+#include <dm.h>
+#include <mapmem.h>
 
 /* The maximum number of microseconds we will wait until another master has
  * released the bus.  If not defined in the board header file, then use a
@@ -34,18 +36,20 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct fsl_i2c *i2c_dev[4] = {
-	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
+#ifndef CONFIG_DM_I2C
+static const struct fsl_i2c_base *i2c_base[4] = {
+	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
-	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
+	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
 #endif
 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
-	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
+	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
 #endif
 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
-	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
+	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
 #endif
 };
+#endif
 
 /* I2C speed map for a DFSR value of 1 */
 
@@ -104,7 +108,7 @@
 /**
  * Set the I2C bus speed for a given I2C device
  *
- * @param dev: the I2C device
+ * @param base: the I2C device registers
  * @i2c_clk: I2C bus clock frequency
  * @speed: the desired speed of the bus
  *
@@ -112,7 +116,7 @@
  *
  * The return value is the actual bus speed that is set.
  */
-static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
+static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base,
 	unsigned int i2c_clk, unsigned int speed)
 {
 	unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX);
@@ -173,8 +177,8 @@
 	debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
 	debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
 #endif
-	writeb(dfsr, &dev->dfsrr);	/* set default filter */
-	writeb(fdr, &dev->fdr);		/* set bus speed */
+	writeb(dfsr, &base->dfsrr);	/* set default filter */
+	writeb(fdr, &base->fdr);	/* set bus speed */
 #else
 	unsigned int i;
 
@@ -184,7 +188,7 @@
 
 			fdr = fsl_i2c_speed_map[i].fdr;
 			speed = i2c_clk / fsl_i2c_speed_map[i].divider;
-			writeb(fdr, &dev->fdr);		/* set bus speed */
+			writeb(fdr, &base->fdr);	/* set bus speed */
 
 			break;
 		}
@@ -192,6 +196,7 @@
 	return speed;
 }
 
+#ifndef CONFIG_DM_I2C
 static unsigned int get_i2c_clock(int bus)
 {
 	if (bus)
@@ -199,8 +204,9 @@
 	else
 		return gd->arch.i2c1_clk;	/* I2C1 clock */
 }
+#endif
 
-static int fsl_i2c_fixup(const struct fsl_i2c *dev)
+static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
 {
 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
 	unsigned long long timeval = 0;
@@ -214,42 +220,42 @@
 		flags = I2C_CR_BIT6;
 #endif
 
-	writeb(I2C_CR_MEN | I2C_CR_MSTA, &dev->cr);
+	writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
 
 	timeval = get_ticks();
-	while (!(readb(&dev->sr) & I2C_SR_MBB)) {
+	while (!(readb(&base->sr) & I2C_SR_MBB)) {
 		if ((get_ticks() - timeval) > timeout)
 			goto err;
 	}
 
-	if (readb(&dev->sr) & I2C_SR_MAL) {
+	if (readb(&base->sr) & I2C_SR_MAL) {
 		/* SDA is stuck low */
-		writeb(0, &dev->cr);
+		writeb(0, &base->cr);
 		udelay(100);
-		writeb(I2C_CR_MSTA | flags, &dev->cr);
-		writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &dev->cr);
+		writeb(I2C_CR_MSTA | flags, &base->cr);
+		writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
 	}
 
-	readb(&dev->dr);
+	readb(&base->dr);
 
 	timeval = get_ticks();
-	while (!(readb(&dev->sr) & I2C_SR_MIF)) {
+	while (!(readb(&base->sr) & I2C_SR_MIF)) {
 		if ((get_ticks() - timeval) > timeout)
 			goto err;
 	}
 	ret = 0;
 
 err:
-	writeb(I2C_CR_MEN | flags, &dev->cr);
-	writeb(0, &dev->sr);
+	writeb(I2C_CR_MEN | flags, &base->cr);
+	writeb(0, &base->sr);
 	udelay(100);
 
 	return ret;
 }
 
-static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
+		       slaveadd, int i2c_clk, int busnum)
 {
-	const struct fsl_i2c *dev;
 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
 	unsigned long long timeval;
 
@@ -260,23 +266,21 @@
 	*/
 	i2c_init_board();
 #endif
-	dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
-
-	writeb(0, &dev->cr);		/* stop I2C controller */
+	writeb(0, &base->cr);		/* stop I2C controller */
 	udelay(5);			/* let it shutdown in peace */
-	set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
-	writeb(slaveadd << 1, &dev->adr);/* write slave address */
-	writeb(0x0, &dev->sr);		/* clear status register */
-	writeb(I2C_CR_MEN, &dev->cr);	/* start I2C controller */
+	set_i2c_bus_speed(base, i2c_clk, speed);
+	writeb(slaveadd << 1, &base->adr);/* write slave address */
+	writeb(0x0, &base->sr);		/* clear status register */
+	writeb(I2C_CR_MEN, &base->cr);	/* start I2C controller */
 
 	timeval = get_ticks();
-	while (readb(&dev->sr) & I2C_SR_MBB) {
+	while (readb(&base->sr) & I2C_SR_MBB) {
 		if ((get_ticks() - timeval) < timeout)
 			continue;
 
-		if (fsl_i2c_fixup(dev))
+		if (fsl_i2c_fixup(base))
 			debug("i2c_init: BUS#%d failed to init\n",
-			      adap->hwadapnr);
+			      busnum);
 
 		break;
 	}
@@ -292,13 +296,12 @@
 }
 
 static int
-i2c_wait4bus(struct i2c_adapter *adap)
+i2c_wait4bus(const struct fsl_i2c_base *base)
 {
-	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
 	unsigned long long timeval = get_ticks();
 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
 
-	while (readb(&dev->sr) & I2C_SR_MBB) {
+	while (readb(&base->sr) & I2C_SR_MBB) {
 		if ((get_ticks() - timeval) > timeout)
 			return -1;
 	}
@@ -306,22 +309,21 @@
 	return 0;
 }
 
-static __inline__ int
-i2c_wait(struct i2c_adapter *adap, int write)
+static inline int
+i2c_wait(const struct fsl_i2c_base *base, int write)
 {
 	u32 csr;
 	unsigned long long timeval = get_ticks();
 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
-	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
 
 	do {
-		csr = readb(&dev->sr);
+		csr = readb(&base->sr);
 		if (!(csr & I2C_SR_MIF))
 			continue;
 		/* Read again to allow register to stabilise */
-		csr = readb(&dev->sr);
+		csr = readb(&base->sr);
 
-		writeb(0x0, &dev->sr);
+		writeb(0x0, &base->sr);
 
 		if (csr & I2C_SR_MAL) {
 			debug("i2c_wait: MAL\n");
@@ -345,203 +347,318 @@
 	return -1;
 }
 
-static __inline__ int
-i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
+static inline int
+i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, u8 dir, int rsta)
 {
-	struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
-
 	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
 	       | (rsta ? I2C_CR_RSTA : 0),
-	       &device->cr);
+	       &base->cr);
 
-	writeb((dev << 1) | dir, &device->dr);
+	writeb((dev << 1) | dir, &base->dr);
 
-	if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
+	if (i2c_wait(base, I2C_WRITE_BIT) < 0)
 		return 0;
 
 	return 1;
 }
 
-static __inline__ int
-__i2c_write(struct i2c_adapter *adap, u8 *data, int length)
+static inline int
+__i2c_write_data(const struct fsl_i2c_base *base, u8 *data, int length)
 {
-	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
 	int i;
 
 	for (i = 0; i < length; i++) {
-		writeb(data[i], &dev->dr);
+		writeb(data[i], &base->dr);
 
-		if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
+		if (i2c_wait(base, I2C_WRITE_BIT) < 0)
 			break;
 	}
 
 	return i;
 }
 
-static __inline__ int
-__i2c_read(struct i2c_adapter *adap, u8 *data, int length)
+static inline int
+__i2c_read_data(const struct fsl_i2c_base *base, u8 *data, int length)
 {
-	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
 	int i;
 
 	writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
-	       &dev->cr);
+	       &base->cr);
 
 	/* dummy read */
-	readb(&dev->dr);
+	readb(&base->dr);
 
 	for (i = 0; i < length; i++) {
-		if (i2c_wait(adap, I2C_READ_BIT) < 0)
+		if (i2c_wait(base, I2C_READ_BIT) < 0)
 			break;
 
 		/* Generate ack on last next to last byte */
 		if (i == length - 2)
 			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
-			       &dev->cr);
+			       &base->cr);
 
 		/* Do not generate stop on last byte */
 		if (i == length - 1)
 			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
-			       &dev->cr);
+			       &base->cr);
 
-		data[i] = readb(&dev->dr);
+		data[i] = readb(&base->dr);
 	}
 
 	return i;
 }
 
 static int
-fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
-	     int length)
+__i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen,
+	   u8 *data, int dlen)
 {
-	struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
-	int i = -1; /* signal error */
-	u8 *a = (u8*)&addr;
-	int len = alen * -1;
+	int ret = -1; /* signal error */
 
-	if (i2c_wait4bus(adap) < 0)
+	if (i2c_wait4bus(base) < 0)
 		return -1;
 
-	/* To handle the need of I2C devices that require to write few bytes
-	 * (more than 4 bytes of address as in the case of else part)
-	 * of data before reading, Negative equivalent of length(bytes to write)
-	 * is passed, but used the +ve part of len for writing data
+	/* Some drivers use offset lengths in excess of 4 bytes. These drivers
+	 * adhere to the following convention:
+	 * - the offset length is passed as negative (that is, the absolute
+	 *   value of olen is the actual offset length)
+	 * - the offset itself is passed in data, which is overwritten by the
+	 *   subsequent read operation
 	 */
-	if (alen < 0) {
-		/* Generate a START and send the Address and
-		 * the Tx Bytes to the slave.
-		 * "START: Address: Write bytes data[len]"
-		 * IF part supports writing any number of bytes in contrast
-		 * to the else part, which supports writing address offset
-		 * of upto 4 bytes only.
-		 * bytes that need to be written are passed in
-		 * "data", which will eventually keep the data READ,
-		 * after writing the len bytes out of it
-		 */
-		if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)
-			i = __i2c_write(adap, data, len);
+	if (olen < 0) {
+		if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
+			ret = __i2c_write_data(base, data, -olen);
 
-		if (i != len)
+		if (ret != -olen)
 			return -1;
 
-		if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)
-			i = __i2c_read(adap, data, length);
+		if (dlen && i2c_write_addr(base, chip_addr,
+					   I2C_READ_BIT, 1) != 0)
+			ret = __i2c_read_data(base, data, dlen);
 	} else {
-		if ((!length || alen > 0) &&
-		    i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0  &&
-		    __i2c_write(adap, &a[4 - alen], alen) == alen)
-			i = 0; /* No error so far */
+		if ((!dlen || olen > 0) &&
+		    i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0  &&
+		    __i2c_write_data(base, offset, olen) == olen)
+			ret = 0; /* No error so far */
 
-		if (length &&
-		    i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
-			i = __i2c_read(adap, data, length);
+		if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
+					   olen ? 1 : 0) != 0)
+			ret = __i2c_read_data(base, data, dlen);
 	}
 
-	writeb(I2C_CR_MEN, &device->cr);
+	writeb(I2C_CR_MEN, &base->cr);
 
-	if (i2c_wait4bus(adap)) /* Wait until STOP */
+	if (i2c_wait4bus(base)) /* Wait until STOP */
 		debug("i2c_read: wait4bus timed out\n");
 
-	if (i == length)
-	    return 0;
+	if (ret == dlen)
+		return 0;
 
 	return -1;
 }
 
 static int
-fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
-	      u8 *data, int length)
+__i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen,
+	    u8 *data, int dlen)
 {
-	struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
-	int i = -1; /* signal error */
-	u8 *a = (u8*)&addr;
+	int ret = -1; /* signal error */
 
-	if (i2c_wait4bus(adap) < 0)
+	if (i2c_wait4bus(base) < 0)
 		return -1;
 
-	if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
-	    __i2c_write(adap, &a[4 - alen], alen) == alen) {
-		i = __i2c_write(adap, data, length);
+	if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
+	    __i2c_write_data(base, offset, olen) == olen) {
+		ret = __i2c_write_data(base, data, dlen);
 	}
 
-	writeb(I2C_CR_MEN, &device->cr);
-	if (i2c_wait4bus(adap)) /* Wait until STOP */
+	writeb(I2C_CR_MEN, &base->cr);
+	if (i2c_wait4bus(base)) /* Wait until STOP */
 		debug("i2c_write: wait4bus timed out\n");
 
-	if (i == length)
-	    return 0;
+	if (ret == dlen)
+		return 0;
 
 	return -1;
 }
 
 static int
-fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
+__i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
 {
-	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
 	/* For unknow reason the controller will ACK when
 	 * probing for a slave with the same address, so skip
 	 * it.
 	 */
-	if (chip == (readb(&dev->adr) >> 1))
+	if (chip == (readb(&base->adr) >> 1))
 		return -1;
 
-	return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
+	return __i2c_read(base, chip, 0, 0, NULL, 0);
+}
+
+static unsigned int __i2c_set_bus_speed(const struct fsl_i2c_base *base,
+			unsigned int speed, int i2c_clk)
+{
+	writeb(0, &base->cr);		/* stop controller */
+	set_i2c_bus_speed(base, i2c_clk, speed);
+	writeb(I2C_CR_MEN, &base->cr);	/* start controller */
+
+	return 0;
+}
+
+#ifndef CONFIG_DM_I2C
+static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+{
+	__i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
+		   get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
+}
+
+static int
+fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
+{
+	return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
+}
+
+static int
+fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
+	     u8 *data, int dlen)
+{
+	u8 *o = (u8 *)&offset;
+	return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
+			  olen, data, dlen);
+}
+
+static int
+fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
+	      u8 *data, int dlen)
+{
+	u8 *o = (u8 *)&offset;
+	return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
+			   olen, data, dlen);
 }
 
 static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
-			unsigned int speed)
+					  unsigned int speed)
 {
-	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
-
-	writeb(0, &dev->cr);		/* stop controller */
-	set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
-	writeb(I2C_CR_MEN, &dev->cr);	/* start controller */
-
-	return 0;
+	return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
+				   get_i2c_clock(adap->hwadapnr));
 }
 
 /*
  * Register fsl i2c adapters
  */
-U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
 			 CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
 			 0)
 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
-U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
 			 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
 			 1)
 #endif
 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
-U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
 			 CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
 			 2)
 #endif
 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
-U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
 			 CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
 			 3)
 #endif
+#else /* CONFIG_DM_I2C */
+static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
+			      u32 chip_flags)
+{
+	struct fsl_i2c_dev *dev = dev_get_priv(bus);
+	return __i2c_probe_chip(dev->base, chip_addr);
+}
+
+static int fsl_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+	struct fsl_i2c_dev *dev = dev_get_priv(bus);
+	return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
+}
+
+static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
+{
+	struct fsl_i2c_dev *dev = dev_get_priv(bus);
+	u64 reg;
+	u32 addr, size;
+
+	reg = fdtdec_get_addr(gd->fdt_blob, bus->of_offset, "reg");
+	addr = reg >> 32;
+	size = reg & 0xFFFFFFFF;
+
+	dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
+
+	if (!dev->base)
+		return -ENOMEM;
+
+	dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+				    "cell-index", -1);
+	dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+				       "u-boot,i2c-slave-addr", 0x7f);
+	dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+				    "clock-frequency", 400000);
+
+	dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : gd->arch.i2c1_clk;
+
+	return 0;
+}
+
+static int fsl_i2c_probe(struct udevice *bus)
+{
+	struct fsl_i2c_dev *dev = dev_get_priv(bus);
+	__i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
+		   dev->index);
+	return 0;
+}
+
+static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+	struct fsl_i2c_dev *dev = dev_get_priv(bus);
+	struct i2c_msg *dmsg, *omsg, dummy;
+
+	memset(&dummy, 0, sizeof(struct i2c_msg));
+
+	/* We expect either two messages (one with an offset and one with the
+	 * actucal data) or one message (just data) */
+	if (nmsgs > 2 || nmsgs == 0) {
+		debug("%s: Only one or two messages are supported.", __func__);
+		return -1;
+	}
+
+	omsg = nmsgs == 1 ? &dummy : msg;
+	dmsg = nmsgs == 1 ? msg : msg + 1;
+
+	if (dmsg->flags & I2C_M_RD)
+		return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
+				  dmsg->buf, dmsg->len);
+	else
+		return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
+				   dmsg->buf, dmsg->len);
+}
+
+static const struct dm_i2c_ops fsl_i2c_ops = {
+	.xfer           = fsl_i2c_xfer,
+	.probe_chip     = fsl_i2c_probe_chip,
+	.set_bus_speed  = fsl_i2c_set_bus_speed,
+};
+
+static const struct udevice_id fsl_i2c_ids[] = {
+	{ .compatible = "fsl-i2c", },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(i2c_fsl) = {
+	.name = "i2c_fsl",
+	.id = UCLASS_I2C,
+	.of_match = fsl_i2c_ids,
+	.probe = fsl_i2c_probe,
+	.ofdata_to_platdata = fsl_i2c_ofdata_to_platdata,
+	.priv_auto_alloc_size = sizeof(struct fsl_i2c_dev),
+	.ops = &fsl_i2c_ops,
+};
+
+#endif /* CONFIG_DM_I2C */
diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 909cea2..5642cd9 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -112,48 +112,10 @@
 
 struct i2c_cdns_bus {
 	int id;
+	unsigned int input_freq;
 	struct cdns_i2c_regs __iomem *regs;	/* register base */
 };
 
-
-/** cdns_i2c_probe() - Probe method
- * @dev: udevice pointer
- *
- * DM callback called when device is probed
- */
-static int cdns_i2c_probe(struct udevice *dev)
-{
-	struct i2c_cdns_bus *bus = dev_get_priv(dev);
-
-	bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
-	if (!bus->regs)
-		return -ENOMEM;
-
-	/* TODO: Calculate dividers based on CPU_CLK_1X */
-	/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
-	writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
-		(2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
-
-	/* Enable master mode, ack, and 7-bit addressing */
-	setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
-		CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
-
-	debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
-
-	return 0;
-}
-
-static int cdns_i2c_remove(struct udevice *dev)
-{
-	struct i2c_cdns_bus *bus = dev_get_priv(dev);
-
-	debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
-
-	unmap_sysmem(bus->regs);
-
-	return 0;
-}
-
 /* Wait for an interrupt */
 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
 {
@@ -172,14 +134,84 @@
 	return int_status & mask;
 }
 
+#define CDNS_I2C_DIVA_MAX	4
+#define CDNS_I2C_DIVB_MAX	64
+
+static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
+		unsigned int *a, unsigned int *b)
+{
+	unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
+	unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
+	unsigned int last_error, current_error;
+
+	/* calculate (divisor_a+1) x (divisor_b+1) */
+	temp = input_clk / (22 * fscl);
+
+	/*
+	 * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
+	 * the fscl input is out of range. Return error.
+	 */
+	if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
+		return -EINVAL;
+
+	last_error = -1;
+	for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
+		div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
+
+		if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
+			continue;
+		div_b--;
+
+		actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
+
+		if (actual_fscl > fscl)
+			continue;
+
+		current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
+							(fscl - actual_fscl));
+
+		if (last_error > current_error) {
+			calc_div_a = div_a;
+			calc_div_b = div_b;
+			best_fscl = actual_fscl;
+			last_error = current_error;
+		}
+	}
+
+	*a = calc_div_a;
+	*b = calc_div_b;
+	*f = best_fscl;
+
+	return 0;
+}
+
 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 {
-	if (speed != 100000) {
-		printf("%s, failed to set clock speed to %u\n", __func__,
-		       speed);
+	struct i2c_cdns_bus *bus = dev_get_priv(dev);
+	u32 div_a = 0, div_b = 0;
+	unsigned long speed_p = speed;
+	int ret = 0;
+
+	if (speed > 400000) {
+		debug("%s, failed to set clock speed to %u\n", __func__,
+		      speed);
 		return -EINVAL;
 	}
 
+	ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
+	if (ret)
+		return ret;
+
+	debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
+	      __func__, div_a, div_b, bus->input_freq, speed, speed_p);
+
+	writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
+	       (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
+
+	/* Enable master mode, ack, and 7-bit addressing */
+	setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
+		CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
+
 	return 0;
 }
 
@@ -313,6 +345,19 @@
 	return 0;
 }
 
+static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+	struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
+
+	i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
+	if (!i2c_bus->regs)
+		return -ENOMEM;
+
+	i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */
+
+	return 0;
+}
+
 static const struct dm_i2c_ops cdns_i2c_ops = {
 	.xfer = cdns_i2c_xfer,
 	.probe_chip = cdns_i2c_probe_chip,
@@ -328,8 +373,7 @@
 	.name = "i2c-cdns",
 	.id = UCLASS_I2C,
 	.of_match = cdns_i2c_of_match,
-	.probe = cdns_i2c_probe,
-	.remove = cdns_i2c_remove,
+	.ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
 	.priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
 	.ops = &cdns_i2c_ops,
 };
diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig
index f959d9d..48900ed 100644
--- a/drivers/i2c/muxes/Kconfig
+++ b/drivers/i2c/muxes/Kconfig
@@ -24,3 +24,13 @@
 	  I2C multimaster arbitration scheme using GPIOs and a challenge &
 	  response mechanism where masters have to claim the bus by asserting
 	  a GPIO.
+
+config I2C_MUX_PCA954x
+	tristate "TI PCA954x I2C Mux/switches"
+	depends on I2C_MUX
+	help
+	  If you say yes here you get support for the TI PCA954x
+	  I2C mux/switch devices. It is x width I2C multiplexer which enables to
+	  paritioning I2C bus and connect multiple devices with the same address
+	  to the same I2C controller where driver handles proper routing to
+	  target i2c device. PCA9544 and PCA9548 are supported.
diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile
index 47c1240..0811add 100644
--- a/drivers/i2c/muxes/Makefile
+++ b/drivers/i2c/muxes/Makefile
@@ -5,3 +5,4 @@
 #
 obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o
 obj-$(CONFIG_$(SPL_)I2C_MUX) += i2c-mux-uclass.o
+obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o
diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c
new file mode 100644
index 0000000..7e0d2da
--- /dev/null
+++ b/drivers/i2c/muxes/pca954x.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2015 - 2016 Xilinx, Inc.
+ * Written by Michal Simek
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pca954x_priv {
+	u32 addr; /* I2C mux address */
+	u32 width; /* I2C mux width - number of busses */
+};
+
+static int pca954x_deselect(struct udevice *mux, struct udevice *bus,
+			    uint channel)
+{
+	struct pca954x_priv *priv = dev_get_priv(mux);
+	uchar byte = 0;
+
+	return dm_i2c_write(mux, priv->addr, &byte, 1);
+}
+
+static int pca954x_select(struct udevice *mux, struct udevice *bus,
+			  uint channel)
+{
+	struct pca954x_priv *priv = dev_get_priv(mux);
+	uchar byte = 1 << channel;
+
+	return dm_i2c_write(mux, priv->addr, &byte, 1);
+}
+
+static const struct i2c_mux_ops pca954x_ops = {
+	.select = pca954x_select,
+	.deselect = pca954x_deselect,
+};
+
+static const struct udevice_id pca954x_ids[] = {
+	{ .compatible = "nxp,pca9548", .data = (ulong)8 },
+	{ .compatible = "nxp,pca9544", .data = (ulong)4 },
+	{ }
+};
+
+static int pca954x_ofdata_to_platdata(struct udevice *dev)
+{
+	struct pca954x_priv *priv = dev_get_priv(dev);
+
+	priv->addr = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", 0);
+	if (!priv->addr) {
+		debug("MUX not found\n");
+		return -ENODEV;
+	}
+	priv->width = dev_get_driver_data(dev);
+
+	if (!priv->width) {
+		debug("No I2C MUX width specified\n");
+		return -EINVAL;
+	}
+
+	debug("Device %s at 0x%x with width %d\n",
+	      dev->name, priv->addr, priv->width);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(pca954x) = {
+	.name = "pca954x",
+	.id = UCLASS_I2C_MUX,
+	.of_match = pca954x_ids,
+	.ops = &pca954x_ops,
+	.ofdata_to_platdata = pca954x_ofdata_to_platdata,
+	.priv_auto_alloc_size = sizeof(struct pca954x_priv),
+};
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 221ff4f..bf44432 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -185,26 +185,17 @@
 }
 
 /*
- * These flags are ORed to any write to the control register
- * They allow global setting of TWSIEN and ACK.
- * By default none are set.
- * twsi_start() sets TWSIEN (in case the controller was disabled)
- * twsi_recv() sets ACK or resets it depending on expected status.
- */
-static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
-
-/*
  * Assert the START condition, either in a single I2C transaction
  * or inside back-to-back ones (repeated starts).
  */
-static int twsi_start(struct i2c_adapter *adap, int expected_status)
+static int twsi_start(struct i2c_adapter *adap, int expected_status, u8 *flags)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 
 	/* globally set TWSIEN in case it was not */
-	twsi_control_flags |= MVTWSI_CONTROL_TWSIEN;
+	*flags |= MVTWSI_CONTROL_TWSIEN;
 	/* assert START */
-	writel(twsi_control_flags | MVTWSI_CONTROL_START |
+	writel(*flags | MVTWSI_CONTROL_START |
 				    MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 	/* wait for controller to process START */
 	return twsi_wait(adap, expected_status);
@@ -213,14 +204,15 @@
 /*
  * Send a byte (i2c address or data).
  */
-static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status)
+static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status,
+		     u8 *flags)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 
 	/* put byte in data register for sending */
 	writel(byte, &twsi->data);
 	/* clear any pending interrupt -- that'll cause sending */
-	writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
+	writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 	/* wait for controller to receive byte and check ACK */
 	return twsi_wait(adap, expected_status);
 }
@@ -229,18 +221,18 @@
  * Receive a byte.
  * Global mvtwsi_control_flags variable says if we should ack or nak.
  */
-static int twsi_recv(struct i2c_adapter *adap, u8 *byte)
+static int twsi_recv(struct i2c_adapter *adap, u8 *byte, u8 *flags)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	int expected_status, status;
 
 	/* compute expected status based on ACK bit in global control flags */
-	if (twsi_control_flags & MVTWSI_CONTROL_ACK)
+	if (*flags & MVTWSI_CONTROL_ACK)
 		expected_status = MVTWSI_STATUS_DATA_R_ACK;
 	else
 		expected_status = MVTWSI_STATUS_DATA_R_NAK;
 	/* acknowledge *previous state* and launch receive */
-	writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
+	writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 	/* wait for controller to receive byte and assert ACK or NAK */
 	status = twsi_wait(adap, expected_status);
 	/* if we did receive expected byte then store it */
@@ -296,8 +288,7 @@
 static void twsi_reset(struct i2c_adapter *adap)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
-	/* ensure controller will be enabled by any twsi*() function */
-	twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
+
 	/* reset controller */
 	writel(0, &twsi->soft_reset);
 	/* wait 2 ms -- this is what the Marvell LSP does */
@@ -353,7 +344,7 @@
  * Expected address status will derive from direction bit (bit 0) in addr.
  */
 static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
-		     u8 addr)
+		     u8 addr, u8 *flags)
 {
 	int status, expected_addr_status;
 
@@ -363,10 +354,11 @@
 	else /* writing */
 		expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
 	/* assert START */
-	status = twsi_start(adap, expected_start_status);
+	status = twsi_start(adap, expected_start_status, flags);
 	/* send out the address if the start went well */
 	if (status == 0)
-		status = twsi_send(adap, addr, expected_addr_status);
+		status = twsi_send(adap, addr, expected_addr_status,
+				   flags);
 	/* return ok or status of first failure to caller */
 	return status;
 }
@@ -378,13 +370,14 @@
 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
 {
 	u8 dummy_byte;
+	u8 flags = 0;
 	int status;
 
 	/* begin i2c read */
-	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1);
+	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1, &flags);
 	/* dummy read was accepted: receive byte but NAK it. */
 	if (status == 0)
-		status = twsi_recv(adap, &dummy_byte);
+		status = twsi_recv(adap, &dummy_byte, &flags);
 	/* Stop transaction */
 	twsi_stop(adap, 0);
 	/* return 0 or status of first failure */
@@ -405,27 +398,28 @@
 			int alen, uchar *data, int length)
 {
 	int status;
+	u8 flags = 0;
 
 	/* begin i2c write to send the address bytes */
-	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
+	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
 	/* send addr bytes */
 	while ((status == 0) && alen--)
 		status = twsi_send(adap, addr >> (8*alen),
-			MVTWSI_STATUS_DATA_W_ACK);
+			MVTWSI_STATUS_DATA_W_ACK, &flags);
 	/* begin i2c read to receive eeprom data bytes */
 	if (status == 0)
 		status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
-				   (chip << 1) | 1);
+				   (chip << 1) | 1, &flags);
 	/* prepare ACK if at least one byte must be received */
 	if (length > 0)
-		twsi_control_flags |= MVTWSI_CONTROL_ACK;
+		flags |= MVTWSI_CONTROL_ACK;
 	/* now receive actual bytes */
 	while ((status == 0) && length--) {
 		/* reset NAK if we if no more to read now */
 		if (length == 0)
-			twsi_control_flags &= ~MVTWSI_CONTROL_ACK;
+			flags &= ~MVTWSI_CONTROL_ACK;
 		/* read current byte */
-		status = twsi_recv(adap, data++);
+		status = twsi_recv(adap, data++, &flags);
 	}
 	/* Stop transaction */
 	status = twsi_stop(adap, status);
@@ -441,16 +435,18 @@
 			int alen, uchar *data, int length)
 {
 	int status;
+	u8 flags = 0;
 
 	/* begin i2c write to send the eeprom adress bytes then data bytes */
-	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
+	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
 	/* send addr bytes */
 	while ((status == 0) && alen--)
 		status = twsi_send(adap, addr >> (8*alen),
-			MVTWSI_STATUS_DATA_W_ACK);
+			MVTWSI_STATUS_DATA_W_ACK, &flags);
 	/* send data bytes */
 	while ((status == 0) && (length-- > 0))
-		status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK);
+		status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK,
+				   &flags);
 	/* Stop transaction */
 	status = twsi_stop(adap, status);
 	/* return 0 or status of first failure */
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index af8667f..c40f6b5 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -138,4 +138,10 @@
 	  legacy UART or other devices in the Winbond Super IO chips
 	  on X86 platforms.
 
+config QFW
+	bool
+	help
+	  Hidden option to enable QEMU fw_cfg interface. This will be selected by
+	  either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
+
 endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 5969d34..98704f2 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -43,3 +43,4 @@
 obj-$(CONFIG_RESET) += reset-uclass.o
 obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
 obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
+obj-$(CONFIG_QFW) += qfw.o
diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c
new file mode 100644
index 0000000..d43d1d3
--- /dev/null
+++ b/drivers/misc/qfw.c
@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <malloc.h>
+#include <qfw.h>
+#include <asm/io.h>
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+#include <asm/tables.h>
+#endif
+#include <linux/list.h>
+
+static bool fwcfg_present;
+static bool fwcfg_dma_present;
+static struct fw_cfg_arch_ops *fwcfg_arch_ops;
+
+static LIST_HEAD(fw_list);
+
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+/*
+ * This function allocates memory for ACPI tables
+ *
+ * @entry : BIOS linker command entry which tells where to allocate memory
+ *          (either high memory or low memory)
+ * @addr  : The address that should be used for low memory allcation. If the
+ *          memory allocation request is 'ZONE_HIGH' then this parameter will
+ *          be ignored.
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr)
+{
+	uint32_t size, align;
+	struct fw_file *file;
+	unsigned long aligned_addr;
+
+	align = le32_to_cpu(entry->alloc.align);
+	/* align must be power of 2 */
+	if (align & (align - 1)) {
+		printf("error: wrong alignment %u\n", align);
+		return -EINVAL;
+	}
+
+	file = qemu_fwcfg_find_file(entry->alloc.file);
+	if (!file) {
+		printf("error: can't find file %s\n", entry->alloc.file);
+		return -ENOENT;
+	}
+
+	size = be32_to_cpu(file->cfg.size);
+
+	/*
+	 * ZONE_HIGH means we need to allocate from high memory, since
+	 * malloc space is already at the end of RAM, so we directly use it.
+	 * If allocation zone is ZONE_FSEG, then we use the 'addr' passed
+	 * in which is low memory
+	 */
+	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
+		aligned_addr = (unsigned long)memalign(align, size);
+		if (!aligned_addr) {
+			printf("error: allocating resource\n");
+			return -ENOMEM;
+		}
+	} else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
+		aligned_addr = ALIGN(*addr, align);
+	} else {
+		printf("error: invalid allocation zone\n");
+		return -EINVAL;
+	}
+
+	debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n",
+	      file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
+
+	qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
+			      size, (void *)aligned_addr);
+	file->addr = aligned_addr;
+
+	/* adjust address for low memory allocation */
+	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
+		*addr = (aligned_addr + size);
+
+	return 0;
+}
+
+/*
+ * This function patches ACPI tables previously loaded
+ * by bios_linker_allocate()
+ *
+ * @entry : BIOS linker command entry which tells how to patch
+ *          ACPI tables
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_add_pointer(struct bios_linker_entry *entry)
+{
+	struct fw_file *dest, *src;
+	uint32_t offset = le32_to_cpu(entry->pointer.offset);
+	uint64_t pointer = 0;
+
+	dest = qemu_fwcfg_find_file(entry->pointer.dest_file);
+	if (!dest || !dest->addr)
+		return -ENOENT;
+	src = qemu_fwcfg_find_file(entry->pointer.src_file);
+	if (!src || !src->addr)
+		return -ENOENT;
+
+	debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n",
+	      dest->addr, src->addr, offset, entry->pointer.size, pointer);
+
+	memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size);
+	pointer	= le64_to_cpu(pointer);
+	pointer += (unsigned long)src->addr;
+	pointer	= cpu_to_le64(pointer);
+	memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size);
+
+	return 0;
+}
+
+/*
+ * This function updates checksum fields of ACPI tables previously loaded
+ * by bios_linker_allocate()
+ *
+ * @entry : BIOS linker command entry which tells where to update ACPI table
+ *          checksums
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_add_checksum(struct bios_linker_entry *entry)
+{
+	struct fw_file *file;
+	uint8_t *data, cksum = 0;
+	uint8_t *cksum_start;
+
+	file = qemu_fwcfg_find_file(entry->cksum.file);
+	if (!file || !file->addr)
+		return -ENOENT;
+
+	data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset));
+	cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start));
+	cksum = table_compute_checksum(cksum_start,
+				       le32_to_cpu(entry->cksum.length));
+	*data = cksum;
+
+	return 0;
+}
+
+/* This function loads and patches ACPI tables provided by QEMU */
+u32 write_acpi_tables(u32 addr)
+{
+	int i, ret = 0;
+	struct fw_file *file;
+	struct bios_linker_entry *table_loader;
+	struct bios_linker_entry *entry;
+	uint32_t size;
+
+	/* make sure fw_list is loaded */
+	ret = qemu_fwcfg_read_firmware_list();
+	if (ret) {
+		printf("error: can't read firmware file list\n");
+		return addr;
+	}
+
+	file = qemu_fwcfg_find_file("etc/table-loader");
+	if (!file) {
+		printf("error: can't find etc/table-loader\n");
+		return addr;
+	}
+
+	size = be32_to_cpu(file->cfg.size);
+	if ((size % sizeof(*entry)) != 0) {
+		printf("error: table-loader maybe corrupted\n");
+		return addr;
+	}
+
+	table_loader = malloc(size);
+	if (!table_loader) {
+		printf("error: no memory for table-loader\n");
+		return addr;
+	}
+
+	qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
+			      size, table_loader);
+
+	for (i = 0; i < (size / sizeof(*entry)); i++) {
+		entry = table_loader + i;
+		switch (le32_to_cpu(entry->command)) {
+		case BIOS_LINKER_LOADER_COMMAND_ALLOCATE:
+			ret = bios_linker_allocate(entry, &addr);
+			if (ret)
+				goto out;
+			break;
+		case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER:
+			ret = bios_linker_add_pointer(entry);
+			if (ret)
+				goto out;
+			break;
+		case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM:
+			ret = bios_linker_add_checksum(entry);
+			if (ret)
+				goto out;
+			break;
+		default:
+			break;
+		}
+	}
+
+out:
+	if (ret) {
+		struct fw_cfg_file_iter iter;
+		for (file = qemu_fwcfg_file_iter_init(&iter);
+		     !qemu_fwcfg_file_iter_end(&iter);
+		     file = qemu_fwcfg_file_iter_next(&iter)) {
+			if (file->addr) {
+				free((void *)file->addr);
+				file->addr = 0;
+			}
+		}
+	}
+
+	free(table_loader);
+	return addr;
+}
+#endif
+
+/* Read configuration item using fw_cfg PIO interface */
+static void qemu_fwcfg_read_entry_pio(uint16_t entry,
+		uint32_t size, void *address)
+{
+	debug("qemu_fwcfg_read_entry_pio: entry 0x%x, size %u address %p\n",
+	      entry, size, address);
+
+	return fwcfg_arch_ops->arch_read_pio(entry, size, address);
+}
+
+/* Read configuration item using fw_cfg DMA interface */
+static void qemu_fwcfg_read_entry_dma(uint16_t entry,
+		uint32_t size, void *address)
+{
+	struct fw_cfg_dma_access dma;
+
+	dma.length = cpu_to_be32(size);
+	dma.address = cpu_to_be64((uintptr_t)address);
+	dma.control = cpu_to_be32(FW_CFG_DMA_READ);
+
+	/*
+	 * writting FW_CFG_INVALID will cause read operation to resume at
+	 * last offset, otherwise read will start at offset 0
+	 */
+	if (entry != FW_CFG_INVALID)
+		dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
+
+	barrier();
+
+	debug("qemu_fwcfg_read_entry_dma: entry 0x%x, size %u address %p, control 0x%x\n",
+	      entry, size, address, be32_to_cpu(dma.control));
+
+	fwcfg_arch_ops->arch_read_dma(&dma);
+}
+
+bool qemu_fwcfg_present(void)
+{
+	return fwcfg_present;
+}
+
+bool qemu_fwcfg_dma_present(void)
+{
+	return fwcfg_dma_present;
+}
+
+void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address)
+{
+	if (fwcfg_dma_present)
+		qemu_fwcfg_read_entry_dma(entry, length, address);
+	else
+		qemu_fwcfg_read_entry_pio(entry, length, address);
+}
+
+int qemu_fwcfg_online_cpus(void)
+{
+	uint16_t nb_cpus;
+
+	if (!fwcfg_present)
+		return -ENODEV;
+
+	qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
+
+	return le16_to_cpu(nb_cpus);
+}
+
+int qemu_fwcfg_read_firmware_list(void)
+{
+	int i;
+	uint32_t count;
+	struct fw_file *file;
+	struct list_head *entry;
+
+	/* don't read it twice */
+	if (!list_empty(&fw_list))
+		return 0;
+
+	qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
+	if (!count)
+		return 0;
+
+	count = be32_to_cpu(count);
+	for (i = 0; i < count; i++) {
+		file = malloc(sizeof(*file));
+		if (!file) {
+			printf("error: allocating resource\n");
+			goto err;
+		}
+		qemu_fwcfg_read_entry(FW_CFG_INVALID,
+				      sizeof(struct fw_cfg_file), &file->cfg);
+		file->addr = 0;
+		list_add_tail(&file->list, &fw_list);
+	}
+
+	return 0;
+
+err:
+	list_for_each(entry, &fw_list) {
+		file = list_entry(entry, struct fw_file, list);
+		free(file);
+	}
+
+	return -ENOMEM;
+}
+
+struct fw_file *qemu_fwcfg_find_file(const char *name)
+{
+	struct list_head *entry;
+	struct fw_file *file;
+
+	list_for_each(entry, &fw_list) {
+		file = list_entry(entry, struct fw_file, list);
+		if (!strcmp(file->cfg.name, name))
+			return file;
+	}
+
+	return NULL;
+}
+
+struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter)
+{
+	iter->entry = fw_list.next;
+	return list_entry((struct list_head *)iter->entry,
+			  struct fw_file, list);
+}
+
+struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter)
+{
+	iter->entry = ((struct list_head *)iter->entry)->next;
+	return list_entry((struct list_head *)iter->entry,
+			  struct fw_file, list);
+}
+
+bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter)
+{
+	return iter->entry == &fw_list;
+}
+
+void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops)
+{
+	uint32_t qemu;
+	uint32_t dma_enabled;
+
+	fwcfg_present = false;
+	fwcfg_dma_present = false;
+	fwcfg_arch_ops = NULL;
+
+	if (!ops || !ops->arch_read_pio || !ops->arch_read_dma)
+		return;
+	fwcfg_arch_ops = ops;
+
+	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
+	if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE)
+		fwcfg_present = true;
+
+	if (fwcfg_present) {
+		qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
+		if (dma_enabled & FW_CFG_DMA_ENABLED)
+			fwcfg_dma_present = true;
+	}
+}
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 4d3df11..c80efc3 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -2,7 +2,7 @@
 
 config MMC
 	bool "Enable MMC support"
-	depends on ARCH_SUNXI
+	depends on ARCH_SUNXI || SANDBOX
 	help
 	  TODO: Move all architectures to use this option
 
@@ -58,4 +58,13 @@
 	help
 	  This selects support for the SD/MMC Host Controller on UniPhier SoCs.
 
+config SANDBOX_MMC
+	bool "Sandbox MMC support"
+	depends on MMC && SANDBOX
+	help
+	  This select a dummy sandbox MMC driver. At present this does nothing
+	  other than allow sandbox to be build with MMC support. This
+	  improves build coverage for sandbox and makes it easier to detect
+	  MMC build errors with sandbox.
+
 endmenu
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 585aaf3..3da4817 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -5,7 +5,13 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_DM_MMC) += mmc-uclass.o
+ifdef CONFIG_DM_MMC
+obj-$(CONFIG_GENERIC_MMC) += mmc-uclass.o
+endif
+
+ifndef CONFIG_BLK
+obj-$(CONFIG_GENERIC_MMC) += mmc_legacy.o
+endif
 
 obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
 obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o
@@ -34,7 +40,11 @@
 obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
 obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
 obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
+ifdef CONFIG_BLK
+ifdef CONFIG_GENERIC_MMC
 obj-$(CONFIG_SANDBOX) += sandbox_mmc.o
+endif
+endif
 obj-$(CONFIG_SDHCI) += sdhci.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
 obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 777489f..1b967d9 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -21,6 +21,112 @@
 	return upriv->mmc;
 }
 
+#ifdef CONFIG_BLK
+struct mmc *find_mmc_device(int dev_num)
+{
+	struct udevice *dev, *mmc_dev;
+	int ret;
+
+	ret = blk_get_device(IF_TYPE_MMC, dev_num, &dev);
+
+	if (ret) {
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+		printf("MMC Device %d not found\n", dev_num);
+#endif
+		return NULL;
+	}
+
+	mmc_dev = dev_get_parent(dev);
+
+	return mmc_get_mmc_dev(mmc_dev);
+}
+
+int get_mmc_num(void)
+{
+	return max(blk_find_max_devnum(IF_TYPE_MMC), 0);
+}
+
+int mmc_get_next_devnum(void)
+{
+	int ret;
+
+	ret = get_mmc_num();
+	if (ret < 0)
+		return ret;
+
+	return ret + 1;
+}
+
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
+{
+	struct blk_desc *desc;
+	struct udevice *dev;
+
+	device_find_first_child(mmc->dev, &dev);
+	if (!dev)
+		return NULL;
+	desc = dev_get_uclass_platdata(dev);
+
+	return desc;
+}
+
+void mmc_do_preinit(void)
+{
+	struct udevice *dev;
+	struct uclass *uc;
+	int ret;
+
+	ret = uclass_get(UCLASS_MMC, &uc);
+	if (ret)
+		return;
+	uclass_foreach_dev(dev, uc) {
+		struct mmc *m = mmc_get_mmc_dev(dev);
+
+		if (!m)
+			continue;
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+		mmc_set_preinit(m, 1);
+#endif
+		if (m->preinit)
+			mmc_start_init(m);
+	}
+}
+
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+void print_mmc_devices(char separator)
+{
+	struct udevice *dev;
+	char *mmc_type;
+	bool first = true;
+
+	for (uclass_first_device(UCLASS_MMC, &dev);
+	     dev;
+	     uclass_next_device(&dev)) {
+		struct mmc *m = mmc_get_mmc_dev(dev);
+
+		if (!first) {
+			printf("%c", separator);
+			if (separator != '\n')
+				puts(" ");
+		}
+		if (m->has_init)
+			mmc_type = IS_SD(m) ? "SD" : "eMMC";
+		else
+			mmc_type = NULL;
+
+		printf("%s: %d", m->cfg->name, mmc_get_blk_desc(m)->devnum);
+		if (mmc_type)
+			printf(" (%s)", mmc_type);
+	}
+
+	printf("\n");
+}
+
+#else
+void print_mmc_devices(char separator) { }
+#endif
+#endif /* CONFIG_BLK */
+
 U_BOOT_DRIVER(mmc) = {
 	.name	= "mmc",
 	.id	= UCLASS_MMC,
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index d3c22ab..74b3d68 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -21,9 +21,6 @@
 #include <div64.h>
 #include "mmc_private.h"
 
-static struct list_head mmc_devices;
-static int cur_dev_num = -1;
-
 __weak int board_mmc_getwp(struct mmc *mmc)
 {
 	return -1;
@@ -178,25 +175,6 @@
 	return mmc_send_cmd(mmc, &cmd, NULL);
 }
 
-struct mmc *find_mmc_device(int dev_num)
-{
-	struct mmc *m;
-	struct list_head *entry;
-
-	list_for_each(entry, &mmc_devices) {
-		m = list_entry(entry, struct mmc, link);
-
-		if (m->block_dev.devnum == dev_num)
-			return m;
-	}
-
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
-	printf("MMC Device %d not found\n", dev_num);
-#endif
-
-	return NULL;
-}
-
 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 			   lbaint_t blkcnt)
 {
@@ -238,9 +216,17 @@
 	return blkcnt;
 }
 
+#ifdef CONFIG_BLK
+static ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
+		       void *dst)
+#else
 static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start,
 		       lbaint_t blkcnt, void *dst)
+#endif
 {
+#ifdef CONFIG_BLK
+	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
 	int dev_num = block_dev->devnum;
 	int err;
 	lbaint_t cur, blocks_todo = blkcnt;
@@ -252,14 +238,14 @@
 	if (!mmc)
 		return 0;
 
-	err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+	err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
 	if (err < 0)
 		return 0;
 
-	if ((start + blkcnt) > mmc->block_dev.lba) {
+	if ((start + blkcnt) > block_dev->lba) {
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 		printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
-			start + blkcnt, mmc->block_dev.lba);
+			start + blkcnt, block_dev->lba);
 #endif
 		return 0;
 	}
@@ -577,43 +563,15 @@
 		return -1;
 	}
 
-	mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
+	mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
 
 	return 0;
 }
 
-int mmc_select_hwpart(int dev_num, int hwpart)
+static int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
 {
-	struct mmc *mmc = find_mmc_device(dev_num);
 	int ret;
 
-	if (!mmc)
-		return -ENODEV;
-
-	if (mmc->block_dev.hwpart == hwpart)
-		return 0;
-
-	if (mmc->part_config == MMCPART_NOAVAILABLE) {
-		printf("Card doesn't support part_switch\n");
-		return -EMEDIUMTYPE;
-	}
-
-	ret = mmc_switch_part(dev_num, hwpart);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-
-int mmc_switch_part(int dev_num, unsigned int part_num)
-{
-	struct mmc *mmc = find_mmc_device(dev_num);
-	int ret;
-
-	if (!mmc)
-		return -1;
-
 	ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
 			 (mmc->part_config & ~PART_ACCESS_MASK)
 			 | (part_num & PART_ACCESS_MASK));
@@ -624,12 +582,55 @@
 	 */
 	if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
 		ret = mmc_set_capacity(mmc, part_num);
-		mmc->block_dev.hwpart = part_num;
+		mmc_get_blk_desc(mmc)->hwpart = part_num;
 	}
 
 	return ret;
 }
 
+#ifdef CONFIG_BLK
+static int mmc_select_hwpart(struct udevice *bdev, int hwpart)
+{
+	struct udevice *mmc_dev = dev_get_parent(bdev);
+	struct mmc *mmc = mmc_get_mmc_dev(mmc_dev);
+	struct blk_desc *desc = dev_get_uclass_platdata(bdev);
+	int ret;
+
+	if (desc->hwpart == hwpart)
+		return 0;
+
+	if (mmc->part_config == MMCPART_NOAVAILABLE)
+		return -EMEDIUMTYPE;
+
+	ret = mmc_switch_part(mmc, hwpart);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+#else
+static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart)
+{
+	struct mmc *mmc = find_mmc_device(desc->devnum);
+	int ret;
+
+	if (!mmc)
+		return -ENODEV;
+
+	if (mmc->block_dev.hwpart == hwpart)
+		return 0;
+
+	if (mmc->part_config == MMCPART_NOAVAILABLE)
+		return -EMEDIUMTYPE;
+
+	ret = mmc_switch_part(mmc, hwpart);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+#endif
+
 int mmc_hwpart_config(struct mmc *mmc,
 		      const struct mmc_hwpart_conf *conf,
 		      enum mmc_hwpart_conf_mode mode)
@@ -1039,6 +1040,7 @@
 	int timeout = 1000;
 	bool has_parts = false;
 	bool part_completed;
+	struct blk_desc *bdesc;
 
 #ifdef CONFIG_MMC_SPI_CRC_ON
 	if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
@@ -1335,7 +1337,7 @@
 		mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
 	}
 
-	err = mmc_set_capacity(mmc, mmc->block_dev.hwpart);
+	err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
 	if (err)
 		return err;
 
@@ -1475,31 +1477,32 @@
 	}
 
 	/* fill in device description */
-	mmc->block_dev.lun = 0;
-	mmc->block_dev.hwpart = 0;
-	mmc->block_dev.type = 0;
-	mmc->block_dev.blksz = mmc->read_bl_len;
-	mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
-	mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
+	bdesc = mmc_get_blk_desc(mmc);
+	bdesc->lun = 0;
+	bdesc->hwpart = 0;
+	bdesc->type = 0;
+	bdesc->blksz = mmc->read_bl_len;
+	bdesc->log2blksz = LOG2(bdesc->blksz);
+	bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
 #if !defined(CONFIG_SPL_BUILD) || \
 		(defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
 		!defined(CONFIG_USE_TINY_PRINTF))
-	sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
+	sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
 		mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
 		(mmc->cid[3] >> 16) & 0xffff);
-	sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
+	sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
 		(mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
 		(mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
 		(mmc->cid[2] >> 24) & 0xff);
-	sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
+	sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
 		(mmc->cid[2] >> 16) & 0xf);
 #else
-	mmc->block_dev.vendor[0] = 0;
-	mmc->block_dev.product[0] = 0;
-	mmc->block_dev.revision[0] = 0;
+	bdesc->vendor[0] = 0;
+	bdesc->product[0] = 0;
+	bdesc->revision[0] = 0;
 #endif
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
-	part_init(&mmc->block_dev);
+	part_init(bdesc);
 #endif
 
 	return 0;
@@ -1537,8 +1540,55 @@
 	return -1;
 }
 
+#ifdef CONFIG_BLK
+int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
+{
+	struct blk_desc *bdesc;
+	struct udevice *bdev;
+	int ret;
+
+	ret = blk_create_devicef(dev, "mmc_blk", "blk", IF_TYPE_MMC, -1, 512,
+				 0, &bdev);
+	if (ret) {
+		debug("Cannot create block device\n");
+		return ret;
+	}
+	bdesc = dev_get_uclass_platdata(bdev);
+	mmc->cfg = cfg;
+	mmc->priv = dev;
+
+	/* the following chunk was from mmc_register() */
+
+	/* Setup dsr related values */
+	mmc->dsr_imp = 0;
+	mmc->dsr = 0xffffffff;
+	/* Setup the universal parts of the block interface just once */
+	bdesc->removable = 1;
+
+	/* setup initial part type */
+	bdesc->part_type = mmc->cfg->part_type;
+	mmc->dev = dev;
+
+	return 0;
+}
+
+int mmc_unbind(struct udevice *dev)
+{
+	struct udevice *bdev;
+
+	device_find_first_child(dev, &bdev);
+	if (bdev) {
+		device_remove(bdev);
+		device_unbind(bdev);
+	}
+
+	return 0;
+}
+
+#else
 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
 {
+	struct blk_desc *bdesc;
 	struct mmc *mmc;
 
 	/* quick validation */
@@ -1559,19 +1609,17 @@
 	mmc->dsr_imp = 0;
 	mmc->dsr = 0xffffffff;
 	/* Setup the universal parts of the block interface just once */
-	mmc->block_dev.if_type = IF_TYPE_MMC;
-	mmc->block_dev.devnum = cur_dev_num++;
-	mmc->block_dev.removable = 1;
-	mmc->block_dev.block_read = mmc_bread;
-	mmc->block_dev.block_write = mmc_bwrite;
-	mmc->block_dev.block_erase = mmc_berase;
+	bdesc = mmc_get_blk_desc(mmc);
+	bdesc->if_type = IF_TYPE_MMC;
+	bdesc->removable = 1;
+	bdesc->devnum = mmc_get_next_devnum();
+	bdesc->block_read = mmc_bread;
+	bdesc->block_write = mmc_bwrite;
+	bdesc->block_erase = mmc_berase;
 
 	/* setup initial part type */
-	mmc->block_dev.part_type = mmc->cfg->part_type;
-
-	INIT_LIST_HEAD(&mmc->link);
-
-	list_add_tail(&mmc->link, &mmc_devices);
+	bdesc->part_type = mmc->cfg->part_type;
+	mmc_list_add(mmc);
 
 	return mmc;
 }
@@ -1581,15 +1629,23 @@
 	/* only freeing memory for now */
 	free(mmc);
 }
+#endif
 
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *mmc_get_dev(int dev)
+#ifndef CONFIG_BLK
+static int mmc_get_dev(int dev, struct blk_desc **descp)
 {
 	struct mmc *mmc = find_mmc_device(dev);
-	if (!mmc || mmc_init(mmc))
-		return NULL;
+	int ret;
 
-	return &mmc->block_dev;
+	if (!mmc)
+		return -ENODEV;
+	ret = mmc_init(mmc);
+	if (ret)
+		return ret;
+
+	*descp = &mmc->block_dev;
+
+	return 0;
 }
 #endif
 
@@ -1636,7 +1692,7 @@
 		return err;
 
 	/* The internal partition reset to user partition(0) at every CMD0*/
-	mmc->block_dev.hwpart = 0;
+	mmc_get_blk_desc(mmc)->hwpart = 0;
 
 	/* Test for SD version 2 */
 	err = mmc_send_if_cond(mmc);
@@ -1683,7 +1739,11 @@
 {
 	int err = 0;
 	unsigned start;
+#ifdef CONFIG_DM_MMC
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
 
+	upriv->mmc = mmc;
+#endif
 	if (mmc->has_init)
 		return 0;
 
@@ -1716,66 +1776,11 @@
 	return -1;
 }
 
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
-
-void print_mmc_devices(char separator)
-{
-	struct mmc *m;
-	struct list_head *entry;
-	char *mmc_type;
-
-	list_for_each(entry, &mmc_devices) {
-		m = list_entry(entry, struct mmc, link);
-
-		if (m->has_init)
-			mmc_type = IS_SD(m) ? "SD" : "eMMC";
-		else
-			mmc_type = NULL;
-
-		printf("%s: %d", m->cfg->name, m->block_dev.devnum);
-		if (mmc_type)
-			printf(" (%s)", mmc_type);
-
-		if (entry->next != &mmc_devices) {
-			printf("%c", separator);
-			if (separator != '\n')
-				puts (" ");
-		}
-	}
-
-	printf("\n");
-}
-
-#else
-void print_mmc_devices(char separator) { }
-#endif
-
-int get_mmc_num(void)
-{
-	return cur_dev_num;
-}
-
 void mmc_set_preinit(struct mmc *mmc, int preinit)
 {
 	mmc->preinit = preinit;
 }
 
-static void do_preinit(void)
-{
-	struct mmc *m;
-	struct list_head *entry;
-
-	list_for_each(entry, &mmc_devices) {
-		m = list_entry(entry, struct mmc, link);
-
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
-		mmc_set_preinit(m, 1);
-#endif
-		if (m->preinit)
-			mmc_start_init(m);
-	}
-}
-
 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
 static int mmc_probe(bd_t *bis)
 {
@@ -1828,9 +1833,9 @@
 		return 0;
 	initialized = 1;
 
-	INIT_LIST_HEAD (&mmc_devices);
-	cur_dev_num = 0;
-
+#ifndef CONFIG_BLK
+	mmc_list_init();
+#endif
 	ret = mmc_probe(bis);
 	if (ret)
 		return ret;
@@ -1839,7 +1844,7 @@
 	print_mmc_devices(',');
 #endif
 
-	do_preinit();
+	mmc_do_preinit();
 	return 0;
 }
 
@@ -1965,3 +1970,25 @@
 			  enable);
 }
 #endif
+
+#ifdef CONFIG_BLK
+static const struct blk_ops mmc_blk_ops = {
+	.read	= mmc_bread,
+	.write	= mmc_bwrite,
+	.select_hwpart	= mmc_select_hwpart,
+};
+
+U_BOOT_DRIVER(mmc_blk) = {
+	.name		= "mmc_blk",
+	.id		= UCLASS_BLK,
+	.ops		= &mmc_blk_ops,
+};
+#else
+U_BOOT_LEGACY_BLK(mmc) = {
+	.if_typename	= "mmc",
+	.if_type	= IF_TYPE_MMC,
+	.max_devs	= -1,
+	.get_dev	= mmc_get_dev,
+	.select_hwpart	= mmc_select_hwpartp,
+};
+#endif
diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c
new file mode 100644
index 0000000..3ec649f
--- /dev/null
+++ b/drivers/mmc/mmc_legacy.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+
+static struct list_head mmc_devices;
+static int cur_dev_num = -1;
+
+struct mmc *find_mmc_device(int dev_num)
+{
+	struct mmc *m;
+	struct list_head *entry;
+
+	list_for_each(entry, &mmc_devices) {
+		m = list_entry(entry, struct mmc, link);
+
+		if (m->block_dev.devnum == dev_num)
+			return m;
+	}
+
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+	printf("MMC Device %d not found\n", dev_num);
+#endif
+
+	return NULL;
+}
+
+int mmc_get_next_devnum(void)
+{
+	return cur_dev_num++;
+}
+
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
+{
+	return &mmc->block_dev;
+}
+
+int get_mmc_num(void)
+{
+	return cur_dev_num;
+}
+
+void mmc_do_preinit(void)
+{
+	struct mmc *m;
+	struct list_head *entry;
+
+	list_for_each(entry, &mmc_devices) {
+		m = list_entry(entry, struct mmc, link);
+
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+		mmc_set_preinit(m, 1);
+#endif
+		if (m->preinit)
+			mmc_start_init(m);
+	}
+}
+
+void mmc_list_init(void)
+{
+	INIT_LIST_HEAD(&mmc_devices);
+	cur_dev_num = 0;
+}
+
+void mmc_list_add(struct mmc *mmc)
+{
+	INIT_LIST_HEAD(&mmc->link);
+
+	list_add_tail(&mmc->link, &mmc_devices);
+}
+
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+void print_mmc_devices(char separator)
+{
+	struct mmc *m;
+	struct list_head *entry;
+	char *mmc_type;
+
+	list_for_each(entry, &mmc_devices) {
+		m = list_entry(entry, struct mmc, link);
+
+		if (m->has_init)
+			mmc_type = IS_SD(m) ? "SD" : "eMMC";
+		else
+			mmc_type = NULL;
+
+		printf("%s: %d", m->cfg->name, m->block_dev.devnum);
+		if (mmc_type)
+			printf(" (%s)", mmc_type);
+
+		if (entry->next != &mmc_devices) {
+			printf("%c", separator);
+			if (separator != '\n')
+				puts(" ");
+		}
+	}
+
+	printf("\n");
+}
+
+#else
+void print_mmc_devices(char separator) { }
+#endif
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index d3f6bfe..27b9e5f 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -25,8 +25,13 @@
 unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start,
 			 lbaint_t blkcnt);
 
-unsigned long mmc_bwrite(struct blk_desc *block_dev, lbaint_t start,
-			 lbaint_t blkcnt, const void *src);
+#ifdef CONFIG_BLK
+ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
+		 const void *src);
+#else
+ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
+		 const void *src);
+#endif
 
 #else /* CONFIG_SPL_BUILD */
 
@@ -46,4 +51,28 @@
 
 #endif /* CONFIG_SPL_BUILD */
 
+/**
+ * mmc_get_next_devnum() - Get the next available MMC device number
+ *
+ * @return next available device number (0 = first), or -ve on error
+ */
+int mmc_get_next_devnum(void);
+
+/**
+ * mmc_do_preinit() - Get an MMC device ready for use
+ */
+void mmc_do_preinit(void);
+
+/**
+ * mmc_list_init() - Set up the list of MMC devices
+ */
+void mmc_list_init(void);
+
+/**
+ * mmc_list_add() - Add a new MMC device to the list of devices
+ *
+ * @mmc:	Device to add
+ */
+void mmc_list_add(struct mmc *mmc);
+
 #endif /* _MMC_PRIVATE_H_ */
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index 7b186f8..0f8b5c7 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -9,6 +9,7 @@
 
 #include <config.h>
 #include <common.h>
+#include <dm.h>
 #include <part.h>
 #include <div64.h>
 #include <linux/math64.h>
@@ -78,7 +79,8 @@
 	if (!mmc)
 		return -1;
 
-	err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+	err = blk_select_hwpart_devnum(IF_TYPE_MMC, dev_num,
+				       block_dev->hwpart);
 	if (err < 0)
 		return -1;
 
@@ -121,9 +123,9 @@
 	struct mmc_data data;
 	int timeout = 1000;
 
-	if ((start + blkcnt) > mmc->block_dev.lba) {
+	if ((start + blkcnt) > mmc_get_blk_desc(mmc)->lba) {
 		printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
-		       start + blkcnt, mmc->block_dev.lba);
+		       start + blkcnt, mmc_get_blk_desc(mmc)->lba);
 		return 0;
 	}
 
@@ -171,9 +173,17 @@
 	return blkcnt;
 }
 
+#ifdef CONFIG_BLK
+ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
+		 const void *src)
+#else
 ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
 		 const void *src)
+#endif
 {
+#ifdef CONFIG_BLK
+	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
 	int dev_num = block_dev->devnum;
 	lbaint_t cur, blocks_todo = blkcnt;
 	int err;
@@ -182,7 +192,7 @@
 	if (!mmc)
 		return 0;
 
-	err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+	err = blk_select_hwpart_devnum(IF_TYPE_MMC, dev_num, block_dev->hwpart);
 	if (err < 0)
 		return 0;
 
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 85a832b..be34057 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -825,6 +825,7 @@
 	gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
 #endif
 
+	mmc->dev = dev;
 	upriv->mmc = mmc;
 
 	return 0;
diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c
index e03d6dd..abe7429 100644
--- a/drivers/mmc/pic32_sdhci.c
+++ b/drivers/mmc/pic32_sdhci.c
@@ -41,7 +41,12 @@
 		return ret;
 	}
 
-	return add_sdhci(host, f_min_max[1], f_min_max[0]);
+	ret = add_sdhci(host, f_min_max[1], f_min_max[0]);
+	if (ret)
+		return ret;
+	host->mmc->dev = dev;
+
+	return 0;
 }
 
 static const struct udevice_id pic32_sdhci_ids[] = {
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index cb9e104..0a261c5 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -104,6 +104,7 @@
 	if (ret)
 		return ret;
 
+	host->mmc->dev = dev;
 	upriv->mmc = host->mmc;
 
 	return 0;
diff --git a/drivers/mmc/sandbox_mmc.c b/drivers/mmc/sandbox_mmc.c
index f4646a8..7da059c 100644
--- a/drivers/mmc/sandbox_mmc.c
+++ b/drivers/mmc/sandbox_mmc.c
@@ -8,18 +8,150 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
+#include <fdtdec.h>
 #include <mmc.h>
 #include <asm/test.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct sandbox_mmc_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
+/**
+ * sandbox_mmc_send_cmd() - Emulate SD commands
+ *
+ * This emulate an SD card version 2. Single-block reads result in zero data.
+ * Multiple-block reads return a test string.
+ */
+static int sandbox_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+				struct mmc_data *data)
+{
+	switch (cmd->cmdidx) {
+	case MMC_CMD_ALL_SEND_CID:
+		break;
+	case SD_CMD_SEND_RELATIVE_ADDR:
+		cmd->response[0] = 0 << 16; /* mmc->rca */
+	case MMC_CMD_GO_IDLE_STATE:
+		break;
+	case SD_CMD_SEND_IF_COND:
+		cmd->response[0] = 0xaa;
+		break;
+	case MMC_CMD_SEND_STATUS:
+		cmd->response[0] = MMC_STATUS_RDY_FOR_DATA;
+		break;
+	case MMC_CMD_SELECT_CARD:
+		break;
+	case MMC_CMD_SEND_CSD:
+		cmd->response[0] = 0;
+		cmd->response[1] = 10 << 16;	/* 1 << block_len */
+		break;
+	case SD_CMD_SWITCH_FUNC: {
+		u32 *resp = (u32 *)data->dest;
+
+		resp[7] = cpu_to_be32(SD_HIGHSPEED_BUSY);
+		break;
+	}
+	case MMC_CMD_READ_SINGLE_BLOCK:
+		memset(data->dest, '\0', data->blocksize);
+		break;
+	case MMC_CMD_READ_MULTIPLE_BLOCK:
+		strcpy(data->dest, "this is a test");
+		break;
+	case MMC_CMD_STOP_TRANSMISSION:
+		break;
+	case SD_CMD_APP_SEND_OP_COND:
+		cmd->response[0] = OCR_BUSY | OCR_HCS;
+		cmd->response[1] = 0;
+		cmd->response[2] = 0;
+		break;
+	case MMC_CMD_APP_CMD:
+		break;
+	case MMC_CMD_SET_BLOCKLEN:
+		debug("block len %d\n", cmd->cmdarg);
+		break;
+	case SD_CMD_APP_SEND_SCR: {
+		u32 *scr = (u32 *)data->dest;
+
+		scr[0] = cpu_to_be32(2 << 24 | 1 << 15);  /* SD version 3 */
+		break;
+	}
+	default:
+		debug("%s: Unknown command %d\n", __func__, cmd->cmdidx);
+		break;
+	}
+
+	return 0;
+}
+
+static void sandbox_mmc_set_ios(struct mmc *mmc)
+{
+}
+
+static int sandbox_mmc_init(struct mmc *mmc)
+{
+	return 0;
+}
+
+static int sandbox_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+static const struct mmc_ops sandbox_mmc_ops = {
+	.send_cmd = sandbox_mmc_send_cmd,
+	.set_ios = sandbox_mmc_set_ios,
+	.init = sandbox_mmc_init,
+	.getcd = sandbox_mmc_getcd,
+};
+
+int sandbox_mmc_probe(struct udevice *dev)
+{
+	struct sandbox_mmc_plat *plat = dev_get_platdata(dev);
+
+	return mmc_init(&plat->mmc);
+}
+
+int sandbox_mmc_bind(struct udevice *dev)
+{
+	struct sandbox_mmc_plat *plat = dev_get_platdata(dev);
+	struct mmc_config *cfg = &plat->cfg;
+	int ret;
+
+	cfg->name = dev->name;
+	cfg->ops = &sandbox_mmc_ops;
+	cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT;
+	cfg->voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
+	cfg->f_min = 1000000;
+	cfg->f_max = 52000000;
+	cfg->b_max = U32_MAX;
+
+	ret = mmc_bind(dev, &plat->mmc, cfg);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int sandbox_mmc_unbind(struct udevice *dev)
+{
+	mmc_unbind(dev);
+
+	return 0;
+}
+
 static const struct udevice_id sandbox_mmc_ids[] = {
 	{ .compatible = "sandbox,mmc" },
 	{ }
 };
 
-U_BOOT_DRIVER(warm_mmc_sandbox) = {
+U_BOOT_DRIVER(mmc_sandbox) = {
 	.name		= "mmc_sandbox",
 	.id		= UCLASS_MMC,
 	.of_match	= sandbox_mmc_ids,
+	.bind		= sandbox_mmc_bind,
+	.unbind		= sandbox_mmc_unbind,
+	.probe		= sandbox_mmc_probe,
+	.platdata_auto_alloc_size = sizeof(struct sandbox_mmc_plat),
 };
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 097db81..6a0e971 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -108,6 +108,7 @@
 		return ret;
 
 	upriv->mmc = host->mmc;
+	host->mmc->dev = dev;
 
 	return 0;
 }
diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index 81a80cd..4978cca 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -725,6 +725,7 @@
 		return -EIO;
 
 	upriv->mmc = priv->mmc;
+	priv->mmc->dev = dev;
 
 	return 0;
 }
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index b59feca..d405929 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -35,6 +35,7 @@
 		  CONFIG_ZYNQ_SDHCI_MIN_FREQ);
 
 	upriv->mmc = host->mmc;
+	host->mmc->dev = dev;
 
 	return 0;
 }
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index c58841e..390e9e4 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -28,6 +28,13 @@
 	  NOR flash to parallel flash interface. Please find details on the
 	  "Embedded Peripherals IP User Guide" of Altera.
 
+config FLASH_PIC32
+	bool "Microchip PIC32 Flash driver"
+	depends on MACH_PIC32 && MTD
+	help
+	  This enables access to Microchip PIC32 internal non-CFI flash
+	  chips through PIC32 Non-Volatile-Memory Controller.
+
 endmenu
 
 source "drivers/mtd/nand/Kconfig"
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 703700a..bd680a7 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -19,5 +19,6 @@
 obj-$(CONFIG_FTSMC020) += ftsmc020.o
 obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
 obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
+obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o
 obj-$(CONFIG_ST_SMI) += st_smi.o
 obj-$(CONFIG_STM32_FLASH) += stm32_flash.o
diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c
new file mode 100644
index 0000000..9166fcd
--- /dev/null
+++ b/drivers/mtd/pic32_flash.c
@@ -0,0 +1,444 @@
+/*
+ * Copyright (C) 2015
+ * Cristian Birsan <cristian.birsan@microchip.com>
+ * Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <flash.h>
+#include <mach/pic32.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* NVM Controller registers */
+struct pic32_reg_nvm {
+	struct pic32_reg_atomic ctrl;
+	struct pic32_reg_atomic key;
+	struct pic32_reg_atomic addr;
+	struct pic32_reg_atomic data;
+};
+
+/* NVM operations */
+#define NVMOP_NOP		0
+#define NVMOP_WORD_WRITE	1
+#define NVMOP_PAGE_ERASE	4
+
+/* NVM control bits */
+#define NVM_WR			BIT(15)
+#define NVM_WREN		BIT(14)
+#define NVM_WRERR		BIT(13)
+#define NVM_LVDERR		BIT(12)
+
+/* NVM programming unlock register */
+#define LOCK_KEY		0x0
+#define UNLOCK_KEY1		0xaa996655
+#define UNLOCK_KEY2		0x556699aa
+
+/*
+ * PIC32 flash banks consist of number of pages, each page
+ * into number of rows and rows into number of words.
+ * Here we will maintain page information instead of sector.
+ */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+static struct pic32_reg_nvm *nvm_regs_p;
+
+static inline void flash_initiate_operation(u32 nvmop)
+{
+	/* set operation */
+	writel(nvmop, &nvm_regs_p->ctrl.raw);
+
+	/* enable flash write */
+	writel(NVM_WREN, &nvm_regs_p->ctrl.set);
+
+	/* unlock sequence */
+	writel(LOCK_KEY, &nvm_regs_p->key.raw);
+	writel(UNLOCK_KEY1, &nvm_regs_p->key.raw);
+	writel(UNLOCK_KEY2, &nvm_regs_p->key.raw);
+
+	/* initiate operation */
+	writel(NVM_WR, &nvm_regs_p->ctrl.set);
+}
+
+static int flash_wait_till_busy(const char *func, ulong timeout)
+{
+	int ret = wait_for_bit(__func__, &nvm_regs_p->ctrl.raw,
+			       NVM_WR, false, timeout, false);
+
+	return ret ? ERR_TIMOUT : ERR_OK;
+}
+
+static inline int flash_complete_operation(void)
+{
+	u32 tmp;
+
+	tmp = readl(&nvm_regs_p->ctrl.raw);
+	if (tmp & NVM_WRERR) {
+		printf("Error in Block Erase - Lock Bit may be set!\n");
+		flash_initiate_operation(NVMOP_NOP);
+		return ERR_PROTECTED;
+	}
+
+	if (tmp & NVM_LVDERR) {
+		printf("Error in Block Erase - low-vol detected!\n");
+		flash_initiate_operation(NVMOP_NOP);
+		return ERR_NOT_ERASED;
+	}
+
+	/* disable flash write or erase operation */
+	writel(NVM_WREN, &nvm_regs_p->ctrl.clr);
+
+	return ERR_OK;
+}
+
+/*
+ * Erase flash sectors, returns:
+ * ERR_OK - OK
+ * ERR_INVAL - invalid sector arguments
+ * ERR_TIMOUT - write timeout
+ * ERR_NOT_ERASED - Flash not erased
+ * ERR_UNKNOWN_FLASH_VENDOR - incorrect flash
+ */
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	ulong sect_start, sect_end, flags;
+	int prot, sect;
+	int rc;
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MCHP) {
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf("- no sectors to erase\n");
+		return ERR_INVAL;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	else
+		printf("\n");
+
+	/* erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			continue;
+
+		/* disable interrupts */
+		flags = disable_interrupts();
+
+		/* write destination page address (physical) */
+		sect_start = CPHYSADDR(info->start[sect]);
+		writel(sect_start, &nvm_regs_p->addr.raw);
+
+		/* page erase */
+		flash_initiate_operation(NVMOP_PAGE_ERASE);
+
+		/* wait */
+		rc = flash_wait_till_busy(__func__,
+					  CONFIG_SYS_FLASH_ERASE_TOUT);
+
+		/* re-enable interrupts if necessary */
+		if (flags)
+			enable_interrupts();
+
+		if (rc != ERR_OK)
+			return rc;
+
+		rc = flash_complete_operation();
+		if (rc != ERR_OK)
+			return rc;
+
+		/*
+		 * flash content is updated but cache might contain stale
+		 * data, so invalidate dcache.
+		 */
+		sect_end = info->start[sect] + info->size / info->sector_count;
+		invalidate_dcache_range(info->start[sect], sect_end);
+	}
+
+	printf(" done\n");
+	return ERR_OK;
+}
+
+int page_erase(flash_info_t *info, int sect)
+{
+	return 0;
+}
+
+/* Write a word to flash */
+static int write_word(flash_info_t *info, ulong dest, ulong word)
+{
+	ulong flags;
+	int rc;
+
+	/* read flash to check if it is sufficiently erased */
+	if ((readl((void __iomem *)dest) & word) != word) {
+		printf("Error, Flash not erased!\n");
+		return ERR_NOT_ERASED;
+	}
+
+	/* disable interrupts */
+	flags = disable_interrupts();
+
+	/* update destination page address (physical) */
+	writel(CPHYSADDR(dest), &nvm_regs_p->addr.raw);
+	writel(word, &nvm_regs_p->data.raw);
+
+	/* word write */
+	flash_initiate_operation(NVMOP_WORD_WRITE);
+
+	/* wait for operation to complete */
+	rc = flash_wait_till_busy(__func__, CONFIG_SYS_FLASH_WRITE_TOUT);
+
+	/* re-enable interrupts if necessary */
+	if (flags)
+		enable_interrupts();
+
+	if (rc != ERR_OK)
+		return rc;
+
+	return flash_complete_operation();
+}
+
+/*
+ * Copy memory to flash, returns:
+ * ERR_OK - OK
+ * ERR_TIMOUT - write timeout
+ * ERR_NOT_ERASED - Flash not erased
+ */
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong dst, tmp_le, len = cnt;
+	int i, l, rc;
+	uchar *cp;
+
+	/* get lower word aligned address */
+	dst = (addr & ~3);
+
+	/* handle unaligned start bytes */
+	l = addr - dst;
+	if (l != 0) {
+		tmp_le = 0;
+		for (i = 0, cp = (uchar *)dst; i < l; ++i, ++cp)
+			tmp_le |= *cp << (i * 8);
+
+		for (; (i < 4) && (cnt > 0); ++i, ++src, --cnt, ++cp)
+			tmp_le |= *src << (i * 8);
+
+		for (; (cnt == 0) && (i < 4); ++i, ++cp)
+			tmp_le |= *cp << (i * 8);
+
+		rc = write_word(info, dst, tmp_le);
+		if (rc)
+			goto out;
+
+		dst += 4;
+	}
+
+	/* handle word aligned part */
+	while (cnt >= 4) {
+		tmp_le = src[0] | src[1] << 8 | src[2] << 16 | src[3] << 24;
+		rc = write_word(info, dst, tmp_le);
+		if (rc)
+			goto out;
+		src += 4;
+		dst += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		rc = ERR_OK;
+		goto out;
+	}
+
+	/* handle unaligned tail bytes */
+	tmp_le = 0;
+	for (i = 0, cp = (uchar *)dst; (i < 4) && (cnt > 0); ++i, ++cp) {
+		tmp_le |= *src++ << (i * 8);
+		--cnt;
+	}
+
+	for (; i < 4; ++i, ++cp)
+		tmp_le |= *cp << (i * 8);
+
+	rc = write_word(info, dst, tmp_le);
+out:
+	/*
+	 * flash content updated by nvm controller but CPU cache might
+	 * have stale data, so invalidate dcache.
+	 */
+	invalidate_dcache_range(addr, addr + len);
+
+	printf(" done\n");
+	return rc;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_MCHP:
+		printf("Microchip Technology ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_MCHP100T:
+		printf("Internal (8 Mbit, 64 x 16k)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+
+		printf(" %08lX%s", info->start[i],
+		       info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long size = 0;
+	struct udevice *dev;
+	int bank;
+
+	/* probe every MTD device */
+	for (uclass_first_device(UCLASS_MTD, &dev); dev;
+	     uclass_next_device(&dev)) {
+		/* nop */
+	}
+
+	/* calc total flash size */
+	for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank)
+		size += flash_info[bank].size;
+
+	return size;
+}
+
+static void pic32_flash_bank_init(flash_info_t *info,
+				  ulong base, ulong size)
+{
+	ulong sect_size;
+	int sect;
+
+	/* device & manufacturer code */
+	info->flash_id = FLASH_MAN_MCHP | FLASH_MCHP100T;
+	info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	info->size = size;
+
+	/* update sector (i.e page) info */
+	sect_size = info->size / info->sector_count;
+	for (sect = 0; sect < info->sector_count; sect++) {
+		info->start[sect] = base;
+		/* protect each sector by default */
+		info->protect[sect] = 1;
+		base += sect_size;
+	}
+}
+
+static int pic32_flash_probe(struct udevice *dev)
+{
+	void *blob = (void *)gd->fdt_blob;
+	int node = dev->of_offset;
+	const char *list, *end;
+	const fdt32_t *cell;
+	unsigned long addr, size;
+	int parent, addrc, sizec;
+	flash_info_t *info;
+	int len, idx;
+
+	/*
+	 * decode regs. there are multiple reg tuples, and they need to
+	 * match with reg-names.
+	 */
+	parent = fdt_parent_offset(blob, node);
+	of_bus_default_count_cells(blob, parent, &addrc, &sizec);
+	list = fdt_getprop(blob, node, "reg-names", &len);
+	if (!list)
+		return -ENOENT;
+
+	end = list + len;
+	cell = fdt_getprop(blob, node, "reg", &len);
+	if (!cell)
+		return -ENOENT;
+
+	for (idx = 0, info = &flash_info[0]; list < end;) {
+		addr = fdt_translate_address((void *)blob, node, cell + idx);
+		size = fdt_addr_to_cpu(cell[idx + addrc]);
+		len = strlen(list);
+		if (!strncmp(list, "nvm", len)) {
+			/* NVM controller */
+			nvm_regs_p = ioremap(addr, size);
+		} else if (!strncmp(list, "bank", 4)) {
+			/* Flash bank: use kseg0 cached address */
+			pic32_flash_bank_init(info, CKSEG0ADDR(addr), size);
+			info++;
+		}
+		idx += addrc + sizec;
+		list += len + 1;
+	}
+
+	/* disable flash write/erase operations */
+	writel(NVM_WREN, &nvm_regs_p->ctrl.clr);
+
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		      &flash_info[0]);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+		      &flash_info[0]);
+#endif
+	return 0;
+}
+
+static const struct udevice_id pic32_flash_ids[] = {
+	{ .compatible = "microchip,pic32mzda-flash" },
+	{}
+};
+
+U_BOOT_DRIVER(pic32_flash) = {
+	.name	= "pic32_flash",
+	.id	= UCLASS_MTD,
+	.of_match = pic32_flash_ids,
+	.probe	= pic32_flash_probe,
+};
diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
index ca56fe9..46c98a9 100644
--- a/drivers/mtd/spi/spi_spl_load.c
+++ b/drivers/mtd/spi/spi_spl_load.c
@@ -23,6 +23,8 @@
 static int spi_load_image_os(struct spi_flash *flash,
 			     struct image_header *header)
 {
+	int err;
+
 	/* Read for a header, parse or error out. */
 	spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, 0x40,
 		       (void *)header);
@@ -30,7 +32,9 @@
 	if (image_get_magic(header) != IH_MAGIC)
 		return -1;
 
-	spl_parse_image_header(header);
+	err = spl_parse_image_header(header);
+	if (err)
+		return err;
 
 	spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS,
 		       spl_image.size, (void *)spl_image.load_addr);
@@ -81,7 +85,9 @@
 		if (err)
 			return err;
 
-		spl_parse_image_header(header);
+		err = spl_parse_image_header(header);
+		if (err)
+			return err;
 		err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
 			       spl_image.size, (void *)spl_image.load_addr);
 	}
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index fbedd04..d5e4a97 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -59,7 +59,7 @@
 obj-$(CONFIG_SMC911X) += smc911x.o
 obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
 obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
-obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
+obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o
 obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
 obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o
 obj-$(CONFIG_ULI526X) += uli526x.o
diff --git a/drivers/net/cpsw-common.c b/drivers/net/cpsw-common.c
new file mode 100644
index 0000000..e828e85
--- /dev/null
+++ b/drivers/net/cpsw-common.c
@@ -0,0 +1,121 @@
+/*
+ * CPSW common - libs used across TI ethernet devices.
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <cpsw.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CTRL_MAC_REG(offset, id) ((offset) + 0x8 * (id))
+
+static int davinci_emac_3517_get_macid(struct udevice *dev, u16 offset,
+				       int slave, u8 *mac_addr)
+{
+	void *fdt = (void *)gd->fdt_blob;
+	int node = dev->of_offset;
+	u32 macid_lsb;
+	u32 macid_msb;
+	fdt32_t gmii = 0;
+	int syscon;
+	u32 addr;
+
+	syscon = fdtdec_lookup_phandle(fdt, node, "syscon");
+	if (syscon < 0) {
+		error("Syscon offset not found\n");
+		return -ENOENT;
+	}
+
+	addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii),
+				sizeof(u32), MAP_NOCACHE);
+	if (addr == FDT_ADDR_T_NONE) {
+		error("Not able to get syscon address to get mac efuse address\n");
+		return -ENOENT;
+	}
+
+	addr += CTRL_MAC_REG(offset, slave);
+
+	/* try reading mac address from efuse */
+	macid_lsb = readl(addr);
+	macid_msb = readl(addr + 4);
+
+	mac_addr[0] = (macid_msb >> 16) & 0xff;
+	mac_addr[1] = (macid_msb >> 8)  & 0xff;
+	mac_addr[2] = macid_msb & 0xff;
+	mac_addr[3] = (macid_lsb >> 16) & 0xff;
+	mac_addr[4] = (macid_lsb >> 8)  & 0xff;
+	mac_addr[5] = macid_lsb & 0xff;
+
+	return 0;
+}
+
+static int cpsw_am33xx_cm_get_macid(struct udevice *dev, u16 offset, int slave,
+				    u8 *mac_addr)
+{
+	void *fdt = (void *)gd->fdt_blob;
+	int node = dev->of_offset;
+	u32 macid_lo;
+	u32 macid_hi;
+	fdt32_t gmii = 0;
+	int syscon;
+	u32 addr;
+
+	syscon = fdtdec_lookup_phandle(fdt, node, "syscon");
+	if (syscon < 0) {
+		error("Syscon offset not found\n");
+		return -ENOENT;
+	}
+
+	addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii),
+				sizeof(u32), MAP_NOCACHE);
+	if (addr == FDT_ADDR_T_NONE) {
+		error("Not able to get syscon address to get mac efuse address\n");
+		return -ENOENT;
+	}
+
+	addr += CTRL_MAC_REG(offset, slave);
+
+	/* try reading mac address from efuse */
+	macid_lo = readl(addr);
+	macid_hi = readl(addr + 4);
+
+	mac_addr[5] = (macid_lo >> 8) & 0xff;
+	mac_addr[4] = macid_lo & 0xff;
+	mac_addr[3] = (macid_hi >> 24) & 0xff;
+	mac_addr[2] = (macid_hi >> 16) & 0xff;
+	mac_addr[1] = (macid_hi >> 8) & 0xff;
+	mac_addr[0] = macid_hi & 0xff;
+
+	return 0;
+}
+
+int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr)
+{
+	if (of_machine_is_compatible("ti,dm8148"))
+		return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+	if (of_machine_is_compatible("ti,am33xx"))
+		return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+	if (of_device_is_compatible(dev, "ti,am3517-emac"))
+		return davinci_emac_3517_get_macid(dev, 0x110, slave, mac_addr);
+
+	if (of_device_is_compatible(dev, "ti,dm816-emac"))
+		return cpsw_am33xx_cm_get_macid(dev, 0x30, slave, mac_addr);
+
+	if (of_machine_is_compatible("ti,am4372"))
+		return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+	if (of_machine_is_compatible("ti,dra7"))
+		return davinci_emac_3517_get_macid(dev, 0x514, slave, mac_addr);
+
+	dev_err(dev, "incompatible machine/device type for reading mac address\n");
+	return -ENOENT;
+}
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 7104754..2ce4ec6 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -26,6 +26,7 @@
 #include <phy.h>
 #include <asm/arch/cpu.h>
 #include <dm.h>
+#include <fdt_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -965,6 +966,11 @@
 	phydev->supported &= supported;
 	phydev->advertising = phydev->supported;
 
+#ifdef CONFIG_DM_ETH
+	if (slave->data->phy_of_handle)
+		phydev->dev->of_offset = slave->data->phy_of_handle;
+#endif
+
 	priv->phydev = phydev;
 	phy_config(phydev);
 
@@ -1137,6 +1143,11 @@
 	.stop		= cpsw_eth_stop,
 };
 
+static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
+{
+	return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL);
+}
+
 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
@@ -1146,9 +1157,8 @@
 	int node = dev->of_offset;
 	int subnode;
 	int slave_index = 0;
-	uint32_t mac_hi, mac_lo;
-	fdt32_t gmii = 0;
 	int active_slave;
+	int ret;
 
 	pdata->iobase = dev_get_addr(dev);
 	priv->data.version = CPSW_CTRL_VERSION_2;
@@ -1202,29 +1212,52 @@
 
 		name = fdt_get_name(fdt, subnode, &len);
 		if (!strncmp(name, "mdio", 4)) {
-			priv->data.mdio_base = fdtdec_get_addr(fdt, subnode,
-							       "reg");
+			u32 mdio_base;
+
+			mdio_base = cpsw_get_addr_by_node(fdt, subnode);
+			if (mdio_base == FDT_ADDR_T_NONE) {
+				error("Not able to get MDIO address space\n");
+				return -ENOENT;
+			}
+			priv->data.mdio_base = mdio_base;
 		}
 
 		if (!strncmp(name, "slave", 5)) {
 			u32 phy_id[2];
 
-			if (slave_index >= priv->data.slaves) {
-				printf("error: num slaves and slave nodes did not match\n");
-				return -EINVAL;
-			}
+			if (slave_index >= priv->data.slaves)
+				continue;
 			phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
 			if (phy_mode)
 				priv->data.slave_data[slave_index].phy_if =
 					phy_get_interface_by_name(phy_mode);
-			fdtdec_get_int_array(fdt, subnode, "phy_id", phy_id, 2);
-			priv->data.slave_data[slave_index].phy_addr = phy_id[1];
+
+			priv->data.slave_data[slave_index].phy_of_handle =
+				fdtdec_lookup_phandle(fdt, subnode,
+						      "phy-handle");
+
+			if (priv->data.slave_data[slave_index].phy_of_handle >= 0) {
+				priv->data.slave_data[slave_index].phy_addr =
+						fdtdec_get_int(gd->fdt_blob,
+							       priv->data.slave_data[slave_index].phy_of_handle,
+							       "reg", -1);
+			} else {
+				fdtdec_get_int_array(fdt, subnode, "phy_id",
+						     phy_id, 2);
+				priv->data.slave_data[slave_index].phy_addr =
+						phy_id[1];
+			}
 			slave_index++;
 		}
 
 		if (!strncmp(name, "cpsw-phy-sel", 12)) {
-			priv->data.gmii_sel = fdtdec_get_addr(fdt, subnode,
-							      "reg");
+			priv->data.gmii_sel = cpsw_get_addr_by_node(fdt,
+								    subnode);
+
+			if (priv->data.gmii_sel == FDT_ADDR_T_NONE) {
+				error("Not able to get gmii_sel reg address\n");
+				return -ENOENT;
+			}
 		}
 	}
 
@@ -1236,20 +1269,11 @@
 		priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
 	}
 
-	subnode = fdtdec_lookup_phandle(fdt, node, "syscon");
-	priv->data.mac_id = fdt_translate_address((void *)fdt, subnode, &gmii);
-	priv->data.mac_id += AM335X_GMII_SEL_OFFSET;
-	priv->data.mac_id += active_slave * 8;
-
-	/* try reading mac address from efuse */
-	mac_lo = readl(priv->data.mac_id);
-	mac_hi = readl(priv->data.mac_id + 4);
-	pdata->enetaddr[0] = mac_hi & 0xFF;
-	pdata->enetaddr[1] = (mac_hi & 0xFF00) >> 8;
-	pdata->enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
-	pdata->enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
-	pdata->enetaddr[4] = mac_lo & 0xFF;
-	pdata->enetaddr[5] = (mac_lo & 0xFF00) >> 8;
+	ret = ti_cm_get_macid(dev, active_slave, pdata->enetaddr);
+	if (ret < 0) {
+		error("cpsw read efuse mac failed\n");
+		return ret;
+	}
 
 	pdata->phy_interface = priv->data.slave_data[active_slave].phy_if;
 	if (pdata->phy_interface == -1) {
@@ -1270,6 +1294,7 @@
 		writel(RGMII_MODE_ENABLE, priv->data.gmii_sel);
 		break;
 	}
+
 	return 0;
 }
 
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 4b2808e..9871cc3 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -84,11 +84,14 @@
 
 static int bcm54xx_startup(struct phy_device *phydev)
 {
-	/* Read the Status (2x to make sure link is right) */
-	genphy_update_link(phydev);
-	bcm54xx_parse_status(phydev);
+	int ret;
 
-	return 0;
+	/* Read the Status (2x to make sure link is right) */
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return bcm54xx_parse_status(phydev);
 }
 
 /* Broadcom BCM5482S */
@@ -139,11 +142,14 @@
 
 static int bcm_cygnus_startup(struct phy_device *phydev)
 {
-	/* Read the Status (2x to make sure link is right) */
-	genphy_update_link(phydev);
-	genphy_parse_link(phydev);
+	int ret;
 
-	return 0;
+	/* Read the Status (2x to make sure link is right) */
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return genphy_parse_link(phydev);
 }
 
 static int bcm_cygnus_config(struct phy_device *phydev)
@@ -239,17 +245,21 @@
  */
 static int bcm5482_startup(struct phy_device *phydev)
 {
+	int ret;
+
 	if (bcm5482_is_serdes(phydev)) {
 		bcm5482_parse_serdes_sr(phydev);
 		phydev->port = PORT_FIBRE;
-	} else {
-		/* Wait for auto-negotiation to complete or fail */
-		genphy_update_link(phydev);
-		/* Parse BCM54xx copper aux status register */
-		bcm54xx_parse_status(phydev);
+		return 0;
 	}
 
-	return 0;
+	/* Wait for auto-negotiation to complete or fail */
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	/* Parse BCM54xx copper aux status register */
+	return bcm54xx_parse_status(phydev);
 }
 
 static struct phy_driver BCM5461S_driver = {
diff --git a/drivers/net/phy/davicom.c b/drivers/net/phy/davicom.c
index 0c039fe..0a6e410 100644
--- a/drivers/net/phy/davicom.c
+++ b/drivers/net/phy/davicom.c
@@ -60,10 +60,13 @@
 
 static int dm9161_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	dm9161_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return dm9161_parse_status(phydev);
 }
 
 static struct phy_driver DM9161_driver = {
diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c
index 70c15e2..2fe0132 100644
--- a/drivers/net/phy/et1011c.c
+++ b/drivers/net/phy/et1011c.c
@@ -79,9 +79,13 @@
 
 static int et1011c_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	et1011c_parse_status(phydev);
-	return 0;
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return et1011c_parse_status(phydev);
 }
 
 static struct phy_driver et1011c_driver = {
diff --git a/drivers/net/phy/lxt.c b/drivers/net/phy/lxt.c
index 91838ce..9abc2a8 100644
--- a/drivers/net/phy/lxt.c
+++ b/drivers/net/phy/lxt.c
@@ -49,10 +49,13 @@
 
 static int lxt971_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	lxt971_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return lxt971_parse_status(phydev);
 }
 
 static struct phy_driver LXT971_driver = {
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index b8b1157..d2e68d4 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -103,7 +103,7 @@
 /* Parse the 88E1011's status register for speed and duplex
  * information
  */
-static uint m88e1xxx_parse_status(struct phy_device *phydev)
+static int m88e1xxx_parse_status(struct phy_device *phydev)
 {
 	unsigned int speed;
 	unsigned int mii_reg;
@@ -120,7 +120,7 @@
 			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 				puts(" TIMEOUT !\n");
 				phydev->link = 0;
-				break;
+				return -ETIMEDOUT;
 			}
 
 			if ((i++ % 1000) == 0)
@@ -162,10 +162,13 @@
 
 static int m88e1011s_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	m88e1xxx_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return m88e1xxx_parse_status(phydev);
 }
 
 /* Marvell 88E1111S */
@@ -349,22 +352,21 @@
 	/* Change Page Number */
 	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
 
-	genphy_config_aneg(phydev);
-
-	phy_reset(phydev);
-
-	return 0;
+	return genphy_config_aneg(phydev);
 }
 
 static int m88e1118_startup(struct phy_device *phydev)
 {
+	int ret;
+
 	/* Change Page Number */
 	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
 
-	genphy_update_link(phydev);
-	m88e1xxx_parse_status(phydev);
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
 
-	return 0;
+	return m88e1xxx_parse_status(phydev);
 }
 
 /* Marvell 88E1121R */
@@ -421,12 +423,15 @@
 
 static int m88e1145_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
 	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
 			MIIM_88E1145_PHY_LED_DIRECT);
-	m88e1xxx_parse_status(phydev);
-
-	return 0;
+	return m88e1xxx_parse_status(phydev);
 }
 
 /* Marvell 88E1149S */
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 8fcf737..b08788a 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -181,7 +181,12 @@
 static int ksz90xx_startup(struct phy_device *phydev)
 {
 	unsigned phy_ctl;
-	genphy_update_link(phydev);
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
 	phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
 
 	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
index 302abe8..74d5609 100644
--- a/drivers/net/phy/mv88e61xx.c
+++ b/drivers/net/phy/mv88e61xx.c
@@ -1,4 +1,9 @@
 /*
+ * (C) Copyright 2015
+ * Elecsys Corporation <www.elecsyscorp.com>
+ * Kevin Smith <kevin.smith@elecsyscorp.com>
+ *
+ * Original driver:
  * (C) Copyright 2009
  * Marvell Semiconductor <www.marvell.com>
  * Prafulla Wadaskar <prafulla@marvell.com>
@@ -6,532 +11,1007 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+/*
+ * PHY driver for mv88e61xx ethernet switches.
+ *
+ * This driver configures the mv88e61xx for basic use as a PHY.  The switch
+ * supports a VLAN configuration that determines how traffic will be routed
+ * between the ports.  This driver uses a simple configuration that routes
+ * traffic from each PHY port only to the CPU port, and from the CPU port to
+ * any PHY port.
+ *
+ * The configuration determines which PHY ports to activate using the
+ * CONFIG_MV88E61XX_PHY_PORTS bitmask.  Setting bit 0 will activate port 0, bit
+ * 1 activates port 1, etc.  Do not set the bit for the port the CPU is
+ * connected to unless it is connected over a PHY interface (not MII).
+ *
+ * This driver was written for and tested on the mv88e6176 with an SGMII
+ * connection.  Other configurations should be supported, but some additions or
+ * changes may be required.
+ */
+
 #include <common.h>
+
+#include <bitfield.h>
+#include <errno.h>
+#include <malloc.h>
+#include <miiphy.h>
 #include <netdev.h>
-#include "mv88e61xx.h"
+
+#define PHY_AUTONEGOTIATE_TIMEOUT	5000
+
+#define PORT_COUNT			7
+#define PORT_MASK			((1 << PORT_COUNT) - 1)
+
+/* Device addresses */
+#define DEVADDR_PHY(p)			(p)
+#define DEVADDR_PORT(p)			(0x10 + (p))
+#define DEVADDR_SERDES			0x0F
+#define DEVADDR_GLOBAL_1		0x1B
+#define DEVADDR_GLOBAL_2		0x1C
+
+/* SMI indirection registers for multichip addressing mode */
+#define SMI_CMD_REG			0x00
+#define SMI_DATA_REG			0x01
+
+/* Global registers */
+#define GLOBAL1_STATUS			0x00
+#define GLOBAL1_CTRL			0x04
+#define GLOBAL1_MON_CTRL		0x1A
+
+/* Global 2 registers */
+#define GLOBAL2_REG_PHY_CMD		0x18
+#define GLOBAL2_REG_PHY_DATA		0x19
+
+/* Port registers */
+#define PORT_REG_STATUS			0x00
+#define PORT_REG_PHYS_CTRL		0x01
+#define PORT_REG_SWITCH_ID		0x03
+#define PORT_REG_CTRL			0x04
+#define PORT_REG_VLAN_MAP		0x06
+#define PORT_REG_VLAN_ID		0x07
+
+/* Phy registers */
+#define PHY_REG_CTRL1			0x10
+#define PHY_REG_STATUS1			0x11
+#define PHY_REG_PAGE			0x16
+
+/* Serdes registers */
+#define SERDES_REG_CTRL_1		0x10
+
+/* Phy page numbers */
+#define PHY_PAGE_COPPER			0
+#define PHY_PAGE_SERDES			1
+
+/* Register fields */
+#define GLOBAL1_CTRL_SWRESET		BIT(15)
+
+#define GLOBAL1_MON_CTRL_CPUDEST_SHIFT	4
+#define GLOBAL1_MON_CTRL_CPUDEST_WIDTH	4
+
+#define PORT_REG_STATUS_LINK		BIT(11)
+#define PORT_REG_STATUS_DUPLEX		BIT(10)
+
+#define PORT_REG_STATUS_SPEED_SHIFT	8
+#define PORT_REG_STATUS_SPEED_WIDTH	2
+#define PORT_REG_STATUS_SPEED_10	0
+#define PORT_REG_STATUS_SPEED_100	1
+#define PORT_REG_STATUS_SPEED_1000	2
+
+#define PORT_REG_STATUS_CMODE_MASK		0xF
+#define PORT_REG_STATUS_CMODE_100BASE_X		0x8
+#define PORT_REG_STATUS_CMODE_1000BASE_X	0x9
+#define PORT_REG_STATUS_CMODE_SGMII		0xa
+
+#define PORT_REG_PHYS_CTRL_LINK_VALUE	BIT(5)
+#define PORT_REG_PHYS_CTRL_LINK_FORCE	BIT(4)
+
+#define PORT_REG_CTRL_PSTATE_SHIFT	0
+#define PORT_REG_CTRL_PSTATE_WIDTH	2
+
+#define PORT_REG_VLAN_ID_DEF_VID_SHIFT	0
+#define PORT_REG_VLAN_ID_DEF_VID_WIDTH	12
+
+#define PORT_REG_VLAN_MAP_TABLE_SHIFT	0
+#define PORT_REG_VLAN_MAP_TABLE_WIDTH	11
+
+#define SERDES_REG_CTRL_1_FORCE_LINK	BIT(10)
+
+#define PHY_REG_CTRL1_ENERGY_DET_SHIFT	8
+#define PHY_REG_CTRL1_ENERGY_DET_WIDTH	2
+
+/* Field values */
+#define PORT_REG_CTRL_PSTATE_DISABLED	0
+#define PORT_REG_CTRL_PSTATE_FORWARD	3
+
+#define PHY_REG_CTRL1_ENERGY_DET_OFF	0
+#define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY	2
+#define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT	3
+
+/* PHY Status Register */
+#define PHY_REG_STATUS1_SPEED		0xc000
+#define PHY_REG_STATUS1_GBIT		0x8000
+#define PHY_REG_STATUS1_100		0x4000
+#define PHY_REG_STATUS1_DUPLEX		0x2000
+#define PHY_REG_STATUS1_SPDDONE		0x0800
+#define PHY_REG_STATUS1_LINK		0x0400
+#define PHY_REG_STATUS1_ENERGY		0x0010
 
 /*
- * Uncomment either of the following line for local debug control;
- * otherwise global debug control will apply.
+ * Macros for building commands for indirect addressing modes.  These are valid
+ * for both the indirect multichip addressing mode and the PHY indirection
+ * required for the writes to any PHY register.
  */
+#define SMI_BUSY			BIT(15)
+#define SMI_CMD_CLAUSE_22		BIT(12)
+#define SMI_CMD_CLAUSE_22_OP_READ	(2 << 10)
+#define SMI_CMD_CLAUSE_22_OP_WRITE	(1 << 10)
 
-/* #undef DEBUG */
-/* #define DEBUG */
+#define SMI_CMD_READ			(SMI_BUSY | SMI_CMD_CLAUSE_22 | \
+					 SMI_CMD_CLAUSE_22_OP_READ)
+#define SMI_CMD_WRITE			(SMI_BUSY | SMI_CMD_CLAUSE_22 | \
+					 SMI_CMD_CLAUSE_22_OP_WRITE)
 
-#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-/* Chip Address mode
- * The Switch support two modes of operation
- * 1. single chip mode and
- * 2. Multi-chip mode
- * Refer section 9.2 &9.3 in chip datasheet-02 for more details
- *
- * By default single chip mode is configured
- * multichip mode operation can be configured in board header
- */
-static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
-{
-	u16 reg = 0;
-	u32 timeout = MV88E61XX_PHY_TIMEOUT;
+#define SMI_CMD_ADDR_SHIFT		5
+#define SMI_CMD_ADDR_WIDTH		5
+#define SMI_CMD_REG_SHIFT		0
+#define SMI_CMD_REG_WIDTH		5
 
-	/* Poll till SMIBusy bit is clear */
-	do {
-		miiphy_read(name, devaddr, 0x0, &reg);
-		if (timeout-- == 0) {
-			printf("SMI busy timeout\n");
-			return -1;
-		}
-	} while (reg & (1 << 15));
-	return 0;
-}
-
-static void mv88e61xx_switch_write(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 data)
-{
-	u16 mii_dev_addr;
-
-	/* command to read PHY dev address */
-	if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
-		printf("Error..could not read PHY dev address\n");
-		return;
-	}
-	mv88e61xx_busychk_multic(name, mii_dev_addr);
-	/* Write data to Switch indirect data register */
-	miiphy_write(name, mii_dev_addr, 0x1, data);
-	/* Write command to Switch indirect command register (write) */
-	miiphy_write(name, mii_dev_addr, 0x0,
-		     reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
-									 15));
-}
-
-static void mv88e61xx_switch_read(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 *data)
-{
-	u16 mii_dev_addr;
-
-	/* command to read PHY dev address */
-	if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
-		printf("Error..could not read PHY dev address\n");
-		return;
-	}
-	mv88e61xx_busychk_multic(name, mii_dev_addr);
-	/* Write command to Switch indirect command register (read) */
-	miiphy_write(name, mii_dev_addr, 0x0,
-		     reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 <<
-									 15));
-	mv88e61xx_busychk_multic(name, mii_dev_addr);
-	/* Read data from Switch indirect data register */
-	miiphy_read(name, mii_dev_addr, 0x1, data);
-}
-#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
-
-/*
- * Convenience macros for switch device/port reads/writes
- * These macros output valid 'mv88e61xx' U_BOOT_CMDs
- */
-
-#ifndef DEBUG
-#define WR_SWITCH_REG wr_switch_reg
-#define RD_SWITCH_REG rd_switch_reg
-#define WR_SWITCH_PORT_REG(n, p, r, d) \
-	WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
-#define RD_SWITCH_PORT_REG(n, p, r, d) \
-	RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
-#else
-static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data)
-{
-	printf("mv88e61xx %s dev %02x reg %02x write %04x\n",
-		name, dev_adr, reg_ofs, data);
-	wr_switch_reg(name, dev_adr, reg_ofs, data);
-}
-static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data)
-{
-	rd_switch_reg(name, dev_adr, reg_ofs, data);
-	printf("mv88e61xx %s dev %02x reg %02x read %04x\n",
-		name, dev_adr, reg_ofs, *data);
-}
-static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
-	u16 data)
-{
-	printf("mv88e61xx %s port %02x reg %02x write %04x\n",
-		name, prt_adr, reg_ofs, data);
-	wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
-}
-static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
-	u16 *data)
-{
-	rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
-	printf("mv88e61xx %s port %02x reg %02x read %04x\n",
-		name, prt_adr, reg_ofs, *data);
-}
+/* Check for required macros */
+#ifndef CONFIG_MV88E61XX_PHY_PORTS
+#error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
+	to activate
+#endif
+#ifndef CONFIG_MV88E61XX_CPU_PORT
+#error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
 #endif
 
-/*
- * Local functions to read/write registers on the switch PHYs.
- * NOTE! This goes through switch, not direct miiphy, writes and reads!
- */
+/* ID register values for different switch models */
+#define PORT_SWITCH_ID_6172		0x1720
+#define PORT_SWITCH_ID_6176		0x1760
+#define PORT_SWITCH_ID_6240		0x2400
+#define PORT_SWITCH_ID_6352		0x3520
 
-/*
- * Make sure SMIBusy bit cleared before another
- * SMI operation can take place
- */
-static int mv88e61xx_busychk(char *name)
+struct mv88e61xx_phy_priv {
+	struct mii_dev *mdio_bus;
+	int smi_addr;
+	int id;
+};
+
+static inline int smi_cmd(int cmd, int addr, int reg)
 {
-	u16 reg = 0;
-	u32 timeout = MV88E61XX_PHY_TIMEOUT;
+	cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
+			       addr);
+	cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
+	return cmd;
+}
+
+static inline int smi_cmd_read(int addr, int reg)
+{
+	return smi_cmd(SMI_CMD_READ, addr, reg);
+}
+
+static inline int smi_cmd_write(int addr, int reg)
+{
+	return smi_cmd(SMI_CMD_WRITE, addr, reg);
+}
+
+__weak int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+	return 0;
+}
+
+/* Wait for the current SMI indirect command to complete */
+static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
+{
+	int val;
+	u32 timeout = 100;
+
 	do {
-		rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR,
-		       MV88E61XX_PHY_CMD, &reg);
-		if (timeout-- == 0) {
-			printf("SMI busy timeout\n");
-			return -1;
-		}
-	} while (reg & 1 << 15);	/* busy mask */
-	return 0;
-}
+		val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
+		if (val >= 0 && (val & SMI_BUSY) == 0)
+			return 0;
 
-static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy,
-	u32 reg, u16 data)
-{
-	/* write switch data reg then cmd reg then check completion */
-	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA,
-		data);
-	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
-		(MV88E61XX_PHY_WRITE_CMD | (phy << 5)  | reg));
-	return mv88e61xx_busychk(name);
-}
+		mdelay(1);
+	} while (--timeout);
 
-static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy,
-	u32 reg, u16 *data)
-{
-	/* write switch cmd reg, check for completion */
-	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
-		(MV88E61XX_PHY_READ_CMD | (phy << 5)  | reg));
-	if (mv88e61xx_busychk(name))
-		return -1;
-	/* read switch data reg and return success */
-	rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data);
-	return 0;
+	puts("SMI busy timeout\n");
+	return -ETIMEDOUT;
 }
 
 /*
- * Convenience macros for switch PHY reads/writes
- */
-
-#ifndef DEBUG
-#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write
-#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read
-#else
-static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 data)
-{
-	int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data);
-	if (r)
-		printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n",
-			name, phy_adr, reg_ofs);
-	else
-		printf("mv88e61xx %s phy %02x reg %02x write %04x\n",
-			name, phy_adr, reg_ofs, data);
-	return r;
-}
-static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 *data)
-{
-	int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data);
-	if (r)
-		printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n",
-			name, phy_adr, reg_ofs);
-	else
-		printf("mv88e61xx %s phy %02x reg %02x read %04x\n",
-			name, phy_adr, reg_ofs, *data);
-	return r;
-}
-#endif
-
-static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig)
-{
-	u32 prt;
-	u16 reg;
-	char *name = swconfig->name;
-	u32 port_mask = swconfig->ports_enabled;
-
-	/* apply internal vlan config */
-	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
-		/* only for enabled ports */
-		if ((1 << prt) & port_mask) {
-			/* take vlan map from swconfig */
-			u8 vlanmap = swconfig->vlancfg[prt];
-			/* remove disabled ports from vlan map */
-			vlanmap &= swconfig->ports_enabled;
-			/* apply vlan map to port */
-			RD_SWITCH_PORT_REG(name, prt,
-				MV88E61XX_PRT_VMAP_REG, &reg);
-			reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1);
-			reg |= vlanmap;
-			WR_SWITCH_PORT_REG(name, prt,
-				MV88E61XX_PRT_VMAP_REG, reg);
-		}
-	}
-}
-
-/*
- * Power up the specified port and reset PHY
- */
-static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy)
-{
-	char *name = swconfig->name;
-
-	/* Write Copper Specific control reg1 (0x10) for-
-	 * Enable Phy power up
-	 * Energy Detect on (sense&Xmit NLP Periodically
-	 * reset other settings default
-	 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360))
-		return -1;
-
-	/* Write PHY ctrl reg (0x0) to apply
-	 * Phy reset (set bit 15 low)
-	 * reset other default values
-	 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140))
-		return -1;
-
-	return 0;
-}
-
-/*
- * Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3)
- * is set to "On-1000Mb/s Link, Off Else"
- * This function sets it to "On-Link, Blink-Activity, Off-NoLink"
+ * The mv88e61xx has three types of addresses: the smi bus address, the device
+ * address, and the register address.  The smi bus address distinguishes it on
+ * the smi bus from other PHYs or switches.  The device address determines
+ * which on-chip register set you are reading/writing (the various PHYs, their
+ * associated ports, or global configuration registers).  The register address
+ * is the offset of the register you are reading/writing.
  *
- * This is optional settings may be needed on some boards
- * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s
- * Link status
+ * When the mv88e61xx is hardware configured to have address zero, it behaves in
+ * single-chip addressing mode, where it responds to all SMI addresses, using
+ * the smi address as its device address.  This obviously only works when this
+ * is the only chip on the SMI bus.  This allows the driver to access device
+ * registers without using indirection.  When the chip is configured to a
+ * non-zero address, it only responds to that SMI address and requires indirect
+ * writes to access the different device addresses.
  */
-static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy)
+static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
 {
-	char *name = swconfig->name;
+	struct mv88e61xx_phy_priv *priv = phydev->priv;
+	struct mii_dev *mdio_bus = priv->mdio_bus;
+	int smi_addr = priv->smi_addr;
+	int res;
 
-	if (swconfig->led_init != MV88E61XX_LED_INIT_EN)
-		return 0;
+	/* In single-chip mode, the device can be addressed directly */
+	if (smi_addr == 0)
+		return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
 
-	/* set page address to 3 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003))
-		return -1;
+	/* Wait for the bus to become free */
+	res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+	if (res < 0)
+		return res;
 
-	/*
-	 * set LED Func Ctrl reg
-	 * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink
-	 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001))
-		return -1;
+	/* Issue the read command */
+	res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
+			 smi_cmd_read(dev, reg));
+	if (res < 0)
+		return res;
 
-	/* set page address to 0 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000))
-		return -1;
+	/* Wait for the read command to complete */
+	res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+	if (res < 0)
+		return res;
+
+	/* Read the data */
+	res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
+	if (res < 0)
+		return res;
+
+	return bitfield_extract(res, 0, 16);
+}
+
+/* See the comment above mv88e61xx_reg_read */
+static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
+			       u16 val)
+{
+	struct mv88e61xx_phy_priv *priv = phydev->priv;
+	struct mii_dev *mdio_bus = priv->mdio_bus;
+	int smi_addr = priv->smi_addr;
+	int res;
+
+	/* In single-chip mode, the device can be addressed directly */
+	if (smi_addr == 0) {
+		return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
+				val);
+	}
+
+	/* Wait for the bus to become free */
+	res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+	if (res < 0)
+		return res;
+
+	/* Set the data to write */
+	res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
+				SMI_DATA_REG, val);
+	if (res < 0)
+		return res;
+
+	/* Issue the write command */
+	res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
+				smi_cmd_write(dev, reg));
+	if (res < 0)
+		return res;
+
+	/* Wait for the write command to complete */
+	res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+	if (res < 0)
+		return res;
 
 	return 0;
 }
 
-/*
- * Reverse Transmit polarity for Media Dependent Interface
- * Pins (MDIP) bits in Copper Specific Control Register 3
- * (Page 0, Reg 20 for each phy (except cpu port)
- * Reference: Section 1.1 Switch datasheet-3
- *
- * This is optional settings may be needed on some boards
- * for PHY<->magnetics h/w tuning
- */
-static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy)
+static int mv88e61xx_phy_wait(struct phy_device *phydev)
 {
-	char *name = swconfig->name;
+	int val;
+	u32 timeout = 100;
 
-	if (swconfig->mdip != MV88E61XX_MDIP_REVERSE)
-		return 0;
+	do {
+		val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
+					 GLOBAL2_REG_PHY_CMD);
+		if (val >= 0 && (val & SMI_BUSY) == 0)
+			return 0;
 
-	/*Reverse MDIP/N[3:0] bits */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f))
-		return -1;
+		mdelay(1);
+	} while (--timeout);
 
-	return 0;
+	return -ETIMEDOUT;
 }
 
-/*
- * Marvell 88E61XX Switch initialization
- */
-int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
+static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
+		int devad, int reg)
 {
-	u32 prt;
-	u16 reg;
-	char *idstr;
-	char *name = swconfig->name;
-	int time;
+	struct phy_device *phydev;
+	int res;
 
-	if (miiphy_set_current_dev(name)) {
-		printf("%s failed\n", __FUNCTION__);
-		return -1;
+	phydev = (struct phy_device *)smi_wrapper->priv;
+
+	/* Issue command to read */
+	res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+				  GLOBAL2_REG_PHY_CMD,
+				  smi_cmd_read(dev, reg));
+
+	/* Wait for data to be read */
+	res = mv88e61xx_phy_wait(phydev);
+	if (res < 0)
+		return res;
+
+	/* Read retrieved data */
+	return mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
+				  GLOBAL2_REG_PHY_DATA);
+}
+
+static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
+		int devad, int reg, u16 data)
+{
+	struct phy_device *phydev;
+	int res;
+
+	phydev = (struct phy_device *)smi_wrapper->priv;
+
+	/* Set the data to write */
+	res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+				  GLOBAL2_REG_PHY_DATA, data);
+	if (res < 0)
+		return res;
+	/* Issue the write command */
+	res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+				  GLOBAL2_REG_PHY_CMD,
+				  smi_cmd_write(dev, reg));
+	if (res < 0)
+		return res;
+
+	/* Wait for command to complete */
+	return mv88e61xx_phy_wait(phydev);
+}
+
+/* Wrapper function to make calls to phy_read_indirect simpler */
+static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
+{
+	return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
+					   MDIO_DEVAD_NONE, reg);
+}
+
+/* Wrapper function to make calls to phy_read_indirect simpler */
+static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
+		int reg, u16 val)
+{
+	return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
+					    MDIO_DEVAD_NONE, reg, val);
+}
+
+static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
+{
+	return mv88e61xx_reg_read(phydev, DEVADDR_PORT(port), reg);
+}
+
+static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
+								u16 val)
+{
+	return mv88e61xx_reg_write(phydev, DEVADDR_PORT(port), reg, val);
+}
+
+static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
+{
+	return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
+}
+
+static int mv88e61xx_get_switch_id(struct phy_device *phydev)
+{
+	int res;
+
+	res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
+	if (res < 0)
+		return res;
+	return res & 0xfff0;
+}
+
+static bool mv88e61xx_6352_family(struct phy_device *phydev)
+{
+	struct mv88e61xx_phy_priv *priv = phydev->priv;
+
+	switch (priv->id) {
+	case PORT_SWITCH_ID_6172:
+	case PORT_SWITCH_ID_6176:
+	case PORT_SWITCH_ID_6240:
+	case PORT_SWITCH_ID_6352:
+		return true;
+	}
+	return false;
+}
+
+static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
+{
+	int res;
+
+	res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
+	if (res < 0)
+		return res;
+	return res & PORT_REG_STATUS_CMODE_MASK;
+}
+
+static int mv88e61xx_parse_status(struct phy_device *phydev)
+{
+	unsigned int speed;
+	unsigned int mii_reg;
+
+	mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
+
+	if ((mii_reg & PHY_REG_STATUS1_LINK) &&
+	    !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
+		int i = 0;
+
+		puts("Waiting for PHY realtime link");
+		while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
+			/* Timeout reached ? */
+			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+				puts(" TIMEOUT !\n");
+				phydev->link = 0;
+				break;
+			}
+
+			if ((i++ % 1000) == 0)
+				putc('.');
+			udelay(1000);
+			mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
+					PHY_REG_STATUS1);
+		}
+		puts(" done\n");
+		udelay(500000);	/* another 500 ms (results in faster booting) */
+	} else {
+		if (mii_reg & PHY_REG_STATUS1_LINK)
+			phydev->link = 1;
+		else
+			phydev->link = 0;
 	}
 
-	if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) {
-		swconfig->cpuport = (1 << 5);
-		printf("Invalid cpu port config, using default port5\n");
-	}
+	if (mii_reg & PHY_REG_STATUS1_DUPLEX)
+		phydev->duplex = DUPLEX_FULL;
+	else
+		phydev->duplex = DUPLEX_HALF;
 
-	RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, &reg);
-	switch (reg &= 0xfff0) {
-	case 0x1610:
-		idstr = "88E6161";
+	speed = mii_reg & PHY_REG_STATUS1_SPEED;
+
+	switch (speed) {
+	case PHY_REG_STATUS1_GBIT:
+		phydev->speed = SPEED_1000;
 		break;
-	case 0x1650:
-		idstr = "88E6165";
-		break;
-	case 0x1210:
-		idstr = "88E6123";
-		/* ports 2,3,4 not available */
-		swconfig->ports_enabled &= 0x023;
+	case PHY_REG_STATUS1_100:
+		phydev->speed = SPEED_100;
 		break;
 	default:
-		/* Could not detect switch id */
-		idstr = "88E61??";
+		phydev->speed = SPEED_10;
 		break;
 	}
 
-	/* be sure all ports are disabled */
-	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
-		RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, &reg);
-		reg &= ~0x3;
-		WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg);
+	return 0;
+}
+
+static int mv88e61xx_switch_reset(struct phy_device *phydev)
+{
+	int time;
+	int val;
+	u8 port;
+
+	/* Disable all ports */
+	for (port = 0; port < PORT_COUNT; port++) {
+		val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
+		if (val < 0)
+			return val;
+		val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
+				       PORT_REG_CTRL_PSTATE_WIDTH,
+				       PORT_REG_CTRL_PSTATE_DISABLED);
+		val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
+		if (val < 0)
+			return val;
 	}
 
-	/* wait 2 ms for queues to drain */
+	/* Wait 2 ms for queues to drain */
 	udelay(2000);
 
-	/* reset switch */
-	RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, &reg);
-	reg |= 0x8000;
-	WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg);
+	/* Reset switch */
+	val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_CTRL);
+	if (val < 0)
+		return val;
+	val |= GLOBAL1_CTRL_SWRESET;
+	val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
+				     GLOBAL1_CTRL, val);
+	if (val < 0)
+		return val;
 
-	/* wait up to 1 second for switch reset complete */
+	/* Wait up to 1 second for switch reset complete */
 	for (time = 1000; time; time--) {
-		RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR,
-			&reg);
-		if ((reg & 0xc800) == 0xc800)
+		val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1,
+					    GLOBAL1_CTRL);
+		if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
 			break;
 		udelay(1000);
 	}
 	if (!time)
-		return -1;
+		return -ETIMEDOUT;
 
-	/* Port based VLANs configuration */
-	mv88e61xx_port_vlan_config(swconfig);
-
-	if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
-		/*
-		 * Enable RGMII delay on Tx and Rx for CPU port
-		 * Ref: sec 9.5 of chip datasheet-02
-		 */
-		/*Force port link down */
-		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10);
-		/* configure port RGMII delay */
-		WR_SWITCH_PORT_REG(name, 4,
-			MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7);
-		RD_SWITCH_PORT_REG(name, 5,
-			MV88E61XX_RGMII_TIMECTRL_REG, &reg);
-		WR_SWITCH_PORT_REG(name, 5,
-			MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18);
-		WR_SWITCH_PORT_REG(name, 4,
-			MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
-		/* Force port to RGMII FDX 1000Base then up */
-		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e);
-		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e);
-	}
-
-	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
-
-		/* configure port's PHY */
-		if (!((1 << prt) & swconfig->cpuport)) {
-			/* port 4 has phy 6, not 4 */
-			int phy = (prt == 4) ? 6 : prt;
-			if (mv88361xx_powerup(swconfig, phy))
-				return -1;
-			if (mv88361xx_reverse_mdipn(swconfig, phy))
-				return -1;
-			if (mv88361xx_led_init(swconfig, phy))
-				return -1;
-		}
-
-		/* set port VID to port+1 except for cpu port */
-		if (!((1 << prt) & swconfig->cpuport)) {
-			RD_SWITCH_PORT_REG(name, prt,
-				MV88E61XX_PRT_VID_REG, &reg);
-			WR_SWITCH_PORT_REG(name, prt,
-				MV88E61XX_PRT_VID_REG,
-				(reg & ~1023) | (prt+1));
-		}
-
-		/*Program port state */
-		RD_SWITCH_PORT_REG(name, prt,
-			MV88E61XX_PRT_CTRL_REG, &reg);
-		WR_SWITCH_PORT_REG(name, prt,
-			MV88E61XX_PRT_CTRL_REG,
-			reg | (swconfig->portstate & 0x03));
-
-	}
-
-	printf("%s Initialized on %s\n", idstr, name);
 	return 0;
 }
 
-#ifdef CONFIG_MV88E61XX_CMD
-static int
-do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int mv88e61xx_serdes_init(struct phy_device *phydev)
 {
-	char *name, *endp;
-	int write = 0;
-	enum { dev, prt, phy } target = dev;
-	u32 addrlo, addrhi, addr;
-	u32 reglo, reghi, reg;
-	u16 data, rdata;
+	int val;
 
-	if (argc < 7)
-		return -1;
+	val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
+	if (val < 0)
+		return val;
 
-	name = argv[1];
+	/* Power up serdes module */
+	val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
+	if (val < 0)
+		return val;
+	val &= ~(BMCR_PDOWN);
+	val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
+	if (val < 0)
+		return val;
 
-	if (strcmp(argv[2], "phy") == 0)
-		target = phy;
-	else if (strcmp(argv[2], "port") == 0)
-		target = prt;
-	else if (strcmp(argv[2], "dev") != 0)
-		return 1;
-
-	addrlo = simple_strtoul(argv[3], &endp, 16);
-
-	if (!*endp) {
-		addrhi = addrlo;
-	} else {
-		while (*endp < '0' || *endp > '9')
-			endp++;
-		addrhi = simple_strtoul(endp, NULL, 16);
-	}
-
-	reglo = simple_strtoul(argv[5], &endp, 16);
-	if (!*endp) {
-		reghi = reglo;
-	} else {
-		while (*endp < '0' || *endp > '9')
-			endp++;
-		reghi = simple_strtoul(endp, NULL, 16);
-	}
-
-	if (strcmp(argv[6], "write") == 0)
-		write = 1;
-	else if (strcmp(argv[6], "read") != 0)
-		return 1;
-
-	data = simple_strtoul(argv[7], NULL, 16);
-
-	for (addr = addrlo; addr <= addrhi; addr++) {
-		for (reg = reglo; reg <= reghi; reg++) {
-			if (write) {
-				if (target == phy)
-					mv88e61xx_switch_miiphy_write(
-						name, addr, reg, data);
-				else if (target == prt)
-					wr_switch_reg(name,
-						addr+MV88E61XX_PRT_OFST,
-						reg, data);
-				else
-					wr_switch_reg(name, addr, reg, data);
-			} else {
-				if (target == phy)
-					mv88e61xx_switch_miiphy_read(
-						name, addr, reg, &rdata);
-				else if (target == prt)
-					rd_switch_reg(name,
-						addr+MV88E61XX_PRT_OFST,
-						reg, &rdata);
-				else
-					rd_switch_reg(name, addr, reg, &rdata);
-				printf("%s %s %s %02x %s %02x %s %04x\n",
-					argv[0], argv[1], argv[2], addr,
-					argv[4], reg, argv[6], rdata);
-				if (write && argc == 7 && rdata != data)
-					return 1;
-			}
-		}
-	}
 	return 0;
 }
 
-U_BOOT_CMD(mv88e61xx, 8, 0, do_switch,
-	"Read or write mv88e61xx switch registers",
-	"<ethdevice> dev|port|phy <addr> reg <reg> write <data>\n"
-	"<ethdevice> dev|port|phy <addr> reg <reg> read [<data>]\n"
-	"    - read/write switch device, port or phy at (addr,reg)\n"
-	"      addr=0..0x1C for dev, 0..5 for port or phy.\n"
-	"      reg=0..0x1F.\n"
-	"      data=0..0xFFFF (tested if present against actual read).\n"
-	"      All numeric parameters are assumed to be hex.\n"
-	"      <addr> and <<reg> arguments can be ranges (x..y)"
-);
-#endif /* CONFIG_MV88E61XX_CMD */
+static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
+{
+	int val;
+
+	val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
+			       PORT_REG_CTRL_PSTATE_WIDTH,
+			       PORT_REG_CTRL_PSTATE_FORWARD);
+	val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
+	if (val < 0)
+		return val;
+
+	return 0;
+}
+
+static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
+							u8 mask)
+{
+	int val;
+
+	/* Set VID to port number plus one */
+	val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
+			       PORT_REG_VLAN_ID_DEF_VID_WIDTH,
+			       port + 1);
+	val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
+	if (val < 0)
+		return val;
+
+	/* Set VID mask */
+	val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
+			       PORT_REG_VLAN_MAP_TABLE_WIDTH,
+			       mask);
+	val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
+	if (val < 0)
+		return val;
+
+	return 0;
+}
+
+static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
+{
+	int res;
+	int val;
+	bool forced = false;
+
+	val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
+	if (val < 0)
+		return val;
+	if (!(val & PORT_REG_STATUS_LINK)) {
+		/* Temporarily force link to read port configuration */
+		u32 timeout = 100;
+		forced = true;
+
+		val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
+		if (val < 0)
+			return val;
+		val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
+				PORT_REG_PHYS_CTRL_LINK_VALUE);
+		val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
+					   val);
+		if (val < 0)
+			return val;
+
+		/* Wait for status register to reflect forced link */
+		do {
+			val = mv88e61xx_port_read(phydev, port,
+						  PORT_REG_STATUS);
+			if (val < 0)
+				goto unforce;
+			if (val & PORT_REG_STATUS_LINK)
+				break;
+		} while (--timeout);
+
+		if (timeout == 0) {
+			res = -ETIMEDOUT;
+			goto unforce;
+		}
+	}
+
+	if (val & PORT_REG_STATUS_DUPLEX)
+		phydev->duplex = DUPLEX_FULL;
+	else
+		phydev->duplex = DUPLEX_HALF;
+
+	val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
+			       PORT_REG_STATUS_SPEED_WIDTH);
+	switch (val) {
+	case PORT_REG_STATUS_SPEED_1000:
+		phydev->speed = SPEED_1000;
+		break;
+	case PORT_REG_STATUS_SPEED_100:
+		phydev->speed = SPEED_100;
+		break;
+	default:
+		phydev->speed = SPEED_10;
+		break;
+	}
+
+	res = 0;
+
+unforce:
+	if (forced) {
+		val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
+		if (val < 0)
+			return val;
+		val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
+				PORT_REG_PHYS_CTRL_LINK_VALUE);
+		val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
+					   val);
+		if (val < 0)
+			return val;
+	}
+
+	return res;
+}
+
+static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
+{
+	int val;
+
+	/* Set CPUDest */
+	val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_MON_CTRL);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
+			       GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
+			       CONFIG_MV88E61XX_CPU_PORT);
+	val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
+				     GLOBAL1_MON_CTRL, val);
+	if (val < 0)
+		return val;
+
+	/* Allow CPU to route to any port */
+	val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
+	val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
+	if (val < 0)
+		return val;
+
+	/* Enable CPU port */
+	val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
+	if (val < 0)
+		return val;
+
+	val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
+	if (val < 0)
+		return val;
+
+	/* If CPU is connected to serdes, initialize serdes */
+	if (mv88e61xx_6352_family(phydev)) {
+		val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
+		if (val < 0)
+			return val;
+		if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
+		    val == PORT_REG_STATUS_CMODE_1000BASE_X ||
+		    val == PORT_REG_STATUS_CMODE_SGMII) {
+			val = mv88e61xx_serdes_init(phydev);
+			if (val < 0)
+				return val;
+		}
+	}
+
+	return 0;
+}
+
+static int mv88e61xx_switch_init(struct phy_device *phydev)
+{
+	static int init;
+	int res;
+
+	if (init)
+		return 0;
+
+	res = mv88e61xx_switch_reset(phydev);
+	if (res < 0)
+		return res;
+
+	res = mv88e61xx_set_cpu_port(phydev);
+	if (res < 0)
+		return res;
+
+	init = 1;
+
+	return 0;
+}
+
+static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
+{
+	int val;
+
+	val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
+	if (val < 0)
+		return val;
+	val &= ~(BMCR_PDOWN);
+	val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
+	if (val < 0)
+		return val;
+
+	return 0;
+}
+
+static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
+{
+	int val;
+
+	/*
+	 * Enable energy-detect sensing on PHY, used to determine when a PHY
+	 * port is physically connected
+	 */
+	val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, PHY_REG_CTRL1_ENERGY_DET_SHIFT,
+			       PHY_REG_CTRL1_ENERGY_DET_WIDTH,
+			       PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT);
+	val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
+	if (val < 0)
+		return val;
+
+	return 0;
+}
+
+static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
+{
+	int val;
+
+	val = mv88e61xx_port_enable(phydev, phy);
+	if (val < 0)
+		return val;
+
+	val = mv88e61xx_port_set_vlan(phydev, phy,
+			1 << CONFIG_MV88E61XX_CPU_PORT);
+	if (val < 0)
+		return val;
+
+	return 0;
+}
+
+static int mv88e61xx_probe(struct phy_device *phydev)
+{
+	struct mii_dev *smi_wrapper;
+	struct mv88e61xx_phy_priv *priv;
+	int res;
+
+	res = mv88e61xx_hw_reset(phydev);
+	if (res < 0)
+		return res;
+
+	priv = malloc(sizeof(*priv));
+	if (!priv)
+		return -ENOMEM;
+
+	memset(priv, 0, sizeof(*priv));
+
+	/*
+	 * This device requires indirect reads/writes to the PHY registers
+	 * which the generic PHY code can't handle.  Make a wrapper MII device
+	 * to handle reads/writes
+	 */
+	smi_wrapper = mdio_alloc();
+	if (!smi_wrapper) {
+		free(priv);
+		return -ENOMEM;
+	}
+
+	/*
+	 * Store the mdio bus in the private data, as we are going to replace
+	 * the bus with the wrapper bus
+	 */
+	priv->mdio_bus = phydev->bus;
+
+	/*
+	 * Store the smi bus address in private data.  This lets us use the
+	 * phydev addr field for device address instead, as the genphy code
+	 * expects.
+	 */
+	priv->smi_addr = phydev->addr;
+
+	/*
+	 * Store the phy_device in the wrapper mii device. This lets us get it
+	 * back when genphy functions call phy_read/phy_write.
+	 */
+	smi_wrapper->priv = phydev;
+	strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
+	smi_wrapper->read = mv88e61xx_phy_read_indirect;
+	smi_wrapper->write = mv88e61xx_phy_write_indirect;
+
+	/* Replace the bus with the wrapper device */
+	phydev->bus = smi_wrapper;
+
+	phydev->priv = priv;
+
+	priv->id = mv88e61xx_get_switch_id(phydev);
+
+	return 0;
+}
+
+static int mv88e61xx_phy_config(struct phy_device *phydev)
+{
+	int res;
+	int i;
+	int ret = -1;
+
+	res = mv88e61xx_switch_init(phydev);
+	if (res < 0)
+		return res;
+
+	for (i = 0; i < PORT_COUNT; i++) {
+		if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
+			phydev->addr = i;
+
+			res = mv88e61xx_phy_enable(phydev, i);
+			if (res < 0) {
+				printf("Error enabling PHY %i\n", i);
+				continue;
+			}
+			res = mv88e61xx_phy_setup(phydev, i);
+			if (res < 0) {
+				printf("Error setting up PHY %i\n", i);
+				continue;
+			}
+			res = mv88e61xx_phy_config_port(phydev, i);
+			if (res < 0) {
+				printf("Error configuring PHY %i\n", i);
+				continue;
+			}
+
+			res = genphy_config_aneg(phydev);
+			if (res < 0) {
+				printf("Error setting PHY %i autoneg\n", i);
+				continue;
+			}
+			res = phy_reset(phydev);
+			if (res < 0) {
+				printf("Error resetting PHY %i\n", i);
+				continue;
+			}
+
+			/* Return success if any PHY succeeds */
+			ret = 0;
+		}
+	}
+
+	return ret;
+}
+
+static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
+{
+	int val;
+
+	val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
+	if (val < 0)
+		return 0;
+
+	/*
+	 * After reset, the energy detect signal remains high for a few seconds
+	 * regardless of whether a cable is connected.  This function will
+	 * return false positives during this time.
+	 */
+	return (val & PHY_REG_STATUS1_ENERGY) == 0;
+}
+
+static int mv88e61xx_phy_startup(struct phy_device *phydev)
+{
+	int i;
+	int link = 0;
+	int res;
+	int speed = phydev->speed;
+	int duplex = phydev->duplex;
+
+	for (i = 0; i < PORT_COUNT; i++) {
+		if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
+			phydev->addr = i;
+			if (!mv88e61xx_phy_is_connected(phydev))
+				continue;
+			res = genphy_update_link(phydev);
+			if (res < 0)
+				continue;
+			res = mv88e61xx_parse_status(phydev);
+			if (res < 0)
+				continue;
+			link = (link || phydev->link);
+		}
+	}
+	phydev->link = link;
+
+	/* Restore CPU interface speed and duplex after it was changed for
+	 * other ports */
+	phydev->speed = speed;
+	phydev->duplex = duplex;
+
+	return 0;
+}
+
+static struct phy_driver mv88e61xx_driver = {
+	.name = "Marvell MV88E61xx",
+	.uid = 0x01410eb1,
+	.mask = 0xfffffff0,
+	.features = PHY_GBIT_FEATURES,
+	.probe = mv88e61xx_probe,
+	.config = mv88e61xx_phy_config,
+	.startup = mv88e61xx_phy_startup,
+	.shutdown = &genphy_shutdown,
+};
+
+int phy_mv88e61xx_init(void)
+{
+	phy_register(&mv88e61xx_driver);
+
+	return 0;
+}
+
+/*
+ * Overload weak get_phy_id definition since we need non-standard functions
+ * to read PHY registers
+ */
+int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
+{
+	struct phy_device temp_phy;
+	struct mv88e61xx_phy_priv temp_priv;
+	struct mii_dev temp_mii;
+	int val;
+
+	/*
+	 * Buid temporary data structures that the chip reading code needs to
+	 * read the ID
+	 */
+	temp_priv.mdio_bus = bus;
+	temp_priv.smi_addr = smi_addr;
+	temp_phy.priv = &temp_priv;
+	temp_mii.priv = &temp_phy;
+
+	val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
+	if (val < 0)
+		return -EIO;
+
+	*phy_id = val << 16;
+
+	val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
+	if (val < 0)
+		return -EIO;
+
+	*phy_id |= (val & 0xffff);
+
+	return 0;
+}
diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h
deleted file mode 100644
index 9c62e4a..0000000
--- a/drivers/net/phy/mv88e61xx.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _MV88E61XX_H
-#define _MV88E61XX_H
-
-#include <miiphy.h>
-
-#define MV88E61XX_CPU_PORT		0x5
-
-#define MV88E61XX_PHY_TIMEOUT		100000
-
-/* port dev-addr (= port + 0x10) */
-#define MV88E61XX_PRT_OFST		0x10
-/* port registers */
-#define MV88E61XX_PCS_CTRL_REG		0x1
-#define MV88E61XX_PRT_CTRL_REG		0x4
-#define MV88E61XX_PRT_VMAP_REG		0x6
-#define MV88E61XX_PRT_VID_REG		0x7
-#define MV88E61XX_RGMII_TIMECTRL_REG	0x1A
-
-/* global registers dev-addr */
-#define MV88E61XX_GLBREG_DEVADR	0x1B
-/* global registers */
-#define MV88E61XX_SGSR			0x00
-#define MV88E61XX_SGCR			0x04
-
-/* global 2 registers dev-addr */
-#define MV88E61XX_GLB2REG_DEVADR	0x1C
-/* global 2 registers */
-#define MV88E61XX_PHY_CMD		0x18
-#define MV88E61XX_PHY_DATA		0x19
-/* global 2 phy commands */
-#define MV88E61XX_PHY_WRITE_CMD		0x9400
-#define MV88E61XX_PHY_READ_CMD		0x9800
-
-#define MV88E61XX_BUSY_OFST		15
-#define MV88E61XX_MODE_OFST		12
-#define MV88E61XX_OP_OFST		10
-#define MV88E61XX_ADDR_OFST		5
-
-#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-static int mv88e61xx_busychk_multic(char *name, u32 devaddr);
-static void mv88e61xx_switch_write(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 data);
-static void mv88e61xx_switch_read(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 *data);
-#define wr_switch_reg mv88e61xx_switch_write
-#define rd_switch_reg mv88e61xx_switch_read
-#else
-/* switch appears a s simple PHY and can thus use miiphy */
-#define wr_switch_reg miiphy_write
-#define rd_switch_reg miiphy_read
-#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
-
-#endif /* _MV88E61XX_H */
diff --git a/drivers/net/phy/natsemi.c b/drivers/net/phy/natsemi.c
index d2e4c3c..1592e9b 100644
--- a/drivers/net/phy/natsemi.c
+++ b/drivers/net/phy/natsemi.c
@@ -93,10 +93,13 @@
 
 static int dp83865_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	dp83865_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return dp83865_parse_status(phydev);
 }
 
 
@@ -134,10 +137,13 @@
 
 static int dp83848_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	dp83848_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return dp83848_parse_status(phydev);
 }
 
 static struct phy_driver DP83848_driver = {
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 23c82bb..80bdfb6 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -248,7 +248,7 @@
 			if (i > PHY_ANEG_TIMEOUT) {
 				printf(" TIMEOUT !\n");
 				phydev->link = 0;
-				return 0;
+				return -ETIMEDOUT;
 			}
 
 			if (ctrlc()) {
@@ -431,10 +431,13 @@
 
 int genphy_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	genphy_parse_link(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return genphy_parse_link(phydev);
 }
 
 int genphy_shutdown(struct phy_device *phydev)
@@ -458,6 +461,9 @@
 
 int phy_init(void)
 {
+#ifdef CONFIG_MV88E61XX_SWITCH
+	phy_mv88e61xx_init();
+#endif
 #ifdef CONFIG_PHY_AQUANTIA
 	phy_aquantia_init();
 #endif
@@ -876,9 +882,7 @@
 int phy_config(struct phy_device *phydev)
 {
 	/* Invoke an optional board-specific helper */
-	board_phy_config(phydev);
-
-	return 0;
+	return board_phy_config(phydev);
 }
 
 int phy_shutdown(struct phy_device *phydev)
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 9d7f55b..7a99cb0 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -208,28 +208,38 @@
 
 static int rtl8211x_startup(struct phy_device *phydev)
 {
-	/* Read the Status (2x to make sure link is right) */
-	genphy_update_link(phydev);
-	rtl8211x_parse_status(phydev);
+	int ret;
 
-	return 0;
+	/* Read the Status (2x to make sure link is right) */
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return rtl8211x_parse_status(phydev);
 }
 
 static int rtl8211e_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	genphy_parse_link(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return genphy_parse_link(phydev);
 }
 
 static int rtl8211f_startup(struct phy_device *phydev)
 {
-	/* Read the Status (2x to make sure link is right) */
-	genphy_update_link(phydev);
-	rtl8211f_parse_status(phydev);
+	int ret;
 
-	return 0;
+	/* Read the Status (2x to make sure link is right) */
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+	/* Read the Status (2x to make sure link is right) */
+
+	return rtl8211f_parse_status(phydev);
 }
 
 /* Support for RTL8211B PHY */
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index 34986a2..313fcdf 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -34,9 +34,13 @@
 
 static int smsc_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	smsc_parse_status(phydev);
-	return 0;
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return smsc_parse_status(phydev);
 }
 
 static struct phy_driver lan8700_driver = {
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index 937426b..c55dd97 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -6,6 +6,14 @@
  */
 #include <common.h>
 #include <phy.h>
+#include <linux/compat.h>
+#include <malloc.h>
+
+#include <fdtdec.h>
+#include <dm.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /* TI DP83867 */
 #define DP83867_DEVADDR		0x1f
@@ -71,6 +79,17 @@
 #define MII_MMD_CTRL_INCR_RDWT	0x8000 /* post increment on reads & writes */
 #define MII_MMD_CTRL_INCR_ON_WT	0xC000 /* post increment on writes only */
 
+/* User setting - can be taken from DTS */
+#define DEFAULT_RX_ID_DELAY	DP83867_RGMIIDCTL_2_25_NS
+#define DEFAULT_TX_ID_DELAY	DP83867_RGMIIDCTL_2_75_NS
+#define DEFAULT_FIFO_DEPTH	DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
+
+struct dp83867_private {
+	int rx_id_delay;
+	int tx_id_delay;
+	int fifo_depth;
+};
+
 /**
  * phy_read_mmd_indirect - reads data from the MMD registers
  * @phydev: The PHY device bus
@@ -137,27 +156,60 @@
 	phy_write(phydev, addr, MII_MMD_DATA, data);
 }
 
+#if defined(CONFIG_DM_ETH)
 /**
- * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
- * is RGMII (all variants)
+ * dp83867_data_init - Convenience function for setting PHY specific data
+ *
  * @phydev: the phy_device struct
  */
-static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
+static int dp83867_of_init(struct phy_device *phydev)
 {
-	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
-		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
-}
+	struct dp83867_private *dp83867 = phydev->priv;
+	struct udevice *dev = phydev->dev;
 
-/* User setting - can be taken from DTS */
-#define RX_ID_DELAY	8
-#define TX_ID_DELAY	0xa
-#define FIFO_DEPTH	1
+	dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+				 "ti,rx-internal-delay", -1);
+
+	dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+				 "ti,tx-internal-delay", -1);
+
+	dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+				 "ti,fifo-depth", -1);
+
+	return 0;
+}
+#else
+static int dp83867_of_init(struct phy_device *phydev)
+{
+	struct dp83867_private *dp83867 = phydev->priv;
+
+	dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
+	dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
+	dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
+
+	return 0;
+}
+#endif
 
 static int dp83867_config(struct phy_device *phydev)
 {
+	struct dp83867_private *dp83867;
 	unsigned int val, delay, cfg2;
 	int ret;
 
+	if (!phydev->priv) {
+		dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
+		if (!dp83867)
+			return -ENOMEM;
+
+		phydev->priv = dp83867;
+		ret = dp83867_of_init(phydev);
+		if (ret)
+			goto err_out;
+	} else {
+		dp83867 = (struct dp83867_private *)phydev->priv;
+	}
+
 	/* Restart the PHY.  */
 	val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
 	phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
@@ -166,10 +218,10 @@
 	if (phy_interface_is_rgmii(phydev)) {
 		ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 			(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
-			(FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
+			(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
 		if (ret)
-			return ret;
-	} else {
+			goto err_out;
+	} else if (phy_interface_is_sgmii(phydev)) {
 		phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 			  (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
 
@@ -189,8 +241,8 @@
 			  DP83867_PHYCTRL_SGMIIEN |
 			  (DP83867_MDI_CROSSOVER_MDIX <<
 			  DP83867_MDI_CROSSOVER) |
-			  (FIFO_DEPTH << DP83867_PHYCTRL_RXFIFO_SHIFT) |
-			  (FIFO_DEPTH  << DP83867_PHYCTRL_TXFIFO_SHIFT));
+			  (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
+			  (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
 		phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
 	}
 
@@ -212,8 +264,8 @@
 		phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 				       DP83867_DEVADDR, phydev->addr, val);
 
-		delay = (RX_ID_DELAY |
-			 (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
+		delay = (dp83867->rx_id_delay |
+			 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 
 		phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
 				       DP83867_DEVADDR, phydev->addr, delay);
@@ -221,6 +273,10 @@
 
 	genphy_config_aneg(phydev);
 	return 0;
+
+err_out:
+	kfree(dp83867);
+	return ret;
 }
 
 static struct phy_driver DP83867_driver = {
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 941d076..2635b82 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -112,10 +112,12 @@
 
 static int vitesse_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	vitesse_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+	return vitesse_parse_status(phydev);
 }
 
 static int cis8204_config(struct phy_device *phydev)
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 5862bf0..7b85aa0 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -250,7 +250,7 @@
 
 static int setup_phy(struct udevice *dev)
 {
-	int i;
+	int i, ret;
 	u16 phyreg;
 	struct xemaclite *emaclite = dev_get_priv(dev);
 	struct phy_device *phydev;
@@ -302,7 +302,9 @@
 	phydev->advertising = supported;
 	emaclite->phydev = phydev;
 	phy_config(phydev);
-	phy_startup(phydev);
+	ret = phy_startup(phydev);
+	if (ret)
+		return ret;
 
 	if (!phydev->link) {
 		printf("%s: No link.\n", phydev->dev->name);
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index aec8077..519699d 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -179,6 +179,7 @@
 	struct zynq_gem_regs *iobase;
 	phy_interface_t interface;
 	struct phy_device *phydev;
+	int phy_of_handle;
 	struct mii_dev *bus;
 };
 
@@ -352,14 +353,17 @@
 	priv->phydev->supported = supported | ADVERTISED_Pause |
 				  ADVERTISED_Asym_Pause;
 	priv->phydev->advertising = priv->phydev->supported;
-	phy_config(priv->phydev);
 
-	return 0;
+	if (priv->phy_of_handle > 0)
+		priv->phydev->dev->of_offset = priv->phy_of_handle;
+
+	return phy_config(priv->phydev);
 }
 
 static int zynq_gem_init(struct udevice *dev)
 {
 	u32 i, nwconfig;
+	int ret;
 	unsigned long clk_rate = 0;
 	struct zynq_gem_priv *priv = dev_get_priv(dev);
 	struct zynq_gem_regs *regs = priv->iobase;
@@ -427,7 +431,9 @@
 		priv->init++;
 	}
 
-	phy_startup(priv->phydev);
+	ret = phy_startup(priv->phydev);
+	if (ret)
+		return ret;
 
 	if (!priv->phydev->link) {
 		printf("%s: No link.\n", priv->phydev->dev->name);
@@ -675,7 +681,6 @@
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct zynq_gem_priv *priv = dev_get_priv(dev);
-	int offset = 0;
 	const char *phy_mode;
 
 	pdata->iobase = (phys_addr_t)dev_get_addr(dev);
@@ -684,10 +689,11 @@
 	priv->emio = 0;
 	priv->phyaddr = -1;
 
-	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
-				       "phy-handle");
-	if (offset > 0)
-		priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
+	priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob,
+					dev->of_offset, "phy-handle");
+	if (priv->phy_of_handle > 0)
+		priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
+					priv->phy_of_handle, "reg", -1);
 
 	phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
 	if (phy_mode)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 4619089..4b73a0f 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -175,11 +175,7 @@
 	int bus;
 
 	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
-#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
-		for (bus = hose->last_busno; bus >= hose->first_busno; bus--) {
-#else
 		for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
-#endif
 			bdf = pci_hose_find_devices(hose, bus, ids, &index);
 			if (bdf != -1)
 				return bdf;
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 2a69bab..567b766 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -105,6 +105,24 @@
 
 if PINCTRL || SPL_PINCTRL
 
+config AR933X_PINCTRL
+	bool "QCA/Athores ar933x pin control driver"
+	depends on DM && SOC_AR933X
+	help
+	  Support pin multiplexing control on QCA/Athores ar933x SoCs.
+	  The driver is controlled by a device tree node which contains
+	  both the GPIO definitions and pin control functions for each
+	  available multiplex function.
+
+config QCA953X_PINCTRL
+	bool "QCA/Athores qca953x pin control driver"
+	depends on DM && SOC_QCA953X
+	help
+	  Support pin multiplexing control on QCA/Athores qca953x SoCs.
+	  The driver is controlled by a device tree node which contains
+	  both the GPIO definitions and pin control functions for each
+	  available multiplex function.
+
 config ROCKCHIP_PINCTRL
 	bool "Rockchip pin control driver"
 	depends on DM
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 37dc904..b99ed2f 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -6,6 +6,7 @@
 obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC)	+= pinctrl-generic.o
 
 obj-y					+= nxp/
+obj-$(CONFIG_ARCH_ATH79) += ath79/
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_PINCTRL_SANDBOX)	+= pinctrl-sandbox.o
 
diff --git a/drivers/pinctrl/ath79/Makefile b/drivers/pinctrl/ath79/Makefile
new file mode 100644
index 0000000..dcea10a
--- /dev/null
+++ b/drivers/pinctrl/ath79/Makefile
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_AR933X_PINCTRL) += pinctrl_ar933x.o
+obj-$(CONFIG_QCA953x_PINCTRL) += pinctrl_qca953x.o
diff --git a/drivers/pinctrl/ath79/pinctrl_ar933x.c b/drivers/pinctrl/ath79/pinctrl_ar933x.c
new file mode 100644
index 0000000..e3f64b6
--- /dev/null
+++ b/drivers/pinctrl/ath79/pinctrl_ar933x.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include <mach/ar71xx_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum periph_id {
+	PERIPH_ID_UART0,
+	PERIPH_ID_SPI0,
+	PERIPH_ID_NONE = -1,
+};
+
+struct ar933x_pinctrl_priv {
+	void __iomem *regs;
+};
+
+static void pinctrl_ar933x_spi_config(struct ar933x_pinctrl_priv *priv, int cs)
+{
+	switch (cs) {
+	case 0:
+		clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
+				AR933X_GPIO(4), AR933X_GPIO(3) |
+				AR933X_GPIO(5) | AR933X_GPIO(2));
+		setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
+			     AR933X_GPIO_FUNC_SPI_EN |
+			     AR933X_GPIO_FUNC_RES_TRUE);
+		break;
+	}
+}
+
+static void pinctrl_ar933x_uart_config(struct ar933x_pinctrl_priv *priv, int uart_id)
+{
+	switch (uart_id) {
+	case PERIPH_ID_UART0:
+		clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
+				AR933X_GPIO(9), AR933X_GPIO(10));
+		setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
+			     AR933X_GPIO_FUNC_UART_EN |
+			     AR933X_GPIO_FUNC_RES_TRUE);
+		break;
+	}
+}
+
+static int ar933x_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+	struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
+
+	debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+	switch (func) {
+	case PERIPH_ID_SPI0:
+		pinctrl_ar933x_spi_config(priv, flags);
+		break;
+	case PERIPH_ID_UART0:
+		pinctrl_ar933x_uart_config(priv, func);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int ar933x_pinctrl_get_periph_id(struct udevice *dev,
+					struct udevice *periph)
+{
+	u32 cell[2];
+	int ret;
+
+	ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+				   "interrupts", cell, ARRAY_SIZE(cell));
+	if (ret < 0)
+		return -EINVAL;
+
+	switch (cell[0]) {
+	case 128:
+		return PERIPH_ID_UART0;
+	case 129:
+		return PERIPH_ID_SPI0;
+	}
+	return -ENOENT;
+}
+
+static int ar933x_pinctrl_set_state_simple(struct udevice *dev,
+					   struct udevice *periph)
+{
+	int func;
+
+	func = ar933x_pinctrl_get_periph_id(dev, periph);
+	if (func < 0)
+		return func;
+	return ar933x_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops ar933x_pinctrl_ops = {
+	.set_state_simple	= ar933x_pinctrl_set_state_simple,
+	.request	= ar933x_pinctrl_request,
+	.get_periph_id	= ar933x_pinctrl_get_periph_id,
+};
+
+static int ar933x_pinctrl_probe(struct udevice *dev)
+{
+	struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = map_physmem(addr,
+				 AR71XX_GPIO_SIZE,
+				 MAP_NOCACHE);
+	return 0;
+}
+
+static const struct udevice_id ar933x_pinctrl_ids[] = {
+	{ .compatible = "qca,ar933x-pinctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_ar933x) = {
+	.name		= "pinctrl_ar933x",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= ar933x_pinctrl_ids,
+	.priv_auto_alloc_size = sizeof(struct ar933x_pinctrl_priv),
+	.ops		= &ar933x_pinctrl_ops,
+	.probe		= ar933x_pinctrl_probe,
+};
diff --git a/drivers/pinctrl/ath79/pinctrl_qca953x.c b/drivers/pinctrl/ath79/pinctrl_qca953x.c
new file mode 100644
index 0000000..d02597e
--- /dev/null
+++ b/drivers/pinctrl/ath79/pinctrl_qca953x.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include <mach/ar71xx_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum periph_id {
+	PERIPH_ID_UART0,
+	PERIPH_ID_SPI0,
+	PERIPH_ID_NONE = -1,
+};
+
+struct qca953x_pinctrl_priv {
+	void __iomem *regs;
+};
+
+static void pinctrl_qca953x_spi_config(struct qca953x_pinctrl_priv *priv, int cs)
+{
+	switch (cs) {
+	case 0:
+		clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
+				QCA953X_GPIO(5) | QCA953X_GPIO(6) |
+				QCA953X_GPIO(7), QCA953X_GPIO(8));
+
+		clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_OUT_FUNC1,
+				QCA953X_GPIO_MUX_MASK(8) |
+				QCA953X_GPIO_MUX_MASK(16) |
+				QCA953X_GPIO_MUX_MASK(24),
+				(QCA953X_GPIO_OUT_MUX_SPI_CS0 << 8) |
+				(QCA953X_GPIO_OUT_MUX_SPI_CLK << 16) |
+				(QCA953X_GPIO_OUT_MUX_SPI_MOSI << 24));
+
+		clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_IN_ENABLE0,
+				QCA953X_GPIO_MUX_MASK(0),
+				QCA953X_GPIO_IN_MUX_SPI_DATA_IN);
+
+		setbits_be32(priv->regs + AR71XX_GPIO_REG_OUT,
+			     QCA953X_GPIO(8));
+		break;
+	}
+}
+
+static void pinctrl_qca953x_uart_config(struct qca953x_pinctrl_priv *priv, int uart_id)
+{
+	switch (uart_id) {
+	case PERIPH_ID_UART0:
+		clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
+				QCA953X_GPIO(9), QCA953X_GPIO(10));
+
+		clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_OUT_FUNC2,
+				QCA953X_GPIO_MUX_MASK(16),
+				QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16);
+
+		clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_IN_ENABLE0,
+				QCA953X_GPIO_MUX_MASK(8),
+				QCA953X_GPIO_IN_MUX_UART0_SIN << 8);
+
+		setbits_be32(priv->regs + AR71XX_GPIO_REG_OUT,
+			     QCA953X_GPIO(10));
+		break;
+	}
+}
+
+static int qca953x_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+	struct qca953x_pinctrl_priv *priv = dev_get_priv(dev);
+
+	debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+	switch (func) {
+	case PERIPH_ID_SPI0:
+		pinctrl_qca953x_spi_config(priv, flags);
+		break;
+	case PERIPH_ID_UART0:
+		pinctrl_qca953x_uart_config(priv, func);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int qca953x_pinctrl_get_periph_id(struct udevice *dev,
+					struct udevice *periph)
+{
+	u32 cell[2];
+	int ret;
+
+	ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+				   "interrupts", cell, ARRAY_SIZE(cell));
+	if (ret < 0)
+		return -EINVAL;
+
+	switch (cell[0]) {
+	case 128:
+		return PERIPH_ID_UART0;
+	case 129:
+		return PERIPH_ID_SPI0;
+	}
+	return -ENOENT;
+}
+
+static int qca953x_pinctrl_set_state_simple(struct udevice *dev,
+					   struct udevice *periph)
+{
+	int func;
+
+	func = qca953x_pinctrl_get_periph_id(dev, periph);
+	if (func < 0)
+		return func;
+	return qca953x_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops qca953x_pinctrl_ops = {
+	.set_state_simple	= qca953x_pinctrl_set_state_simple,
+	.request	= qca953x_pinctrl_request,
+	.get_periph_id	= qca953x_pinctrl_get_periph_id,
+};
+
+static int qca953x_pinctrl_probe(struct udevice *dev)
+{
+	struct qca953x_pinctrl_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = map_physmem(addr,
+				 AR71XX_GPIO_SIZE,
+				 MAP_NOCACHE);
+	return 0;
+}
+
+static const struct udevice_id qca953x_pinctrl_ids[] = {
+	{ .compatible = "qca,qca953x-pinctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_qca953x) = {
+	.name		= "pinctrl_qca953x",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= qca953x_pinctrl_ids,
+	.priv_auto_alloc_size = sizeof(struct qca953x_pinctrl_priv),
+	.ops		= &qca953x_pinctrl_ops,
+	.probe		= qca953x_pinctrl_probe,
+};
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index a9a5d47..2497ae9 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -89,6 +89,15 @@
 	  You will need to provide parameters to make this work. The driver will
 	  be available until the real driver model serial is running.
 
+config DEBUG_UART_AR933X
+	bool "QCA/Atheros ar933x"
+	depends on AR933X_UART
+	help
+	  Select this to enable a debug UART using the ar933x uart driver.
+	  You will need to provide parameters to make this work. The
+	  driver will be available until the real driver model serial is
+	  running.
+
 config DEBUG_UART_NS16550
 	bool "ns16550"
 	help
@@ -263,6 +272,15 @@
 	  Select this to enable an UART for Altera devices. Please find
 	  details on the "Embedded Peripherals IP User Guide" of Altera.
 
+config AR933X_UART
+	bool "QCA/Atheros ar933x UART support"
+	depends on DM_SERIAL && SOC_AR933X
+	help
+	  Select this to enable UART support for QCA/Atheros ar933x
+	  devices. This driver uses driver model and requires a device
+	  tree binding to operate, please refer to the document at
+	  doc/device-tree-bindings/serial/qca,ar9330-uart.txt.
+
 config FSL_LPUART
 	bool "Freescale LPUART support"
 	help
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index b0ac9d8..9def128 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -17,6 +17,7 @@
 
 obj-$(CONFIG_ALTERA_UART) += altera_uart.o
 obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
+obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
 obj-$(CONFIG_EFI_APP) += serial_efi.o
diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c
index 407354f..059cb0f 100644
--- a/drivers/serial/mcfuart.c
+++ b/drivers/serial/mcfuart.c
@@ -2,6 +2,9 @@
  * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
  * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
  *
+ * Modified to add device model (DM) support
+ * (C) Copyright 2015  Angelo Dureghello <angelo@sysam.it>
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
@@ -11,9 +14,10 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_coldfire.h>
 #include <serial.h>
 #include <linux/compiler.h>
-
 #include <asm/immap.h>
 #include <asm/uart.h>
 
@@ -21,91 +25,110 @@
 
 extern void uart_port_conf(int port);
 
-static int mcf_serial_init(void)
+static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate)
 {
-	volatile uart_t *uart;
 	u32 counter;
 
-	uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
-
-	uart_port_conf(CONFIG_SYS_UART_PORT);
+	uart_port_conf(port_idx);
 
 	/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
-	uart->ucr = UART_UCR_RESET_RX;
-	uart->ucr = UART_UCR_RESET_TX;
-	uart->ucr = UART_UCR_RESET_ERROR;
-	uart->ucr = UART_UCR_RESET_MR;
+	writeb(UART_UCR_RESET_RX, &uart->ucr);
+	writeb(UART_UCR_RESET_TX, &uart->ucr);
+	writeb(UART_UCR_RESET_ERROR, &uart->ucr);
+	writeb(UART_UCR_RESET_MR, &uart->ucr);
 	__asm__("nop");
 
-	uart->uimr = 0;
+	writeb(0, &uart->uimr);
 
 	/* write to CSR: RX/TX baud rate from timers */
-	uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK);
+	writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
 
-	uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE);
-	uart->umr = UART_UMR_SB_STOP_BITS_1;
+	writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
+	writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
 
 	/* Setting up BaudRate */
-	counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
-	counter = counter / gd->baudrate;
+	counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
+	counter = counter / baudrate;
 
 	/* write to CTUR: divide counter upper byte */
-	uart->ubg1 = (u8) ((counter & 0xff00) >> 8);
+	writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1);
 	/* write to CTLR: divide counter lower byte */
-	uart->ubg2 = (u8) (counter & 0x00ff);
+	writeb((u8)(counter & 0x00ff), &uart->ubg2);
 
-	uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED);
+	writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
 
 	return (0);
 }
 
+static void mcf_serial_setbrg_common(uart_t *uart, int baudrate)
+{
+	u32 counter;
+
+	/* Setting up BaudRate */
+	counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
+	counter = counter / baudrate;
+
+	/* write to CTUR: divide counter upper byte */
+	writeb(((counter & 0xff00) >> 8), &uart->ubg1);
+	/* write to CTLR: divide counter lower byte */
+	writeb((counter & 0x00ff), &uart->ubg2);
+
+	writeb(UART_UCR_RESET_RX, &uart->ucr);
+	writeb(UART_UCR_RESET_TX, &uart->ucr);
+
+	writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
+}
+
+#ifndef CONFIG_DM_SERIAL
+
+static int mcf_serial_init(void)
+{
+	uart_t *uart_base;
+	int port_idx;
+
+	uart_base = (uart_t *)CONFIG_SYS_UART_BASE;
+	port_idx = CONFIG_SYS_UART_PORT;
+
+	return mcf_serial_init_common(uart_base, port_idx, gd->baudrate);
+}
+
 static void mcf_serial_putc(const char c)
 {
-	volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
+	uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
 
 	if (c == '\n')
 		serial_putc('\r');
 
 	/* Wait for last character to go. */
-	while (!(uart->usr & UART_USR_TXRDY)) ;
+	while (!(readb(&uart->usr) & UART_USR_TXRDY))
+		;
 
-	uart->utb = c;
+	writeb(c, &uart->utb);
 }
 
 static int mcf_serial_getc(void)
 {
-	volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
+	uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
 
 	/* Wait for a character to arrive. */
-	while (!(uart->usr & UART_USR_RXRDY)) ;
-	return uart->urb;
-}
+	while (!(readb(&uart->usr) & UART_USR_RXRDY))
+		;
 
-static int mcf_serial_tstc(void)
-{
-	volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
-
-	return (uart->usr & UART_USR_RXRDY);
+	return readb(&uart->urb);
 }
 
 static void mcf_serial_setbrg(void)
 {
-	volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
-	u32 counter;
+	uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
 
-	/* Setting up BaudRate */
-	counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
-	counter = counter / gd->baudrate;
+	mcf_serial_setbrg_common(uart, gd->baudrate);
+}
 
-	/* write to CTUR: divide counter upper byte */
-	uart->ubg1 = ((counter & 0xff00) >> 8);
-	/* write to CTLR: divide counter lower byte */
-	uart->ubg2 = (counter & 0x00ff);
+static int mcf_serial_tstc(void)
+{
+	uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
 
-	uart->ucr = UART_UCR_RESET_RX;
-	uart->ucr = UART_UCR_RESET_TX;
-
-	uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED;
+	return readb(&uart->usr) & UART_USR_RXRDY;
 }
 
 static struct serial_device mcf_serial_drv = {
@@ -128,3 +151,80 @@
 {
 	return &mcf_serial_drv;
 }
+
+#endif
+
+#ifdef CONFIG_DM_SERIAL
+
+static int coldfire_serial_probe(struct udevice *dev)
+{
+	struct coldfire_serial_platdata *plat = dev->platdata;
+
+	return mcf_serial_init_common((uart_t *)plat->base,
+						plat->port, plat->baudrate);
+}
+
+static int coldfire_serial_putc(struct udevice *dev, const char ch)
+{
+	struct coldfire_serial_platdata *plat = dev->platdata;
+	uart_t *uart = (uart_t *)plat->base;
+
+	/* Wait for last character to go. */
+	if (!(readb(&uart->usr) & UART_USR_TXRDY))
+		return -EAGAIN;
+
+	writeb(ch, &uart->utb);
+
+	return 0;
+}
+
+static int coldfire_serial_getc(struct udevice *dev)
+{
+	struct coldfire_serial_platdata *plat = dev->platdata;
+	uart_t *uart = (uart_t *)(plat->base);
+
+	/* Wait for a character to arrive. */
+	if (!(readb(&uart->usr) & UART_USR_RXRDY))
+		return -EAGAIN;
+
+	return readb(&uart->urb);
+}
+
+int coldfire_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	struct coldfire_serial_platdata *plat = dev->platdata;
+	uart_t *uart = (uart_t *)(plat->base);
+
+	mcf_serial_setbrg_common(uart, baudrate);
+
+	return 0;
+}
+
+static int coldfire_serial_pending(struct udevice *dev, bool input)
+{
+	struct coldfire_serial_platdata *plat = dev->platdata;
+	uart_t *uart = (uart_t *)(plat->base);
+
+	if (input)
+		return readb(&uart->usr) & UART_USR_RXRDY ? 1 : 0;
+	else
+		return readb(&uart->usr) & UART_USR_TXRDY ? 0 : 1;
+
+	return 0;
+}
+
+static const struct dm_serial_ops coldfire_serial_ops = {
+	.putc = coldfire_serial_putc,
+	.pending = coldfire_serial_pending,
+	.getc = coldfire_serial_getc,
+	.setbrg = coldfire_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_coldfire) = {
+	.name = "serial_coldfire",
+	.id = UCLASS_SERIAL,
+	.probe = coldfire_serial_probe,
+	.ops = &coldfire_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+#endif
diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c
new file mode 100644
index 0000000..aae66dc
--- /dev/null
+++ b/drivers/serial/serial_ar933x.c
@@ -0,0 +1,243 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <dm/pinctrl.h>
+#include <mach/ar71xx_regs.h>
+
+#define AR933X_UART_DATA_REG            0x00
+#define AR933X_UART_CS_REG              0x04
+#define AR933X_UART_CLK_REG             0x08
+
+#define AR933X_UART_DATA_TX_RX_MASK     0xff
+#define AR933X_UART_DATA_RX_CSR         BIT(8)
+#define AR933X_UART_DATA_TX_CSR         BIT(9)
+#define AR933X_UART_CS_IF_MODE_S        2
+#define AR933X_UART_CS_IF_MODE_M        0x3
+#define AR933X_UART_CS_IF_MODE_DTE      1
+#define AR933X_UART_CS_IF_MODE_DCE      2
+#define AR933X_UART_CS_TX_RDY_ORIDE     BIT(7)
+#define AR933X_UART_CS_RX_RDY_ORIDE     BIT(8)
+#define AR933X_UART_CLK_STEP_M          0xffff
+#define AR933X_UART_CLK_SCALE_M         0xfff
+#define AR933X_UART_CLK_SCALE_S         16
+#define AR933X_UART_CLK_STEP_S          0
+
+struct ar933x_serial_priv {
+	void __iomem *regs;
+};
+
+/*
+ * Baudrate algorithm come from Linux/drivers/tty/serial/ar933x_uart.c
+ * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
+ */
+static u32 ar933x_serial_get_baud(u32 clk, u32 scale, u32 step)
+{
+	u64 t;
+	u32 div;
+
+	div = (2 << 16) * (scale + 1);
+	t = clk;
+	t *= step;
+	t += (div / 2);
+	do_div(t, div);
+
+	return t;
+}
+
+static void ar933x_serial_get_scale_step(u32 clk, u32 baud,
+					 u32 *scale, u32 *step)
+{
+	u32 tscale, baudrate;
+	long min_diff;
+
+	*scale = 0;
+	*step = 0;
+
+	min_diff = baud;
+	for (tscale = 0; tscale < AR933X_UART_CLK_SCALE_M; tscale++) {
+		u64 tstep;
+		int diff;
+
+		tstep = baud * (tscale + 1);
+		tstep *= (2 << 16);
+		do_div(tstep, clk);
+
+		if (tstep > AR933X_UART_CLK_STEP_M)
+			break;
+
+		baudrate = ar933x_serial_get_baud(clk, tscale, tstep);
+		diff = abs(baudrate - baud);
+		if (diff < min_diff) {
+			min_diff = diff;
+			*scale = tscale;
+			*step = tstep;
+		}
+	}
+}
+
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	u32 val, scale, step;
+
+	val = get_serial_clock();
+	ar933x_serial_get_scale_step(val, baudrate, &scale, &step);
+
+	val  = (scale & AR933X_UART_CLK_SCALE_M)
+			<< AR933X_UART_CLK_SCALE_S;
+	val |= (step & AR933X_UART_CLK_STEP_M)
+			<< AR933X_UART_CLK_STEP_S;
+	writel(val, priv->regs + AR933X_UART_CLK_REG);
+
+	return 0;
+}
+
+static int ar933x_serial_putc(struct udevice *dev, const char c)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	u32 data;
+
+	data = readl(priv->regs + AR933X_UART_DATA_REG);
+	if (!(data & AR933X_UART_DATA_TX_CSR))
+		return -EAGAIN;
+
+	data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+	writel(data, priv->regs + AR933X_UART_DATA_REG);
+
+	return 0;
+}
+
+static int ar933x_serial_getc(struct udevice *dev)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	u32 data;
+
+	data = readl(priv->regs + AR933X_UART_DATA_REG);
+	if (!(data & AR933X_UART_DATA_RX_CSR))
+		return -EAGAIN;
+
+	writel(AR933X_UART_DATA_RX_CSR, priv->regs + AR933X_UART_DATA_REG);
+	return data & AR933X_UART_DATA_TX_RX_MASK;
+}
+
+static int ar933x_serial_pending(struct udevice *dev, bool input)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	u32 data;
+
+	data = readl(priv->regs + AR933X_UART_DATA_REG);
+	if (input)
+		return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0;
+	else
+		return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1;
+}
+
+static int ar933x_serial_probe(struct udevice *dev)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+	u32 val;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = map_physmem(addr, AR933X_UART_SIZE,
+				 MAP_NOCACHE);
+
+	/*
+	 * UART controller configuration:
+	 * - no DMA
+	 * - no interrupt
+	 * - DCE mode
+	 * - no flow control
+	 * - set RX ready oride
+	 * - set TX ready oride
+	 */
+	val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
+	      AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
+	writel(val, priv->regs + AR933X_UART_CS_REG);
+	return 0;
+}
+
+static const struct dm_serial_ops ar933x_serial_ops = {
+	.putc = ar933x_serial_putc,
+	.pending = ar933x_serial_pending,
+	.getc = ar933x_serial_getc,
+	.setbrg = ar933x_serial_setbrg,
+};
+
+static const struct udevice_id ar933x_serial_ids[] = {
+	{ .compatible = "qca,ar9330-uart" },
+	{ }
+};
+
+U_BOOT_DRIVER(serial_ar933x) = {
+	.name   = "serial_ar933x",
+	.id = UCLASS_SERIAL,
+	.of_match = ar933x_serial_ids,
+	.priv_auto_alloc_size = sizeof(struct ar933x_serial_priv),
+	.probe = ar933x_serial_probe,
+	.ops    = &ar933x_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+#ifdef CONFIG_DEBUG_UART_AR933X
+
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+	void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
+	u32 val, scale, step;
+
+	/*
+	 * UART controller configuration:
+	 * - no DMA
+	 * - no interrupt
+	 * - DCE mode
+	 * - no flow control
+	 * - set RX ready oride
+	 * - set TX ready oride
+	 */
+	val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
+	      AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
+	writel(val, regs + AR933X_UART_CS_REG);
+
+	ar933x_serial_get_scale_step(CONFIG_DEBUG_UART_CLOCK,
+				     CONFIG_BAUDRATE, &scale, &step);
+
+	val  = (scale & AR933X_UART_CLK_SCALE_M)
+			<< AR933X_UART_CLK_SCALE_S;
+	val |= (step & AR933X_UART_CLK_STEP_M)
+			<< AR933X_UART_CLK_STEP_S;
+	writel(val, regs + AR933X_UART_CLK_REG);
+}
+
+static inline void _debug_uart_putc(int c)
+{
+	void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
+	u32 data;
+
+	do {
+		data = readl(regs + AR933X_UART_DATA_REG);
+	} while (!(data & AR933X_UART_DATA_TX_CSR));
+
+	data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+	writel(data, regs + AR933X_UART_DATA_REG);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index f0258f8..b7fd8e5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -23,6 +23,15 @@
 	  IP core. Please find details on the "Embedded Peripherals IP
 	  User Guide" of Altera.
 
+config ATH79_SPI
+	bool "Atheros SPI driver"
+	depends on ARCH_ATH79
+	help
+	  Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
+	  to access SPI NOR flash and other SPI peripherals. This driver
+	  uses driver model and requires a device tree binding to operate.
+	  please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
+
 config CADENCE_QSPI
 	bool "Cadence QSPI driver"
 	help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3eca745..7fb2926 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -17,6 +17,7 @@
 
 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
 obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
+obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
 obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
new file mode 100644
index 0000000..b18c733
--- /dev/null
+++ b/drivers/spi/ath79_spi.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <dm/pinctrl.h>
+#include <mach/ar71xx_regs.h>
+
+/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
+#define ATH79_SPI_CLK_DIV(x)           (((x) >> 1) - 1)
+#define ATH79_SPI_RRW_DELAY_FACTOR     12000
+#define ATH79_SPI_MHZ                  (1000 * 1000)
+
+struct ath79_spi_priv {
+	void __iomem *regs;
+	u32 rrw_delay;
+};
+
+static void spi_cs_activate(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+
+	writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
+	writel(AR71XX_SPI_IOC_CS_ALL, priv->regs + AR71XX_SPI_REG_IOC);
+}
+
+static void spi_cs_deactivate(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+
+	writel(AR71XX_SPI_IOC_CS_ALL, priv->regs + AR71XX_SPI_REG_IOC);
+	writel(0, priv->regs + AR71XX_SPI_REG_FS);
+}
+
+static int ath79_spi_claim_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+static int ath79_spi_release_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
+		const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+	u8 *rx = din;
+	const u8 *tx = dout;
+	u8 curbyte, curbitlen, restbits;
+	u32 bytes = bitlen / 8;
+	u32 out, in;
+	u64 tick;
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(dev);
+
+	restbits = (bitlen % 8);
+	if (restbits)
+		bytes++;
+
+	out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
+	while (bytes > 0) {
+		bytes--;
+		curbyte = 0;
+		if (tx)
+			curbyte = *tx++;
+
+		if (restbits && !bytes) {
+			curbitlen = restbits;
+			curbyte <<= 8 - restbits;
+		} else {
+			curbitlen = 8;
+		}
+
+		for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
+			if (curbyte & 0x80)
+				out |= AR71XX_SPI_IOC_DO;
+			else
+				out &= ~(AR71XX_SPI_IOC_DO);
+
+			writel(out, priv->regs + AR71XX_SPI_REG_IOC);
+
+			/* delay for low level */
+			if (priv->rrw_delay) {
+				tick = get_ticks() + priv->rrw_delay;
+				while (get_ticks() < tick)
+					/*NOP*/;
+			}
+
+			writel(out | AR71XX_SPI_IOC_CLK,
+			       priv->regs + AR71XX_SPI_REG_IOC);
+
+			/* delay for high level */
+			if (priv->rrw_delay) {
+				tick = get_ticks() + priv->rrw_delay;
+				while (get_ticks() < tick)
+					/*NOP*/;
+			}
+
+			curbyte <<= 1;
+		}
+
+		if (!bytes)
+			writel(out, priv->regs + AR71XX_SPI_REG_IOC);
+
+		in = readl(priv->regs + AR71XX_SPI_REG_RDS);
+		if (rx) {
+			if (restbits && !bytes)
+				*rx++ = (in << (8 - restbits));
+			else
+				*rx++ = in;
+		}
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(dev);
+
+	return 0;
+}
+
+
+static int ath79_spi_set_speed(struct udevice *bus, uint speed)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	u32 val, div = 0;
+	u64 time;
+
+	if (speed)
+		div = get_bus_freq(0) / speed;
+
+	if (div > 63)
+		div = 63;
+
+	if (div < 5)
+		div = 5;
+
+	/* calculate delay */
+	time = get_tbclk();
+	do_div(time, speed / 2);
+	val = get_bus_freq(0) / ATH79_SPI_MHZ;
+	val = ATH79_SPI_RRW_DELAY_FACTOR / val;
+	if (time > val)
+		priv->rrw_delay = time - val + 1;
+	else
+		priv->rrw_delay = 0;
+
+	writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
+	clrsetbits_be32(priv->regs + AR71XX_SPI_REG_CTRL,
+			AR71XX_SPI_CTRL_DIV_MASK,
+			ATH79_SPI_CLK_DIV(div));
+	writel(0, priv->regs + AR71XX_SPI_REG_FS);
+	return 0;
+}
+
+static int ath79_spi_set_mode(struct udevice *bus, uint mode)
+{
+	return 0;
+}
+
+static int ath79_spi_probe(struct udevice *bus)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(bus);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = map_physmem(addr,
+				 AR71XX_SPI_SIZE,
+				 MAP_NOCACHE);
+
+	/* Init SPI Hardware, disable remap, set clock */
+	writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
+	writel(AR71XX_SPI_CTRL_RD | ATH79_SPI_CLK_DIV(8),
+	       priv->regs + AR71XX_SPI_REG_CTRL);
+	writel(0, priv->regs + AR71XX_SPI_REG_FS);
+
+	return 0;
+}
+
+static int ath79_cs_info(struct udevice *bus, uint cs,
+			   struct spi_cs_info *info)
+{
+	/* Always allow activity on CS 0/1/2 */
+	if (cs >= 3)
+		return -ENODEV;
+
+	return 0;
+}
+
+static const struct dm_spi_ops ath79_spi_ops = {
+	.claim_bus  = ath79_spi_claim_bus,
+	.release_bus    = ath79_spi_release_bus,
+	.xfer       = ath79_spi_xfer,
+	.set_speed  = ath79_spi_set_speed,
+	.set_mode   = ath79_spi_set_mode,
+	.cs_info    = ath79_cs_info,
+};
+
+static const struct udevice_id ath79_spi_ids[] = {
+	{ .compatible = "qca,ar7100-spi" },
+	{}
+};
+
+U_BOOT_DRIVER(ath79_spi) = {
+	.name   = "ath79_spi",
+	.id = UCLASS_SPI,
+	.of_match = ath79_spi_ids,
+	.ops    = &ath79_spi_ops,
+	.priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
+	.probe  = ath79_spi_probe,
+};
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 2fe34c9..60e9d6e 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -35,6 +35,12 @@
 #define OMAP3_MCSPI4_BASE	0x480BA000
 #endif
 
+#define OMAP4_MCSPI_REG_OFFSET	0x100
+
+struct omap2_mcspi_platform_config {
+	unsigned int regs_offset;
+};
+
 /* per-register bitmasks */
 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
 #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
@@ -623,7 +629,10 @@
 	const void *blob = gd->fdt_blob;
 	int node = dev->of_offset;
 
-	priv->regs = (struct mcspi *)dev_get_addr(dev);
+	struct omap2_mcspi_platform_config* data =
+		(struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
+
+	priv->regs = (struct mcspi *)(dev_get_addr(dev) + data->regs_offset);
 	priv->pin_dir = fdtdec_get_uint(blob, node, "ti,pindir-d0-out-d1-in",
 					    MCSPI_PINDIR_D0_IN_D1_OUT);
 	priv->wordlen = SPI_DEFAULT_WORDLEN;
@@ -662,9 +671,17 @@
 	 */
 };
 
+static struct omap2_mcspi_platform_config omap2_pdata = {
+	.regs_offset = 0,
+};
+
+static struct omap2_mcspi_platform_config omap4_pdata = {
+	.regs_offset = OMAP4_MCSPI_REG_OFFSET,
+};
+
 static const struct udevice_id omap3_spi_ids[] = {
-	{ .compatible = "ti,omap2-mcspi" },
-	{ .compatible = "ti,omap4-mcspi" },
+	{ .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
+	{ .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
 	{ }
 };
 
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
index aa4abcc..d23dc81 100644
--- a/drivers/spi/soft_spi.c
+++ b/drivers/spi/soft_spi.c
@@ -26,15 +26,20 @@
 	struct gpio_desc mosi;
 	struct gpio_desc miso;
 	int spi_delay_us;
+	int flags;
 };
 
+#define SPI_MASTER_NO_RX        BIT(0)
+#define SPI_MASTER_NO_TX        BIT(1)
+
 struct soft_spi_priv {
 	unsigned int mode;
 };
 
 static int soft_spi_scl(struct udevice *dev, int bit)
 {
-	struct soft_spi_platdata *plat = dev->platdata;
+	struct udevice *bus = dev_get_parent(dev);
+	struct soft_spi_platdata *plat = dev_get_platdata(bus);
 
 	dm_gpio_set_value(&plat->sclk, bit);
 
@@ -43,7 +48,8 @@
 
 static int soft_spi_sda(struct udevice *dev, int bit)
 {
-	struct soft_spi_platdata *plat = dev->platdata;
+	struct udevice *bus = dev_get_parent(dev);
+	struct soft_spi_platdata *plat = dev_get_platdata(bus);
 
 	dm_gpio_set_value(&plat->mosi, bit);
 
@@ -52,7 +58,8 @@
 
 static int soft_spi_cs_activate(struct udevice *dev)
 {
-	struct soft_spi_platdata *plat = dev->platdata;
+	struct udevice *bus = dev_get_parent(dev);
+	struct soft_spi_platdata *plat = dev_get_platdata(bus);
 
 	dm_gpio_set_value(&plat->cs, 0);
 	dm_gpio_set_value(&plat->sclk, 0);
@@ -63,7 +70,8 @@
 
 static int soft_spi_cs_deactivate(struct udevice *dev)
 {
-	struct soft_spi_platdata *plat = dev->platdata;
+	struct udevice *bus = dev_get_parent(dev);
+	struct soft_spi_platdata *plat = dev_get_platdata(bus);
 
 	dm_gpio_set_value(&plat->cs, 0);
 
@@ -100,8 +108,9 @@
 static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen,
 			 const void *dout, void *din, unsigned long flags)
 {
-	struct soft_spi_priv *priv = dev_get_priv(dev);
-	struct soft_spi_platdata *plat = dev->platdata;
+	struct udevice *bus = dev_get_parent(dev);
+	struct soft_spi_priv *priv = dev_get_priv(bus);
+	struct soft_spi_platdata *plat = dev_get_platdata(bus);
 	uchar		tmpdin  = 0;
 	uchar		tmpdout = 0;
 	const u8	*txd = dout;
@@ -134,14 +143,16 @@
 
 		if (!cpha)
 			soft_spi_scl(dev, 0);
-		soft_spi_sda(dev, tmpdout & 0x80);
+		if ((plat->flags & SPI_MASTER_NO_TX) == 0)
+			soft_spi_sda(dev, !!(tmpdout & 0x80));
 		udelay(plat->spi_delay_us);
 		if (cpha)
 			soft_spi_scl(dev, 0);
 		else
 			soft_spi_scl(dev, 1);
 		tmpdin	<<= 1;
-		tmpdin	|= dm_gpio_get_value(&plat->miso);
+		if ((plat->flags & SPI_MASTER_NO_RX) == 0)
+			tmpdin	|= dm_gpio_get_value(&plat->miso);
 		tmpdout	<<= 1;
 		udelay(plat->spi_delay_us);
 		if (cpha)
@@ -203,24 +214,36 @@
 	struct spi_slave *slave = dev_get_parent_priv(dev);
 	struct soft_spi_platdata *plat = dev->platdata;
 	int cs_flags, clk_flags;
+	int ret;
 
 	cs_flags = (slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW;
 	clk_flags = (slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0;
-	if (gpio_request_by_name(dev, "cs-gpio", 0, &plat->cs,
+
+	if (gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs,
 				 GPIOD_IS_OUT | cs_flags) ||
-	    gpio_request_by_name(dev, "sclk-gpio", 0, &plat->sclk,
-				 GPIOD_IS_OUT | clk_flags) ||
-	    gpio_request_by_name(dev, "mosi-gpio", 0, &plat->mosi,
-				 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE) ||
-	    gpio_request_by_name(dev, "miso-gpio", 0, &plat->miso,
-				 GPIOD_IS_IN))
+	    gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk,
+				 GPIOD_IS_OUT | clk_flags))
+		return -EINVAL;
+
+	ret = gpio_request_by_name(dev, "gpio-mosi", 0, &plat->mosi,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	if (ret)
+		plat->flags |= SPI_MASTER_NO_TX;
+
+	ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso,
+				   GPIOD_IS_IN);
+	if (ret)
+		plat->flags |= SPI_MASTER_NO_RX;
+
+	if ((plat->flags & (SPI_MASTER_NO_RX | SPI_MASTER_NO_TX)) ==
+	    (SPI_MASTER_NO_RX | SPI_MASTER_NO_TX))
 		return -EINVAL;
 
 	return 0;
 }
 
 static const struct udevice_id soft_spi_ids[] = {
-	{ .compatible = "u-boot,soft-spi" },
+	{ .compatible = "spi-gpio" },
 	{ }
 };
 
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 5561f36..84b6786 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -45,12 +45,12 @@
 	return 0;
 }
 
-int spi_claim_bus(struct spi_slave *slave)
+int dm_spi_claim_bus(struct udevice *dev)
 {
-	struct udevice *dev = slave->dev;
 	struct udevice *bus = dev->parent;
 	struct dm_spi_ops *ops = spi_get_ops(bus);
 	struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
+	struct spi_slave *slave = dev_get_parent_priv(dev);
 	int speed;
 	int ret;
 
@@ -73,9 +73,8 @@
 	return ops->claim_bus ? ops->claim_bus(dev) : 0;
 }
 
-void spi_release_bus(struct spi_slave *slave)
+void dm_spi_release_bus(struct udevice *dev)
 {
-	struct udevice *dev = slave->dev;
 	struct udevice *bus = dev->parent;
 	struct dm_spi_ops *ops = spi_get_ops(bus);
 
@@ -83,10 +82,9 @@
 		ops->release_bus(dev);
 }
 
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-	     const void *dout, void *din, unsigned long flags)
+int dm_spi_xfer(struct udevice *dev, unsigned int bitlen,
+		const void *dout, void *din, unsigned long flags)
 {
-	struct udevice *dev = slave->dev;
 	struct udevice *bus = dev->parent;
 
 	if (bus->uclass->uc_drv->id != UCLASS_SPI)
@@ -95,6 +93,22 @@
 	return spi_get_ops(bus)->xfer(dev, bitlen, dout, din, flags);
 }
 
+int spi_claim_bus(struct spi_slave *slave)
+{
+	return dm_spi_claim_bus(slave->dev);
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	dm_spi_release_bus(slave->dev);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+	     const void *dout, void *din, unsigned long flags)
+{
+	return dm_spi_xfer(slave->dev, bitlen, dout, din, flags);
+}
+
 static int spi_post_bind(struct udevice *dev)
 {
 	/* Scan the bus for devices */
diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
index 2f3d43d..2f46d38 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -3,5 +3,6 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
 
+obj-$(CONFIG_DM_USB) += common.o
 obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o
 obj-$(CONFIG_USB_XHCI_FSL) += fsl-dt-fixup.o
diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c
new file mode 100644
index 0000000..35c2dc1
--- /dev/null
+++ b/drivers/usb/common/common.c
@@ -0,0 +1,40 @@
+/*
+ * Provides code common for host and device side USB.
+ *
+ * (C) Copyright 2016
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <linux/usb/otg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char *const usb_dr_modes[] = {
+	[USB_DR_MODE_UNKNOWN]		= "",
+	[USB_DR_MODE_HOST]		= "host",
+	[USB_DR_MODE_PERIPHERAL]	= "peripheral",
+	[USB_DR_MODE_OTG]		= "otg",
+};
+
+enum usb_dr_mode usb_get_dr_mode(int node)
+{
+	const void *fdt = gd->fdt_blob;
+	const char *dr_mode;
+	int i;
+
+	dr_mode = fdt_getprop(fdt, node, "dr_mode", NULL);
+	if (!dr_mode) {
+		error("usb dr_mode not found\n");
+		return USB_DR_MODE_UNKNOWN;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
+		if (!strcmp(dr_mode, usb_dr_modes[i]))
+			return i;
+
+	return USB_DR_MODE_UNKNOWN;
+}
diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index 36d4b23..5676a0f 100644
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -352,7 +352,9 @@
 	 */
 	__raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
 
-	clk->rate = (u64)(clk->parent->rate * 16) / div;
+	do_div(parent_rate, div);
+
+	clk->rate = parent_rate;
 
 	return 0;
 }
diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
index 7fd10e6..c01809e 100644
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra.c
@@ -620,6 +620,13 @@
 static int tegra_lcd_bind(struct udevice *dev)
 {
 	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+	const void *blob = gd->fdt_blob;
+	int node = dev->of_offset;
+	int rgb;
+
+	rgb = fdt_subnode_offset(blob, node, "rgb");
+	if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
+		return -ENODEV;
 
 	plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 		(1 << LCD_MAX_LOG2_BPP) / 8;
diff --git a/dts/Kconfig b/dts/Kconfig
index d585009..c56c129 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -62,6 +62,7 @@
 config OF_LIST
 	string "List of device tree files to include for DT control"
 	depends on SPL_LOAD_FIT
+	default DEFAULT_DEVICE_TREE
 	help
 	  This option specifies a list of device tree files to use for DT
 	  control. These will be packaged into a FIT. At run-time, SPL will
diff --git a/examples/api/Makefile b/examples/api/Makefile
index 4e9b8ea..6cffee7 100644
--- a/examples/api/Makefile
+++ b/examples/api/Makefile
@@ -11,8 +11,12 @@
 LOAD_ADDR = 0x1000000
 endif
 ifeq ($(ARCH),mips)
+ifdef CONFIG_64BIT
+LOAD_ADDR = 0xffffffff80200000
+else
 LOAD_ADDR = 0x80200000
 endif
+endif
 
 # Resulting ELF and binary exectuables will be named demo and demo.bin
 extra-y = demo
diff --git a/examples/api/crt0.S b/examples/api/crt0.S
index ced2c82..5a7049d 100644
--- a/examples/api/crt0.S
+++ b/examples/api/crt0.S
@@ -41,28 +41,29 @@
 	ldr	pc, [ip]
 
 #elif defined(CONFIG_MIPS)
+#include <asm/asm.h>
 	.text
 	.globl __start
 	.ent __start
 __start:
-	sw	$sp, search_hint
+	PTR_S	$sp, search_hint
 	b	main
 	.end __start
 
 	.globl syscall
 	.ent syscall
 syscall:
-	sw	$ra, return_addr
-	lw	$t9, syscall_ptr
+	PTR_S	$ra, return_addr
+	PTR_L	$t9, syscall_ptr
 	jalr	$t9
 	nop
-	lw	$ra, return_addr
+	PTR_L	$ra, return_addr
 	jr	$ra
 	nop
 	.end syscall
 
 return_addr:
-	.align 4
+	.align 8
 	.long 0
 #else
 #error No support for this arch!
@@ -70,7 +71,7 @@
 
 	.globl syscall_ptr
 syscall_ptr:
-	.align	4
+	.align	8
 	.long	0
 
 	.globl search_hint
diff --git a/examples/api/glue.c b/examples/api/glue.c
index d619518..8aabf32 100644
--- a/examples/api/glue.c
+++ b/examples/api/glue.c
@@ -77,7 +77,7 @@
 {
 	int c;
 
-	if (!syscall(API_GETC, NULL, (uint32_t)&c))
+	if (!syscall(API_GETC, NULL, &c))
 		return -1;
 
 	return c;
@@ -87,7 +87,7 @@
 {
 	int t;
 
-	if (!syscall(API_TSTC, NULL, (uint32_t)&t))
+	if (!syscall(API_TSTC, NULL, &t))
 		return -1;
 
 	return t;
@@ -95,12 +95,12 @@
 
 void ub_putc(char c)
 {
-	syscall(API_PUTC, NULL, (uint32_t)&c);
+	syscall(API_PUTC, NULL, &c);
 }
 
 void ub_puts(const char *s)
 {
-	syscall(API_PUTS, NULL, (uint32_t)s);
+	syscall(API_PUTS, NULL, s);
 }
 
 /****************************************
@@ -126,7 +126,7 @@
 	si.mr_no = UB_MAX_MR;
 	memset(&mr, 0, sizeof(mr));
 
-	if (!syscall(API_GET_SYS_INFO, &err, (u_int32_t)&si))
+	if (!syscall(API_GET_SYS_INFO, &err, &si))
 		return NULL;
 
 	return ((err) ? NULL : &si);
@@ -344,7 +344,7 @@
 {
 	char *value;
 
-	if (!syscall(API_ENV_GET, NULL, (uint32_t)name, (uint32_t)&value))
+	if (!syscall(API_ENV_GET, NULL, name, &value))
 		return NULL;
 
 	return value;
@@ -352,7 +352,7 @@
 
 void ub_env_set(const char *name, char *value)
 {
-	syscall(API_ENV_SET, NULL, (uint32_t)name, (uint32_t)value);
+	syscall(API_ENV_SET, NULL, name, value);
 }
 
 static char env_name[256];
@@ -369,7 +369,7 @@
 	 * 'name=val' string), since the API_ENUM_ENV call uses envmatch()
 	 * internally, which handles such case
 	 */
-	if (!syscall(API_ENV_ENUM, NULL, (uint32_t)last, (uint32_t)&env))
+	if (!syscall(API_ENV_ENUM, NULL, last, &env))
 		return NULL;
 
 	if (!env)
@@ -396,7 +396,7 @@
 {
 	int err = 0;
 
-	if (!syscall(API_DISPLAY_GET_INFO, &err, (uint32_t)type, (uint32_t)di))
+	if (!syscall(API_DISPLAY_GET_INFO, &err, type, di))
 		return API_ESYSC;
 
 	return err;
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 920a0a9..0d62067 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -65,6 +65,23 @@
 	: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "ip");
 #endif
 #elif defined(CONFIG_MIPS)
+#ifdef CONFIG_CPU_MIPS64
+/*
+ * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call-
+ * clobbered register that is also used to set gp ($26). Note that the
+ * jr instruction also executes the instruction immediately following
+ * it; however, GCC/mips generates an additional `nop' after each asm
+ * statement
+ */
+#define EXPORT_FUNC(f, a, x, ...) \
+	asm volatile (			\
+"	.globl " #x "\n"		\
+#x ":\n"				\
+"	ld	$25, %0($26)\n"		\
+"	ld	$25, %1($25)\n"		\
+"	jr	$25\n"			\
+        : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t9");
+#else
 /*
  * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call-
  * clobbered register that is also used to set gp ($26). Note that the
@@ -80,6 +97,7 @@
 "	lw	$25, %1($25)\n"		\
 "	jr	$25\n"			\
 	: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t9");
+#endif
 #elif defined(CONFIG_NIOS2)
 /*
  * gp holds the pointer to the global_data, r8 is call-clobbered
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 600a90e..826bd85 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -1254,7 +1254,7 @@
 
 #if defined(CONFIG_CMD_IDE) || \
     defined(CONFIG_CMD_SATA) || \
-    defined(CONFIG_CMD_SCSI) || \
+    defined(CONFIG_SCSI) || \
     defined(CONFIG_CMD_USB) || \
     defined(CONFIG_MMC)
 	printf("Interface:  ");
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 68b5f0b..2500c10 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -207,6 +207,16 @@
 struct fdtdec_phandle_args;
 
 /**
+ * gpio_xlate_offs_flags() - implementation for common use of dm_gpio_ops.xlate
+ *
+ * This routine sets the offset field to args[0] and the flags field to
+ * GPIOD_ACTIVE_LOW if the GPIO_ACTIVE_LOW flag is present in args[1].
+ *
+ */
+int gpio_xlate_offs_flags(struct udevice *dev, struct gpio_desc *desc,
+			  struct fdtdec_phandle_args *args);
+
+/**
  * struct struct dm_gpio_ops - Driver model GPIO operations
  *
  * Refer to functions above for description. These function largely copy
@@ -258,12 +268,11 @@
 	 *
 	 *   @desc->dev to @dev
 	 *   @desc->flags to 0
-	 *   @desc->offset to the value of the first argument in args, if any,
-	 *		otherwise -1 (which is invalid)
+	 *   @desc->offset to 0
 	 *
-	 * This method is optional so if the above defaults suit it can be
-	 * omitted. Typical behaviour is to set up the GPIOD_ACTIVE_LOW flag
-	 * in desc->flags.
+	 * This method is optional and defaults to gpio_xlate_offs_flags,
+	 * which will parse offset and the GPIO_ACTIVE_LOW flag in the first
+	 * two arguments.
 	 *
 	 * Note that @dev is passed in as a parameter to follow driver model
 	 * uclass conventions, even though it is already available as
diff --git a/include/ata.h b/include/ata.h
index 9d6f59c..dde377c 100644
--- a/include/ata.h
+++ b/include/ata.h
@@ -126,7 +126,7 @@
 
 #define ATA_BLOCKSIZE	512	/* bytes */
 #define ATA_BLOCKSHIFT	9	/* 2 ^ ATA_BLOCKSIZESHIFT = 512 */
-#define ATA_SECTORWORDS	(512 / sizeof(unsigned long))
+#define ATA_SECTORWORDS	(512 / sizeof(uint32_t))
 
 #ifndef ATA_RESET_TIME
 #define ATA_RESET_TIME	60	/* spec allows up to 31 seconds */
diff --git a/include/blk.h b/include/blk.h
index f624671..66a1c55 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -30,6 +30,7 @@
 	IF_TYPE_SD,
 	IF_TYPE_SATA,
 	IF_TYPE_HOST,
+	IF_TYPE_SYSTEMACE,
 
 	IF_TYPE_COUNT,			/* Number of interface types */
 };
@@ -62,6 +63,11 @@
 	char		product[20+1];	/* IDE Serial no, SCSI product */
 	char		revision[8+1];	/* firmware revision */
 #ifdef CONFIG_BLK
+	/*
+	 * For now we have a few functions which take struct blk_desc as a
+	 * parameter. This field allows them to look up the associated
+	 * device. Once these functions are removed we can drop this field.
+	 */
 	struct udevice *bdev;
 #else
 	unsigned long	(*block_read)(struct blk_desc *block_dev,
@@ -210,6 +216,25 @@
 	 */
 	unsigned long (*erase)(struct udevice *dev, lbaint_t start,
 			       lbaint_t blkcnt);
+
+	/**
+	 * select_hwpart() - select a particular hardware partition
+	 *
+	 * Some devices (e.g. MMC) can support partitioning at the hardware
+	 * level. This is quite separate from the normal idea of
+	 * software-based partitions. MMC hardware partitions must be
+	 * explicitly selected. Once selected only the region of the device
+	 * covered by that partition is accessible.
+	 *
+	 * The MMC standard provides for two boot partitions (numbered 1 and 2),
+	 * rpmb (3), and up to 4 addition general-purpose partitions (4-7).
+	 *
+	 * @desc:	Block device to update
+	 * @hwpart:	Hardware partition number to select. 0 means the raw
+	 *		device, 1 is the first partition, 2 is the second, etc.
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*select_hwpart)(struct udevice *dev, int hwpart);
 };
 
 #define blk_get_ops(dev)	((struct blk_ops *)(dev)->driver->ops)
@@ -269,7 +294,8 @@
  * @drv_name:	Driver name to use for the block device
  * @name:	Name for the device
  * @if_type:	Interface type (enum if_type_t)
- * @devnum:	Device number, specific to the interface type
+ * @devnum:	Device number, specific to the interface type, or -1 to
+ *		allocate the next available number
  * @blksz:	Block size of the device in bytes (typically 512)
  * @size:	Total size of the device in bytes
  * @devp:	the new device (which has not been probed)
@@ -279,6 +305,23 @@
 		      lbaint_t size, struct udevice **devp);
 
 /**
+ * blk_create_devicef() - Create a new named block device
+ *
+ * @parent:	Parent of the new device
+ * @drv_name:	Driver name to use for the block device
+ * @name:	Name for the device (parent name is prepended)
+ * @if_type:	Interface type (enum if_type_t)
+ * @devnum:	Device number, specific to the interface type, or -1 to
+ *		allocate the next available number
+ * @blksz:	Block size of the device in bytes (typically 512)
+ * @size:	Total size of the device in bytes
+ * @devp:	the new device (which has not been probed)
+ */
+int blk_create_devicef(struct udevice *parent, const char *drv_name,
+		       const char *name, int if_type, int devnum, int blksz,
+		       lbaint_t size, struct udevice **devp);
+
+/**
  * blk_prepare_device() - Prepare a block device for use
  *
  * This reads partition information from the device if supported.
@@ -298,6 +341,29 @@
  */
 int blk_unbind_all(int if_type);
 
+/**
+ * blk_find_max_devnum() - find the maximum device number for an interface type
+ *
+ * Finds the last allocated device number for an interface type @if_type. The
+ * next number is safe to use for a newly allocated device.
+ *
+ * @if_type:	Interface type to scan
+ * @return maximum device number found, or -ENODEV if none, or other -ve on
+ * error
+ */
+int blk_find_max_devnum(enum if_type if_type);
+
+/**
+ * blk_select_hwpart() - select a hardware partition
+ *
+ * Select a hardware partition if the device supports it (typically MMC does)
+ *
+ * @dev:	Device to update
+ * @hwpart:	Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_select_hwpart(struct udevice *dev, int hwpart);
+
 #else
 #include <errno.h>
 /*
@@ -340,6 +406,201 @@
 	blkcache_invalidate(block_dev->if_type, block_dev->devnum);
 	return block_dev->block_erase(block_dev, start, blkcnt);
 }
+
+/**
+ * struct blk_driver - Driver for block interface types
+ *
+ * This provides access to the block devices for each interface type. One
+ * driver should be provided using U_BOOT_LEGACY_BLK() for each interface
+ * type that is to be supported.
+ *
+ * @if_typename:	Interface type name
+ * @if_type:		Interface type
+ * @max_devs:		Maximum number of devices supported
+ * @desc:		Pointer to list of devices for this interface type,
+ *			or NULL to use @get_dev() instead
+ */
+struct blk_driver {
+	const char *if_typename;
+	enum if_type if_type;
+	int max_devs;
+	struct blk_desc *desc;
+	/**
+	 * get_dev() - get a pointer to a block device given its number
+	 *
+	 * Each interface allocates its own devices and typically
+	 * struct blk_desc is contained with the interface's data structure.
+	 * There is no global numbering for block devices. This method allows
+	 * the device for an interface type to be obtained when @desc is NULL.
+	 *
+	 * @devnum:	Device number (0 for first device on that interface,
+	 *		1 for second, etc.
+	 * @descp:	Returns pointer to the block device on success
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*get_dev)(int devnum, struct blk_desc **descp);
+
+	/**
+	 * select_hwpart() - Select a hardware partition
+	 *
+	 * Some devices (e.g. MMC) can support partitioning at the hardware
+	 * level. This is quite separate from the normal idea of
+	 * software-based partitions. MMC hardware partitions must be
+	 * explicitly selected. Once selected only the region of the device
+	 * covered by that partition is accessible.
+	 *
+	 * The MMC standard provides for two boot partitions (numbered 1 and 2),
+	 * rpmb (3), and up to 4 addition general-purpose partitions (4-7).
+	 * Partition 0 is the main user-data partition.
+	 *
+	 * @desc:	Block device descriptor
+	 * @hwpart:	Hardware partition number to select. 0 means the main
+	 *		user-data partition, 1 is the first partition, 2 is
+	 *		the second, etc.
+	 * @return 0 if OK, other value for an error
+	 */
+	int (*select_hwpart)(struct blk_desc *desc, int hwpart);
+};
+
+/*
+ * Declare a new U-Boot legacy block driver. New drivers should use driver
+ * model (UCLASS_BLK).
+ */
+#define U_BOOT_LEGACY_BLK(__name)					\
+	ll_entry_declare(struct blk_driver, __name, blk_driver)
+
+struct blk_driver *blk_driver_lookup_type(int if_type);
+
 #endif /* !CONFIG_BLK */
 
+/**
+ * blk_get_devnum_by_typename() - Get a block device by type and number
+ *
+ * This looks through the available block devices of the given type, returning
+ * the one with the given @devnum.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return point to block device descriptor, or NULL if not found
+ */
+struct blk_desc *blk_get_devnum_by_type(enum if_type if_type, int devnum);
+
+/**
+ * blk_get_devnum_by_type() - Get a block device by type name, and number
+ *
+ * This looks up the block device type based on @if_typename, then calls
+ * blk_get_devnum_by_type().
+ *
+ * @if_typename:	Block device type name
+ * @devnum:		Device number
+ * @return point to block device descriptor, or NULL if not found
+ */
+struct blk_desc *blk_get_devnum_by_typename(const char *if_typename,
+					    int devnum);
+
+/**
+ * blk_dselect_hwpart() - select a hardware partition
+ *
+ * This selects a hardware partition (such as is supported by MMC). The block
+ * device size may change as this effectively points the block device to a
+ * partition at the hardware level. See the select_hwpart() method above.
+ *
+ * @desc:	Block device descriptor for the device to select
+ * @hwpart:	Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_dselect_hwpart(struct blk_desc *desc, int hwpart);
+
+/**
+ * blk_list_part() - list the partitions for block devices of a given type
+ *
+ * This looks up the partition type for each block device of type @if_type,
+ * then displays a list of partitions.
+ *
+ * @if_type:	Block device type
+ * @return 0 if OK, -ENODEV if there is none of that type
+ */
+int blk_list_part(enum if_type if_type);
+
+/**
+ * blk_list_devices() - list the block devices of a given type
+ *
+ * This lists each block device of the type @if_type, showing the capacity
+ * as well as type-specific information.
+ *
+ * @if_type:	Block device type
+ */
+void blk_list_devices(enum if_type if_type);
+
+/**
+ * blk_show_device() - show information about a given block device
+ *
+ * This shows the block device capacity as well as type-specific information.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return 0 if OK, -ENODEV for invalid device number
+ */
+int blk_show_device(enum if_type if_type, int devnum);
+
+/**
+ * blk_print_device_num() - show information about a given block device
+ *
+ * This is similar to blk_show_device() but returns an error if the block
+ * device type is unknown.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return 0 if OK, -ENODEV for invalid device number, -ENOENT if the block
+ * device is not connected
+ */
+int blk_print_device_num(enum if_type if_type, int devnum);
+
+/**
+ * blk_print_part_devnum() - print the partition information for a device
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return 0 if OK, -ENOENT if the block device is not connected, -ENOSYS if
+ * the interface type is not supported, other -ve on other error
+ */
+int blk_print_part_devnum(enum if_type if_type, int devnum);
+
+/**
+ * blk_read_devnum() - read blocks from a device
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @blkcnt:	Number of blocks to read
+ * @buffer:	Address to write data to
+ * @return number of blocks read, or -ve error number on error
+ */
+ulong blk_read_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		      lbaint_t blkcnt, void *buffer);
+
+/**
+ * blk_write_devnum() - write blocks to a device
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @blkcnt:	Number of blocks to write
+ * @buffer:	Address to read data from
+ * @return number of blocks written, or -ve error number on error
+ */
+ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		       lbaint_t blkcnt, const void *buffer);
+
+/**
+ * blk_select_hwpart_devnum() - select a hardware partition
+ *
+ * This is similar to blk_dselect_hwpart() but it looks up the interface and
+ * device number.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @hwpart:	Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart);
+
 #endif
diff --git a/include/bootstage.h b/include/bootstage.h
index 9765360..0880a68 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -198,6 +198,7 @@
 	BOOTSTAGE_ID_ACCUM_SCSI,
 	BOOTSTAGE_ID_ACCUM_SPI,
 	BOOTSTAGE_ID_ACCUM_DECOMP,
+	BOOTSTAGE_ID_FPGA_INIT,
 
 	/* a few spare for the user, from here */
 	BOOTSTAGE_ID_USER,
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index ed502a1..b5fd6c6 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -45,7 +45,7 @@
 #define CONFIG_CMD_READ		/* Read data from partition	*/
 #define CONFIG_CMD_SANDBOX	/* sb command to access sandbox features */
 #define CONFIG_CMD_SAVES	/* save S record dump		*/
-#define CONFIG_CMD_SCSI		/* SCSI Support			*/
+#define CONFIG_SCSI		/* SCSI Support			*/
 #define CONFIG_CMD_SDRAM	/* SDRAM DIMM SPD info printout */
 #define CONFIG_CMD_TERMINAL	/* built-in Serial Terminal	*/
 #define CONFIG_CMD_UBI		/* UBI Support			*/
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 7f67344..5a8d7f2 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -165,7 +165,7 @@
 	BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_CMD_SATA
 #endif
 
-#ifdef CONFIG_CMD_SCSI
+#ifdef CONFIG_SCSI
 #define BOOTENV_RUN_SCSI_INIT "run scsi_init; "
 #define BOOTENV_SET_SCSI_NEED_INIT "setenv scsi_need_init; "
 #define BOOTENV_SHARED_SCSI \
@@ -185,9 +185,9 @@
 #define BOOTENV_SET_SCSI_NEED_INIT
 #define BOOTENV_SHARED_SCSI
 #define BOOTENV_DEV_SCSI \
-	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_CMD_SCSI
+	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI
 #define BOOTENV_DEV_NAME_SCSI \
-	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_CMD_SCSI
+	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI
 #endif
 
 #ifdef CONFIG_CMD_IDE
diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h
index 2666191..2ad54b7 100644
--- a/include/config_fallbacks.h
+++ b/include/config_fallbacks.h
@@ -45,7 +45,7 @@
 /* Rather than repeat this expression each time, add a define for it */
 #if defined(CONFIG_CMD_IDE) || \
 	defined(CONFIG_CMD_SATA) || \
-	defined(CONFIG_CMD_SCSI) || \
+	defined(CONFIG_SCSI) || \
 	defined(CONFIG_CMD_USB) || \
 	defined(CONFIG_CMD_PART) || \
 	defined(CONFIG_CMD_GPT) || \
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 26d92da..f3036c1 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -373,7 +373,7 @@
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
-    #define CONFIG_CMD_SCSI
+    #define CONFIG_SCSI
 #endif
 
 /*
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 8c4e5e2..bb7f38e 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -576,7 +576,7 @@
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #endif
 
 /*
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index e7f01d0..f6d45a9 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -449,7 +449,7 @@
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #endif
 
 #define CONFIG_WATCHDOG			/* watchdog enabled */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 2f94c82..9b2623c 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -354,8 +354,6 @@
 
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
-#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
-
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
@@ -612,7 +610,7 @@
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
-    #define CONFIG_CMD_SCSI
+    #define CONFIG_SCSI
 #endif
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 4bd06a4..4506d86 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -43,7 +43,7 @@
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_FDC
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SAVES
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 32d7d4d..d53b0fd 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -75,7 +75,7 @@
 
 /* SATA */
 #define CONFIG_BOARD_LATE_INIT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
new file mode 100644
index 0000000..2beffa4
--- /dev/null
+++ b/include/configs/ap121.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE            0x9f000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_HZ                   1000
+#define CONFIG_SYS_MHZ                  200
+#define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE          0x8000
+#define CONFIG_SYS_ICACHE_SIZE          0x10000
+#define CONFIG_SYS_CACHELINE_SIZE       32
+
+#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN           0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN       0x20000
+
+#define CONFIG_SYS_SDRAM_BASE           0x80000000
+#define CONFIG_SYS_LOAD_ADDR            0x81000000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x8000
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
+
+#define CONFIG_BAUDRATE                 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTDELAY                3
+#define CONFIG_BOOTARGS                 "console=ttyS0,115200 " \
+					"root=/dev/mtdblock2 " \
+					"rootfstype=squashfs"
+#define CONFIG_BOOTCOMMAND              "sf probe;" \
+					"mtdparts default;" \
+					"bootm 0x9f300000"
+#define CONFIG_LZMA
+
+#define MTDIDS_DEFAULT                  "nor0=spi-flash.0"
+#define MTDPARTS_DEFAULT                "mtdparts=spi-flash.0:" \
+					"256k(u-boot),64k(u-boot-env)," \
+					"2752k(rootfs),896k(uImage)," \
+					"64k(NVRAM),64k(ART)"
+
+#define CONFIG_ENV_SPI_MAX_HZ           25000000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET               0x40000
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#define CONFIG_ENV_SIZE                 0x10000
+
+/*
+ * Command
+ */
+#define CONFIG_CMD_MTDPARTS
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE               256
+#define CONFIG_SYS_MAXARGS              16
+#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START        0x80100000
+#define CONFIG_SYS_MEMTEST_END          0x83f00000
+#define CONFIG_CMD_MEMTEST
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
new file mode 100644
index 0000000..7b69e10
--- /dev/null
+++ b/include/configs/ap143.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE            0x9f000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_HZ                   1000
+#define CONFIG_SYS_MHZ                  325
+#define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE          0x8000
+#define CONFIG_SYS_ICACHE_SIZE          0x10000
+#define CONFIG_SYS_CACHELINE_SIZE       32
+
+#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN           0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN       0x20000
+
+#define CONFIG_SYS_SDRAM_BASE           0x80000000
+#define CONFIG_SYS_LOAD_ADDR            0x81000000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x2000
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_CLK          25000000
+#define CONFIG_BAUDRATE                 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTDELAY                3
+#define CONFIG_BOOTARGS                 "console=ttyS0,115200 " \
+					"root=/dev/mtdblock2 " \
+					"rootfstype=squashfs"
+#define CONFIG_BOOTCOMMAND              "sf probe;" \
+					"mtdparts default;" \
+					"bootm 0x9f300000"
+#define CONFIG_LZMA
+
+#define MTDIDS_DEFAULT                  "nor0=spi-flash.0"
+#define MTDPARTS_DEFAULT                "mtdparts=spi-flash.0:" \
+					"256k(u-boot),64k(u-boot-env)," \
+					"2752k(rootfs),896k(uImage)," \
+					"64k(NVRAM),64k(ART)"
+
+#define CONFIG_ENV_SPI_MAX_HZ           25000000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET               0x40000
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#define CONFIG_ENV_SIZE                 0x10000
+
+/*
+ * Command
+ */
+#define CONFIG_CMD_MTDPARTS
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE               256
+#define CONFIG_SYS_MAXARGS              16
+#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START        0x80100000
+#define CONFIG_SYS_MEMTEST_END          0x83f00000
+#define CONFIG_CMD_MEMTEST
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index 1bd4729..05d2d45 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -59,7 +59,6 @@
  * I2C configuration
  */
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
 #define CONFIG_I2C_ENV_EEPROM_BUS	2
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_SYS_I2C_SPEED1		100000
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 9a12552..1f20ec3 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -255,4 +255,15 @@
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
+
 #endif	/* __CONFIG_CM_FX6_H */
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index c4f1d4f..6dbc9e9 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -165,6 +165,17 @@
 #define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
 #define STATUS_LED_BOOT			0
 
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
+
 #ifndef CONFIG_SPL_BUILD
 /*
  * Enable PCA9555 at I2C0-0x26.
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 5d58116..0fb8530 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -361,4 +361,15 @@
 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
 
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3"
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index 7cedb67..7c087c6 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -305,4 +305,15 @@
 
 #define CONFIG_OMAP3_SPI
 
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v1, v2, v3"
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index ee818ed..c2dbd31 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -170,4 +170,15 @@
 #define CONFIG_SPL_I2C_SUPPORT
 #define CONFIG_SPL_POWER_SUPPORT
 
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
+
 #endif	/* __CONFIG_CM_T43_H */
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index 9b13aa6..ff63d7a 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -60,7 +60,7 @@
 #define CONFIG_SPL_SATA_BOOT_DEVICE		0
 #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION	1
 
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
@@ -81,6 +81,17 @@
 
 /* Enabled commands */
 
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
+
 /* USB Networking options */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index d84dde3..3539a62 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -27,7 +27,7 @@
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 79b6c09..8a0cd66 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -230,7 +230,7 @@
 
 /* SATA */
 #define CONFIG_BOARD_LATE_INIT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
diff --git a/include/configs/efi-x86.h b/include/configs/efi-x86.h
index 6dd0b32..95e46c5 100644
--- a/include/configs/efi-x86.h
+++ b/include/configs/efi-x86.h
@@ -18,7 +18,7 @@
 #undef CONFIG_VIDEO
 #undef CONFIG_CFB_CONSOLE
 #undef CONFIG_SCSI_AHCI
-#undef CONFIG_CMD_SCSI
+#undef CONFIG_SCSI
 #undef CONFIG_INTEL_ICH6_GPIO
 #undef CONFIG_USB_EHCI_PCI
 
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index 2f1f6d4..40f7fba 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -29,7 +29,7 @@
 
 /* SATA is not supported in Quark SoC */
 #undef CONFIG_SCSI_AHCI
-#undef CONFIG_CMD_SCSI
+#undef CONFIG_SCSI
 
 /* Video is not supported in Quark SoC */
 #undef CONFIG_VIDEO
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index 3bce12b..5cefddc 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -51,7 +51,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 
 #define CONFIG_BOOT_RETRY_TIME		-1
 #define CONFIG_RESET_TO_RETRY
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 68d3fd7..9bd9f6e 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -48,12 +48,16 @@
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	800 /* 400 KB */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
 #define CONFIG_SYS_MONITOR_LEN  (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024)
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#define CONFIG_SPL_EXT_SUPPORT
 #endif
 
 /* SATA support */
 #if defined(CONFIG_SPL_SATA_SUPPORT)
 #define CONFIG_SPL_SATA_BOOT_DEVICE		0
 #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#define CONFIG_SPL_EXT_SUPPORT
 #endif
 
 /* Define the payload for FAT/EXT support */
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index d71a229..af1f73d 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -108,7 +108,7 @@
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_DOS_PARTITION
 #define CONFIG_BOARD_LATE_INIT
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 16a536a..4b27114 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -44,7 +44,7 @@
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_DOS_PARTITION
 #define CONFIG_BOARD_LATE_INIT
 
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 45827f6..3baca64 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -62,7 +62,7 @@
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_DOS_PARTITION
 #define CONFIG_BOARD_LATE_INIT
 
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 674d1f6..95ad128 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -40,6 +40,6 @@
 #define CONFIG_X86EMU_RAW_IO
 
 #define CONFIG_ENV_SECT_SIZE		0x1000
-#define CONFIG_ENV_OFFSET		0x007fe000
+#define CONFIG_ENV_OFFSET		0x006ef000
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/novena.h b/include/configs/novena.h
index cfb92d6..2382951 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -75,7 +75,6 @@
 
 /* SPL */
 #define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_EXT_SUPPORT
 #define CONFIG_SPL_MMC_SUPPORT
 #include "imx6_spl.h"			/* common IMX6 SPL configuration */
 
@@ -150,6 +149,7 @@
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_STDIO_DEREGISTER
 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 86cefa3..4ddc492 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -115,7 +115,7 @@
 /* Max time to hold reset on this board, see doc/README.omap-reset-time */
 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
 
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index a7cd003..702967c 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -58,6 +58,10 @@
 #define CONFIG_CMD_IDE
 #define CONFIG_DOS_PARTITION
 
+#ifdef CONFIG_SYS_BIG_ENDIAN
+#define CONFIG_IDE_SWAP_IO
+#endif
+
 #define CONFIG_SYS_IDE_MAXBUS		2
 #define CONFIG_SYS_ATA_IDE0_OFFSET	0x1f0
 #define CONFIG_SYS_ATA_IDE1_OFFSET	0x170
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 394382c..2394549 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -58,6 +58,10 @@
 #define CONFIG_CMD_IDE
 #define CONFIG_DOS_PARTITION
 
+#ifdef CONFIG_SYS_BIG_ENDIAN
+#define CONFIG_IDE_SWAP_IO
+#endif
+
 #define CONFIG_SYS_IDE_MAXBUS		2
 #define CONFIG_SYS_ATA_IDE0_OFFSET	0x1f0
 #define CONFIG_SYS_ATA_IDE1_OFFSET	0x170
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
index b0d2ffe..476d37d 100644
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@@ -43,7 +43,7 @@
 #define CONFIG_ATAPI
 
 #undef CONFIG_SCSI_AHCI
-#undef CONFIG_CMD_SCSI
+#undef CONFIG_SCSI
 #else
 #define CONFIG_SCSI_DEV_LIST		\
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI}
diff --git a/include/configs/sama5d2_ptc.h b/include/configs/sama5d2_ptc.h
new file mode 100644
index 0000000..d91d75e
--- /dev/null
+++ b/include/configs/sama5d2_ptc.h
@@ -0,0 +1,155 @@
+/*
+ * Configuration settings for the SAMA5D2 PTC Engineering board.
+ *
+ * Copyright (C) 2016 Atmel
+ *		      Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* No NOR flash, this definition should put before common header */
+#define CONFIG_SYS_NO_FLASH
+
+#include "at91-sama5_common.h"
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_UART0
+#define CONFIG_USART_ID			ATMEL_ID_UART0
+
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x210000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+#undef CONFIG_AT91_GPIO
+#define CONFIG_ATMEL_PIO4
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+
+/* SerialFlash */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#endif
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_CMD_NAND_TRIMFFS
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
+#define CONFIG_USB_STORAGE
+#endif
+
+/* USB device */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_ATMEL_USBA
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D2_PTC"
+
+#if defined(CONFIG_CMD_USB)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB_SEARCH_PHY
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_ENV_OFFSET_REDUND
+#undef CONFIG_BOOTCOMMAND
+/* u-boot env in nand flash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x200000
+#define CONFIG_ENV_OFFSET_REDUND	0x400000
+#define CONFIG_BOOTCOMMAND		"nand read 0x21000000 0xb80000 0x80000;"	\
+					"nand read 0x22000000 0x600000 0x600000;"	\
+					"bootz 0x22000000 - 0x21000000"
+#endif
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,57600 earlyprintk "				\
+	"mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) "	\
+	"rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
+
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x200000
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_PMECC_CAP		8
+#define CONFIG_PMECC_SECTOR_SIZE	512
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x1000
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_OOBSIZE		224
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x40000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+#endif
+
+#endif
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 9790a14..23a0c40 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -192,4 +192,29 @@
 #define CONFIG_CMD_LZMADEC
 #define CONFIG_CMD_DATE
 
+#define CONFIG_CMD_IDE
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+#define CONFIG_SYS_ATA_BASE_ADDR	0x100
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_REG_OFFSET	1
+#define CONFIG_SYS_ATA_ALT_OFFSET	2
+#define CONFIG_SYS_ATA_STRIDE		4
+
+#define CONFIG_SCSI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_DEVICE	2
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	8
+#define CONFIG_SYS_SCSI_MAX_LUN		4
+
+#define CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+
+#define CONFIG_SYSTEMACE
+#define CONFIG_SYS_SYSTEMACE_WIDTH	16
+#define CONFIG_SYS_SYSTEMACE_BASE	0
+
+#define CONFIG_GENERIC_MMC
+
 #endif
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index a7c7aef..c9970f1 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -297,8 +297,6 @@
 
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 
-#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
-
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 4fdc09a..f657766 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -173,7 +173,6 @@
  * I2C support
  */
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
 #define CONFIG_SYS_I2C_BUS_MAX		4
 #define CONFIG_SYS_I2C_BASE		SOCFPGA_I2C0_ADDRESS
 #define CONFIG_SYS_I2C_BASE1		SOCFPGA_I2C1_ADDRESS
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index c4b6234..7b2d262 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -35,7 +35,6 @@
 
 /* I2C driver configuration */
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
 #if defined(CONFIG_SPEAR600)
 #define CONFIG_SYS_I2C_BASE			0xD0200000
 #elif defined(CONFIG_SPEAR300)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 2406115..ac2d931 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -125,7 +125,7 @@
 #define CONFIG_SYS_SCSI_MAX_LUN		1
 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 					 CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #endif
 
 #define CONFIG_SETUP_MEMORY_TAGS
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index 1caa858..dda70c5 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -64,6 +64,7 @@
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PREBOOT
 
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index b049be4..2135af0 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -153,6 +153,7 @@
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_DM_MMC
 #undef CONFIG_TIMER
+#undef CONFIG_DM_ETH
 #endif
 
 #endif /* __CONFIG_TI_OMAP5_COMMON_H */
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
new file mode 100644
index 0000000..2b9e92e
--- /dev/null
+++ b/include/configs/tplink_wdr4300.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE		0xa1000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_MHZ			280
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE		0x8000
+#define CONFIG_SYS_ICACHE_SIZE		0x10000
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN		0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN	0x20000
+
+#define CONFIG_SYS_SDRAM_BASE		0xa0000000
+#define CONFIG_SYS_LOAD_ADDR		0xa1000000
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_CLK		40000000
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTARGS			\
+	"console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
+#define CONFIG_BOOTCOMMAND		\
+	"dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr"
+#define CONFIG_LZMA
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			0x10000
+
+/*
+ * Command
+ */
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
+#define CONFIG_CMDLINE_EDITING			/* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/* USB, USB storage, USB ethernet */
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_IS_TDI
+
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x83f00000
+#define CONFIG_CMD_MEMTEST
+
+#define CONFIG_USE_PRIVATE_LIBGCC
+
+#define CONFIG_CMD_MII
+#define CONFIG_PHY_GIGE
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index badb955..77ced71 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -16,7 +16,6 @@
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_EXT_SUPPORT
 
 /* common IMX6 SPL configuration */
 #include "imx6_spl.h"
diff --git a/include/configs/x600.h b/include/configs/x600.h
index d7da0b2..5fdd2be 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -85,7 +85,6 @@
 
 /* I2C config options */
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
 #define CONFIG_SYS_I2C_BASE			0xD0200000
 #define CONFIG_SYS_I2C_SPEED			400000
 #define CONFIG_SYS_I2C_SLAVE			0x02
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index a2822e0..b4aad6c 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -100,7 +100,7 @@
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_GETTIME
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 
 #define CONFIG_CMD_ZBOOT
 
@@ -193,14 +193,19 @@
 #define CONFIG_HOSTNAME		x86
 #define CONFIG_BOOTFILE		"bzImage"
 #define CONFIG_LOADADDR		0x1000000
-#define CONFIG_RAMDISK_ADDR		0x4000000
+#define CONFIG_RAMDISK_ADDR	0x4000000
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+#define CONFIG_OTHBOOTARGS	"othbootargs=\0"
+#else
+#define CONFIG_OTHBOOTARGS	"othbootargs=acpi=off\0"
+#endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS			\
 	CONFIG_STD_DEVICES_SETTINGS			\
 	"pciconfighost=1\0"				\
 	"netdev=eth0\0"					\
 	"consoledev=ttyS0\0"				\
-	"othbootargs=acpi=off\0"			\
+	CONFIG_OTHBOOTARGS				\
 	"ramdiskaddr=0x4000000\0"			\
 	"ramdiskfile=initramfs.gz\0"
 
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 060bca9..b2fa164 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -41,7 +41,7 @@
 # define CONFIG_IDENT_STRING		" Xilinx ZynqMP"
 #endif
 
-#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR		0xfffffffc
 
 /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
 #if !defined(COUNTER_FREQUENCY)
@@ -65,6 +65,9 @@
 #define CONFIG_CMD_ENV
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_ISO_PARTITION
+#endif
 #define CONFIG_MP
 
 /* BOOTP options */
@@ -74,10 +77,24 @@
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_MAY_FAIL
 #define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_PXE_CLIENTARCH     0x100
+
+/* Diff from config_distro_defaults.h */
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_AUTO_COMPLETE
+
+/* PXE */
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
 
 #if defined(CONFIG_ZYNQ_SDHCI)
 # define CONFIG_MMC
 # define CONFIG_GENERIC_MMC
+# define CONFIG_SUPPORT_EMMC_BOOT
 # define CONFIG_SDHCI
 # ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
 #  define CONFIG_ZYNQ_SDHCI_MAX_FREQ	200000000
@@ -133,6 +150,7 @@
 #endif
 
 /* Initial environment variables */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"kernel_addr=0x80000\0" \
 	"fdt_addr=0x7000000\0" \
@@ -143,8 +161,8 @@
 		"load mmc $sdbootdev:$partid $kernel_addr Image && " \
 		"booti $kernel_addr - $fdt_addr\0" \
 	DFU_ALT_INFO
+#endif
 
-#define CONFIG_PREBOOT		"run bootargs"
 #define CONFIG_BOOTCOMMAND	"run $modeboot"
 #define CONFIG_BOOTDELAY	3
 
@@ -201,7 +219,7 @@
 #define CONFIG_SYS_SCSI_MAX_LUN		1
 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 					 CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #endif
 
 #define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
@@ -212,4 +230,41 @@
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_CLOCKS
 
+#define CONFIG_SPL_TEXT_BASE		0xfffc0000
+#define CONFIG_SPL_MAX_SIZE		0x20000
+
+/* Just random location in OCM */
+#define CONFIG_SPL_BSS_START_ADDR	0x1000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x2000000
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_RAM_DEVICE
+
+#define CONFIG_SPL_OS_BOOT
+/* u-boot is like dtb */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME	"u-boot.bin"
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x8000000
+
+/* ATF is my kernel image */
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"atf.ub"
+
+/* FIT load address for RAM boot */
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	0x10000000
+
+/* MMC support */
+#ifdef CONFIG_ZYNQ_SDHCI
+# define CONFIG_SPL_MMC_SUPPORT
+# define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0 /* unused */
+# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0 /* unused */
+# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0 /* unused */
+# define CONFIG_SPL_LIBDISK_SUPPORT
+# define CONFIG_SPL_FAT_SUPPORT
+# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+#endif
+
 #endif /* __XILINX_ZYNQMP_H */
diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h
index 30db2e4..81079fe 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -48,6 +48,12 @@
 
 #define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZCU102"
 
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ZYNQ_EEPROM_BUS		5
+#define CONFIG_ZYNQ_GEM_EEPROM_ADDR	0x54
+#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET	0x20
+
 #define CONFIG_KERNEL_FDT_OFST_SIZE \
 	"kernel_offset=0x180000\0" \
 	"fdt_offset=0x100000\0" \
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index a3e4aec..82ece0d 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -315,11 +315,7 @@
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
-#ifdef CONFIG_OF_SEPARATE
-# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot-dtb.img"
-#else
-# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot.img"
-#endif
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot.img"
 #endif
 
 /* Disable dcache for SPL just for sure */
diff --git a/include/cpsw.h b/include/cpsw.h
index cf1d30b..257d12a 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -21,6 +21,7 @@
 	u32		sliver_reg_ofs;
 	int		phy_addr;
 	int		phy_if;
+	int		phy_of_handle;
 };
 
 enum {
@@ -51,5 +52,6 @@
 };
 
 int cpsw_register(struct cpsw_platform_data *data);
+int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr);
 
 #endif /* _CPSW_H_  */
diff --git a/include/dm/device.h b/include/dm/device.h
index 8970fc0..f03bcd3 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -41,6 +41,9 @@
 /* Device is bound */
 #define DM_FLAG_BOUND			(1 << 6)
 
+/* Device name is allocated and should be freed on unbind() */
+#define DM_NAME_ALLOCED			(1 << 7)
+
 /**
  * struct udevice - An instance of a driver
  *
@@ -523,6 +526,9 @@
  * this is unnecessary but for probed devices which don't get a useful name
  * this function can be helpful.
  *
+ * The name is allocated and will be freed automatically when the device is
+ * unbound.
+ *
  * @dev:	Device to update
  * @name:	New name (this string is allocated new memory and attached to
  *		the device)
@@ -532,6 +538,39 @@
 int device_set_name(struct udevice *dev, const char *name);
 
 /**
+ * device_set_name_alloced() - note that a device name is allocated
+ *
+ * This sets the DM_NAME_ALLOCED flag for the device, so that when it is
+ * unbound the name will be freed. This avoids memory leaks.
+ *
+ * @dev:	Device to update
+ */
+void device_set_name_alloced(struct udevice *dev);
+
+/**
+ * of_device_is_compatible() - check if the device is compatible with the compat
+ *
+ * This allows to check whether the device is comaptible with the compat.
+ *
+ * @dev:	udevice pointer for which compatible needs to be verified.
+ * @compat:	Compatible string which needs to verified in the given
+ *		device
+ * @return true if OK, false if the compatible is not found
+ */
+bool of_device_is_compatible(struct udevice *dev, const char *compat);
+
+/**
+ * of_machine_is_compatible() - check if the machine is compatible with
+ *				the compat
+ *
+ * This allows to check whether the machine is comaptible with the compat.
+ *
+ * @compat:	Compatible string which needs to verified
+ * @return true if OK, false if the compatible is not found
+ */
+bool of_machine_is_compatible(const char *compat);
+
+/**
  * device_is_on_pci_bus - Test if a device is on a PCI bus
  *
  * @dev:	device to test
diff --git a/include/dm/platform_data/serial_coldfire.h b/include/dm/platform_data/serial_coldfire.h
new file mode 100644
index 0000000..5d86456
--- /dev/null
+++ b/include/dm/platform_data/serial_coldfire.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2015  Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __serial_coldfire_h
+#define __serial_coldfire_h
+
+/*
+ * struct coldfire_serial_platdata - information about a coldfire port
+ *
+ * @base:               Uart port base register address
+ * @port:               Uart port index, for cpu with pinmux for uart / gpio
+ * baudrtatre:          Uart port baudrate
+ */
+struct coldfire_serial_platdata {
+	unsigned long base;
+	int port;
+	int baudrate;
+};
+
+#endif /* __serial_coldfire_h */
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index cbf9b2c..a5cf6e2 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -26,11 +26,11 @@
 
 	/* U-Boot uclasses start here - in alphabetical order */
 	UCLASS_ADC,		/* Analog-to-digital converter */
+	UCLASS_AHCI,		/* SATA disk controller */
 	UCLASS_BLK,		/* Block device */
 	UCLASS_CLK,		/* Clock source, e.g. used by peripherals */
 	UCLASS_CPU,		/* CPU, typically part of an SoC */
 	UCLASS_CROS_EC,		/* Chrome OS EC */
-	UCLASS_DISK,		/* Disk controller, e.g. SATA */
 	UCLASS_DISPLAY,		/* Display (e.g. DisplayPort, HDMI) */
 	UCLASS_DMA,		/* Direct Memory Access */
 	UCLASS_RAM,		/* RAM controller */
diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
new file mode 100644
index 0000000..1843757
--- /dev/null
+++ b/include/dt-bindings/net/ti-dp83867.h
@@ -0,0 +1,35 @@
+/*
+ * TI DP83867 PHY drivers
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ */
+
+#ifndef _DT_BINDINGS_TI_DP83867_H
+#define _DT_BINDINGS_TI_DP83867_H
+
+/* PHY CTRL bits */
+#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB	0x00
+#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB	0x01
+#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB	0x02
+#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB	0x03
+
+/* RGMIIDCTL internal delay for rx and tx */
+#define DP83867_RGMIIDCTL_250_PS	0x0
+#define DP83867_RGMIIDCTL_500_PS	0x1
+#define DP83867_RGMIIDCTL_750_PS	0x2
+#define DP83867_RGMIIDCTL_1_NS		0x3
+#define DP83867_RGMIIDCTL_1_25_NS	0x4
+#define DP83867_RGMIIDCTL_1_50_NS	0x5
+#define DP83867_RGMIIDCTL_1_75_NS	0x6
+#define DP83867_RGMIIDCTL_2_00_NS	0x7
+#define DP83867_RGMIIDCTL_2_25_NS	0x8
+#define DP83867_RGMIIDCTL_2_50_NS	0x9
+#define DP83867_RGMIIDCTL_2_75_NS	0xa
+#define DP83867_RGMIIDCTL_3_00_NS	0xb
+#define DP83867_RGMIIDCTL_3_25_NS	0xc
+#define DP83867_RGMIIDCTL_3_50_NS	0xd
+#define DP83867_RGMIIDCTL_3_75_NS	0xe
+#define DP83867_RGMIIDCTL_4_00_NS	0xf
+
+#endif
diff --git a/include/eeprom_field.h b/include/eeprom_field.h
new file mode 100644
index 0000000..94e259f
--- /dev/null
+++ b/include/eeprom_field.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2009-2016 CompuLab, Ltd.
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FIELD_
+#define _FIELD_
+
+#define PRINT_FIELD_SEGMENT	"%-30s"
+
+struct eeprom_field {
+	char *name;
+	int size;
+	unsigned char *buf;
+
+	void (*print)(const struct eeprom_field *eeprom_field);
+	int (*update)(struct eeprom_field *eeprom_field, char *value);
+};
+
+void eeprom_field_print_bin(const struct eeprom_field *field);
+int eeprom_field_update_bin(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_bin_rev(const struct eeprom_field *field);
+int eeprom_field_update_bin_rev(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_mac(const struct eeprom_field *field);
+int eeprom_field_update_mac(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_ascii(const struct eeprom_field *field);
+int eeprom_field_update_ascii(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_reserved(const struct eeprom_field *field);
+int eeprom_field_update_reserved(struct eeprom_field *field, char *value);
+
+#endif
diff --git a/include/eeprom_layout.h b/include/eeprom_layout.h
new file mode 100644
index 0000000..459b99d
--- /dev/null
+++ b/include/eeprom_layout.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2009-2016 CompuLab, Ltd.
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LAYOUT_
+#define _LAYOUT_
+
+#define RESERVED_FIELDS			NULL
+#define LAYOUT_VERSION_UNRECOGNIZED	-1
+#define LAYOUT_VERSION_AUTODETECT	-2
+
+struct eeprom_layout {
+	struct eeprom_field *fields;
+	int num_of_fields;
+	int layout_version;
+	unsigned char *data;
+	int data_size;
+	void (*print)(const struct eeprom_layout *eeprom_layout);
+	int (*update)(struct eeprom_layout *eeprom_layout, char *field_name,
+		      char *new_data);
+};
+
+void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf,
+			 unsigned int buf_size, int layout_version);
+__weak void __eeprom_layout_assign(struct eeprom_layout *layout,
+				   int layout_version);
+
+#endif
diff --git a/include/flash.h b/include/flash.h
index c6321a0..2a5e13a 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -400,6 +400,9 @@
 #define FLASH_STM800DT	0x00D7		/* STM M29W800DT (1M = 64K x 16, top)	*/
 #define FLASH_STM800DB	0x005B		/* STM M29W800DB (1M = 64K x 16, bottom)*/
 
+#define FLASH_MCHP100T	0x0060		/* MCHP internal (1M = 64K x 16) */
+#define FLASH_MCHP100B	0x0061		/* MCHP internal (1M = 64K x 16) */
+
 #define FLASH_28F400_T	0x0062		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
 #define FLASH_28F400_B	0x0063		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
 
@@ -486,7 +489,7 @@
 #define FLASH_MAN_SHARP 0x00500000
 #define FLASH_MAN_ATM	0x00600000
 #define FLASH_MAN_CFI	0x01000000
-
+#define FLASH_MAN_MCHP	0x02000000	/* Microchip Technology		*/
 
 #define FLASH_TYPEMASK	0x0000FFFF	/* extract FLASH type	information	*/
 #define FLASH_VENDMASK	0xFFFF0000	/* extract FLASH vendor information	*/
diff --git a/include/ide.h b/include/ide.h
index a4e65cf..9b0a4a9 100644
--- a/include/ide.h
+++ b/include/ide.h
@@ -34,10 +34,18 @@
 
 void ide_init(void);
 struct blk_desc;
+struct udevice;
+#ifdef CONFIG_BLK
+ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+	       void *buffer);
+ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+		const void *buffer);
+#else
 ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 	       void *buffer);
 ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 		const void *buffer);
+#endif
 
 #ifdef CONFIG_IDE_PREINIT
 int ide_preinit(void);
diff --git a/include/image.h b/include/image.h
index f9ee564..a8f6bd1 100644
--- a/include/image.h
+++ b/include/image.h
@@ -246,8 +246,10 @@
 #define IH_TYPE_RKSD		24	/* Rockchip SD card		*/
 #define IH_TYPE_RKSPI		25	/* Rockchip SPI image		*/
 #define IH_TYPE_ZYNQIMAGE	26	/* Xilinx Zynq Boot Image */
+#define IH_TYPE_ZYNQMPIMAGE	27	/* Xilinx ZynqMP Boot Image */
+#define IH_TYPE_FPGA		28	/* FPGA Image */
 
-#define IH_TYPE_COUNT		27	/* Number of image types */
+#define IH_TYPE_COUNT		29	/* Number of image types */
 
 /*
  * Compression Types
@@ -494,6 +496,8 @@
 int genimg_has_config(bootm_headers_t *images);
 ulong genimg_get_image(ulong img_addr);
 
+int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
+		uint8_t arch, const ulong *ld_start, ulong * const ld_len);
 int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
 		uint8_t arch, ulong *rd_start, ulong *rd_end);
 
@@ -809,6 +813,7 @@
 #define FIT_LOADABLE_PROP	"loadables"
 #define FIT_DEFAULT_PROP	"default"
 #define FIT_SETUP_PROP		"setup"
+#define FIT_FPGA_PROP		"fpga"
 
 #define FIT_MAX_HASH_LEN	HASH_MAX_DIGEST_SIZE
 
diff --git a/include/iotrace.h b/include/iotrace.h
index 9bd1f16..e4ceb61 100644
--- a/include/iotrace.h
+++ b/include/iotrace.h
@@ -31,10 +31,11 @@
 #define writew(val, addr)	iotrace_writew(val, (const void *)(addr))
 
 #undef readb
-#define readb(addr)	iotrace_readb((const void *)(addr))
+#define readb(addr)	iotrace_readb((const void *)(uintptr_t)addr)
 
 #undef writeb
-#define writeb(val, addr)	iotrace_writeb(val, (const void *)(addr))
+#define writeb(val, addr) \
+	iotrace_writeb(val, (const void *)(uintptr_t)addr)
 
 #endif
 
diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h
index 7ec5550..8f8ac6a 100644
--- a/include/linux/usb/otg.h
+++ b/include/linux/usb/otg.h
@@ -17,4 +17,13 @@
 	USB_DR_MODE_OTG,
 };
 
+/**
+ * usb_get_dr_mode() - Get dual role mode for given device
+ * @node: Node offset to the given device
+ *
+ * The function gets phy interface string from property 'dr_mode',
+ * and returns the correspondig enum usb_dr_mode
+ */
+enum usb_dr_mode usb_get_dr_mode(int node);
+
 #endif /* __LINUX_USB_OTG_H */
diff --git a/include/mmc.h b/include/mmc.h
index cdb56e7..a5c6573 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -344,7 +344,9 @@
 
 /* TODO struct mmc should be in mmc_private but it's hard to fix right now */
 struct mmc {
+#ifndef CONFIG_BLK
 	struct list_head link;
+#endif
 	const struct mmc_config *cfg;	/* provided configuration */
 	uint version;
 	void *priv;
@@ -376,11 +378,16 @@
 	u64 capacity_gp[4];
 	u64 enh_user_start;
 	u64 enh_user_size;
+#ifndef CONFIG_BLK
 	struct blk_desc block_dev;
+#endif
 	char op_cond_pending;	/* 1 if we are waiting on an op_cond command */
 	char init_in_progress;	/* 1 if we have done mmc_start_init() */
 	char preinit;		/* start init as early as possible */
 	int ddr_mode;
+#ifdef CONFIG_DM_MMC
+	struct udevice *dev;	/* Device for this MMC controller */
+#endif
 };
 
 struct mmc_hwpart_conf {
@@ -406,7 +413,29 @@
 
 int mmc_register(struct mmc *mmc);
 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
+
+/**
+ * mmc_bind() - Set up a new MMC device ready for probing
+ *
+ * A child block device is bound with the IF_TYPE_MMC interface type. This
+ * allows the device to be used with CONFIG_BLK
+ *
+ * @dev:	MMC device to set up
+ * @mmc:	MMC struct
+ * @cfg:	MMC configuration
+ * @return 0 if OK, -ve on error
+ */
+int mmc_bind(struct udevice *dev, struct mmc *mmc,
+	     const struct mmc_config *cfg);
 void mmc_destroy(struct mmc *mmc);
+
+/**
+ * mmc_unbind() - Unbind a MMC device's child block device
+ *
+ * @dev:	MMC device
+ * @return 0 if OK, -ve on error
+ */
+int mmc_unbind(struct udevice *dev);
 int mmc_initialize(bd_t *bis);
 int mmc_init(struct mmc *mmc);
 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
@@ -415,7 +444,6 @@
 int mmc_set_dev(int dev_num);
 void print_mmc_devices(char separator);
 int get_mmc_num(void);
-int mmc_switch_part(int dev_num, unsigned int part_num);
 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
 		      enum mmc_hwpart_conf_mode mode);
 int mmc_getcd(struct mmc *mmc);
@@ -498,4 +526,12 @@
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
 #endif
 
+/**
+ * mmc_get_blk_desc() - Get the block descriptor for an MMC device
+ *
+ * @mmc:	MMC device
+ * @return block device if found, else NULL
+ */
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
+
 #endif /* _MMC_H_ */
diff --git a/include/netdev.h b/include/netdev.h
index 244f23f..7a211bc 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -134,64 +134,6 @@
 	return num;
 }
 
-/*
- * Boards with mv88e61xx switch can use this by defining
- * CONFIG_MV88E61XX_SWITCH in respective board configheader file
- * the stuct and enums here are used to specify switch configuration params
- */
-#if defined(CONFIG_MV88E61XX_SWITCH)
-
-/* constants for any 88E61xx switch */
-#define MV88E61XX_MAX_PORTS_NUM	6
-
-enum mv88e61xx_cfg_mdip {
-	MV88E61XX_MDIP_NOCHANGE,
-	MV88E61XX_MDIP_REVERSE
-};
-
-enum mv88e61xx_cfg_ledinit {
-	MV88E61XX_LED_INIT_DIS,
-	MV88E61XX_LED_INIT_EN
-};
-
-enum mv88e61xx_cfg_rgmiid {
-	MV88E61XX_RGMII_DELAY_DIS,
-	MV88E61XX_RGMII_DELAY_EN
-};
-
-enum mv88e61xx_cfg_prtstt {
-	MV88E61XX_PORTSTT_DISABLED,
-	MV88E61XX_PORTSTT_BLOCKING,
-	MV88E61XX_PORTSTT_LEARNING,
-	MV88E61XX_PORTSTT_FORWARDING
-};
-
-struct mv88e61xx_config {
-	char *name;
-	u8 vlancfg[MV88E61XX_MAX_PORTS_NUM];
-	enum mv88e61xx_cfg_rgmiid rgmii_delay;
-	enum mv88e61xx_cfg_prtstt portstate;
-	enum mv88e61xx_cfg_ledinit led_init;
-	enum mv88e61xx_cfg_mdip mdip;
-	u32 ports_enabled;
-	u8 cpuport;
-};
-
-/*
- * Common mappings for Internal VLANs
- * These mappings consider that all ports are useable; the driver
- * will mask inexistent/unused ports.
- */
-
-/* Switch mode : routes any port to any port */
-#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F }
-
-/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */
-#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F }
-
-int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
-#endif /* CONFIG_MV88E61XX_SWITCH */
-
 struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id);
 #ifdef CONFIG_PHYLIB
 struct phy_device;
diff --git a/include/part.h b/include/part.h
index e3811c6..226b5be 100644
--- a/include/part.h
+++ b/include/part.h
@@ -12,7 +12,6 @@
 
 struct block_drvr {
 	char *name;
-	struct blk_desc* (*get_dev)(int dev);
 	int (*select_hwpart)(int dev_num, int hwpart);
 };
 
@@ -73,32 +72,8 @@
  *	   error occurred.
  */
 struct blk_desc *blk_get_dev(const char *ifname, int dev);
-struct blk_desc *ide_get_dev(int dev);
-struct blk_desc *sata_get_dev(int dev);
-struct blk_desc *scsi_get_dev(int dev);
-struct blk_desc *usb_stor_get_dev(int dev);
-struct blk_desc *mmc_get_dev(int dev);
 
-/**
- * mmc_select_hwpart() - Select the MMC hardware partiion on an MMC device
- *
- * MMC devices can support partitioning at the hardware level. This is quite
- * separate from the normal idea of software-based partitions. MMC hardware
- * partitions must be explicitly selected. Once selected only the region of
- * the device covered by that partition is accessible.
- *
- * The MMC standard provides for two boot partitions (numbered 1 and 2),
- * rpmb (3), and up to 4 addition general-purpose partitions (4-7).
- *
- * @dev_num:	Block device number (struct blk_desc->dev value)
- * @hwpart:	Hardware partition number to select. 0 means the raw device,
- *		1 is the first partition, 2 is the second, etc.
- * @return 0 if OK, other value for an error
- */
-int mmc_select_hwpart(int dev_num, int hwpart);
-struct blk_desc *systemace_get_dev(int dev);
 struct blk_desc *mg_disk_get_dev(int dev);
-struct blk_desc *host_get_dev(int dev);
 int host_get_dev_err(int dev, struct blk_desc **blk_devp);
 
 /* disk/part.c */
@@ -175,15 +150,7 @@
 #else
 static inline struct blk_desc *blk_get_dev(const char *ifname, int dev)
 { return NULL; }
-static inline struct blk_desc *ide_get_dev(int dev) { return NULL; }
-static inline struct blk_desc *sata_get_dev(int dev) { return NULL; }
-static inline struct blk_desc *scsi_get_dev(int dev) { return NULL; }
-static inline struct blk_desc *usb_stor_get_dev(int dev) { return NULL; }
-static inline struct blk_desc *mmc_get_dev(int dev) { return NULL; }
-static inline int mmc_select_hwpart(int dev_num, int hwpart) { return -1; }
-static inline struct blk_desc *systemace_get_dev(int dev) { return NULL; }
 static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; }
-static inline struct blk_desc *host_get_dev(int dev) { return NULL; }
 
 static inline int part_get_info(struct blk_desc *dev_desc, int part,
 				disk_partition_t *info) { return -1; }
diff --git a/include/phy.h b/include/phy.h
index 21459a8..268d9a1 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -249,6 +249,7 @@
 int gen10g_shutdown(struct phy_device *phydev);
 int gen10g_discover_mmds(struct phy_device *phydev);
 
+int phy_mv88e61xx_init(void);
 int phy_aquantia_init(void);
 int phy_atheros_init(void);
 int phy_broadcom_init(void);
@@ -277,6 +278,28 @@
  */
 int phy_get_interface_by_name(const char *str);
 
+/**
+ * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
+ * is RGMII (all variants)
+ * @phydev: the phy_device struct
+ */
+static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
+{
+	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
+		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
+}
+
+/**
+ * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
+ * is SGMII (all variants)
+ * @phydev: the phy_device struct
+ */
+static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
+{
+	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
+		phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
+}
+
 /* PHY UIDs for various PHYs that are referenced in external code */
 #define PHY_UID_CS4340  0x13e51002
 #define PHY_UID_TN2020	0x00a19410
diff --git a/arch/x86/include/asm/fw_cfg.h b/include/qfw.h
similarity index 80%
rename from arch/x86/include/asm/fw_cfg.h
rename to include/qfw.h
index e9450c6..b0b3b59 100644
--- a/arch/x86/include/asm/fw_cfg.h
+++ b/include/qfw.h
@@ -7,11 +7,6 @@
 #ifndef __FW_CFG__
 #define __FW_CFG__
 
-#define FW_CONTROL_PORT	0x510
-#define FW_DATA_PORT		0x511
-#define FW_DMA_PORT_LOW	0x514
-#define FW_DMA_PORT_HIGH	0x518
-
 #include <linux/list.h>
 
 enum qemu_fwcfg_items {
@@ -87,12 +82,22 @@
 	struct list_head list;  /* list node to link to fw_list */
 };
 
+struct fw_cfg_file_iter {
+	struct list_head *entry; /* structure to iterate file list */
+};
+
 struct fw_cfg_dma_access {
 	__be32 control;
 	__be32 length;
 	__be64 address;
 };
 
+struct fw_cfg_arch_ops {
+	void (*arch_read_pio)(uint16_t selector, uint32_t size,
+			void *address);
+	void (*arch_read_dma)(struct fw_cfg_dma_access *dma);
+};
+
 struct bios_linker_entry {
 	__le32 command;
 	union {
@@ -144,8 +149,14 @@
 
 /**
  * Initialize QEMU fw_cfg interface
+ *
+ * @ops: arch specific read operations
  */
-void qemu_fwcfg_init(void);
+void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops);
+
+void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address);
+int qemu_fwcfg_read_firmware_list(void);
+struct fw_file *qemu_fwcfg_find_file(const char *name);
 
 /**
  * Get system cpu number
@@ -154,4 +165,12 @@
  */
 int qemu_fwcfg_online_cpus(void);
 
+/* helper functions to iterate firmware file list */
+struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter);
+struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter);
+bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter);
+
+bool qemu_fwcfg_present(void);
+bool qemu_fwcfg_dma_present(void);
+
 #endif
diff --git a/include/spi.h b/include/spi.h
index 4b88d39..ca96fa4 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -612,6 +612,58 @@
 			 struct udevice *bus, struct udevice *slave,
 			 struct udevice **emulp);
 
+/**
+ * Claim the bus and prepare it for communication with a given slave.
+ *
+ * This must be called before doing any transfers with a SPI slave. It
+ * will enable and initialize any SPI hardware as necessary, and make
+ * sure that the SCK line is in the correct idle state. It is not
+ * allowed to claim the same bus for several slaves without releasing
+ * the bus in between.
+ *
+ * @dev:	The SPI slave device
+ *
+ * Returns: 0 if the bus was claimed successfully, or a negative value
+ * if it wasn't.
+ */
+int dm_spi_claim_bus(struct udevice *dev);
+
+/**
+ * Release the SPI bus
+ *
+ * This must be called once for every call to dm_spi_claim_bus() after
+ * all transfers have finished. It may disable any SPI hardware as
+ * appropriate.
+ *
+ * @slave:	The SPI slave device
+ */
+void dm_spi_release_bus(struct udevice *dev);
+
+/**
+ * SPI transfer
+ *
+ * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
+ * "bitlen" bits in the SPI MISO port.  That's just the way SPI works.
+ *
+ * The source of the outgoing bits is the "dout" parameter and the
+ * destination of the input bits is the "din" parameter.  Note that "dout"
+ * and "din" can point to the same memory location, in which case the
+ * input data overwrites the output data (since both are buffered by
+ * temporary variables, this is OK).
+ *
+ * dm_spi_xfer() interface:
+ * @dev:	The SPI slave device which will be sending/receiving the data.
+ * @bitlen:	How many bits to write and read.
+ * @dout:	Pointer to a string of bits to send out.  The bits are
+ *		held in a byte array and are sent MSB first.
+ * @din:	Pointer to a string of bits that will be filled in.
+ * @flags:	A bitwise combination of SPI_XFER_* flags.
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int dm_spi_xfer(struct udevice *dev, unsigned int bitlen,
+		const void *dout, void *din, unsigned long flags);
+
 /* Access the operations for a SPI device */
 #define spi_get_ops(dev)	((struct dm_spi_ops *)(dev)->driver->ops)
 #define spi_emul_get_ops(dev)	((struct dm_spi_emul_ops *)(dev)->driver->ops)
diff --git a/include/spl.h b/include/spl.h
index de4f70a..335b76a 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -56,8 +56,9 @@
 u32 spl_boot_device(void);
 u32 spl_boot_mode(void);
 void spl_set_header_raw_uboot(void);
-void spl_parse_image_header(const struct image_header *header);
+int spl_parse_image_header(const struct image_header *header);
 void spl_board_prepare_for_linux(void);
+void spl_board_prepare_for_boot(void);
 void __noreturn jump_to_image_linux(void *arg);
 int spl_start_uboot(void);
 void spl_display_print(void);
diff --git a/include/systemace.h b/include/systemace.h
deleted file mode 100644
index 3b6ec7d..0000000
--- a/include/systemace.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __SYSTEMACE_H
-#define __SYSTEMACE_H
-/*
- * Copyright (c) 2004 Picture Elements, Inc.
- *    Stephen Williams (steve@picturel.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifdef CONFIG_SYSTEMACE
-
-# include  <part.h>
-
-struct blk_desc *systemace_get_dev(int dev);
-
-#endif	/* CONFIG_SYSTEMACE */
-#endif	/* __SYSTEMACE_H */
diff --git a/include/usb.h b/include/usb.h
index 5adad36..02a0ccd 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -228,7 +228,6 @@
 #ifdef CONFIG_USB_STORAGE
 
 #define USB_MAX_STOR_DEV 7
-struct blk_desc *usb_stor_get_dev(int index);
 int usb_stor_scan(int mode);
 int usb_stor_info(void);
 
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 28e5b7f..075fd34 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <blk.h>
 #include <efi_loader.h>
 #include <inttypes.h>
 #include <part.h>
@@ -142,7 +143,7 @@
 };
 
 static void efi_disk_add_dev(char *name,
-			     const struct block_drvr *cur_drvr,
+			     const struct blk_driver *cur_drvr,
 			     const struct blk_desc *desc,
 			     int dev_index,
 			     lbaint_t offset)
@@ -160,7 +161,7 @@
 	diskobj->parent.protocols[1].open = efi_disk_open_dp;
 	diskobj->parent.handle = diskobj;
 	diskobj->ops = block_io_disk_template;
-	diskobj->ifname = cur_drvr->name;
+	diskobj->ifname = cur_drvr->if_typename;
 	diskobj->dev_index = dev_index;
 	diskobj->offset = offset;
 
@@ -189,7 +190,7 @@
 }
 
 static int efi_disk_create_eltorito(struct blk_desc *desc,
-				    const struct block_drvr *cur_drvr,
+				    const struct blk_driver *cur_drvr,
 				    int diskid)
 {
 	int disks = 0;
@@ -202,8 +203,8 @@
 		return 0;
 
 	while (!part_get_info(desc, part, &info)) {
-		snprintf(devname, sizeof(devname), "%s%d:%d", cur_drvr->name,
-			 diskid, part);
+		snprintf(devname, sizeof(devname), "%s%d:%d",
+			 cur_drvr->if_typename, diskid, part);
 		efi_disk_add_dev(devname, cur_drvr, desc, diskid, info.start);
 		part++;
 		disks++;
@@ -222,25 +223,29 @@
  */
 int efi_disk_register(void)
 {
-	const struct block_drvr *cur_drvr;
-	int i;
+	const struct blk_driver *cur_drvr;
+	int i, if_type;
 	int disks = 0;
 
 	/* Search for all available disk devices */
-	for (cur_drvr = block_drvr; cur_drvr->name; cur_drvr++) {
-		printf("Scanning disks on %s...\n", cur_drvr->name);
+	for (if_type = 0; if_type < IF_TYPE_COUNT; if_type++) {
+		cur_drvr = blk_driver_lookup_type(if_type);
+		if (!cur_drvr)
+			continue;
+
+		printf("Scanning disks on %s...\n", cur_drvr->if_typename);
 		for (i = 0; i < 4; i++) {
 			struct blk_desc *desc;
 			char devname[32] = { 0 }; /* dp->str is u16[32] long */
 
-			desc = blk_get_dev(cur_drvr->name, i);
+			desc = blk_get_devnum_by_type(if_type, i);
 			if (!desc)
 				continue;
 			if (desc->type == DEV_TYPE_UNKNOWN)
 				continue;
 
 			snprintf(devname, sizeof(devname), "%s%d",
-				 cur_drvr->name, i);
+				 cur_drvr->if_typename, i);
 			efi_disk_add_dev(devname, cur_drvr, desc, i, 0);
 			disks++;
 
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index ad1d9b5..97a09a2 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -323,13 +323,13 @@
 
 # ACPI
 # ---------------------------------------------------------------------------
-quiet_cmd_acpi_c_asl= ASL     $@
+quiet_cmd_acpi_c_asl= ASL     $<
 cmd_acpi_c_asl=         \
-	$(CPP) -x assembler-with-cpp -P -o $<.tmp $<; \
-	iasl -p $< -tc -va $<.tmp; \
+	$(CPP) -x assembler-with-cpp -P $(UBOOTINCLUDE) -o $<.tmp $<; \
+	iasl -p $< -tc $<.tmp $(if $(KBUILD_VERBOSE:1=), >/dev/null); \
 	mv $(patsubst %.asl,%.hex,$<) $@
 
-$(obj)/%.c:    $(src)/%.asl
+$(obj)/dsdt.c:    $(src)/dsdt.asl
 	$(call cmd,acpi_c_asl)
 
 # Bzip2
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index ec8d8f1..6d2017d 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -129,7 +129,12 @@
 boot.bin: $(obj)/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)
 else
+ifdef CONFIG_ARCH_ZYNQ
 MKIMAGEFLAGS_boot.bin = -T zynqimage
+endif
+ifdef CONFIG_ARCH_ZYNQMP
+MKIMAGEFLAGS_boot.bin = -T zynqmpimage
+endif
 
 spl/boot.bin: $(obj)/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)
@@ -157,6 +162,8 @@
 ALL-y	+= $(obj)/boot.bin
 endif
 
+ALL-(CONFIG_ARCH_ZYNQMP)	+= $(obj)/boot.bin
+
 all:	$(ALL-y)
 
 quiet_cmd_cat = CAT     $@
diff --git a/scripts/basic/fixdep.c b/scripts/basic/fixdep.c
index e8e8c77..9bd0de2 100644
--- a/scripts/basic/fixdep.c
+++ b/scripts/basic/fixdep.c
@@ -296,7 +296,11 @@
 		perror(filename);
 		exit(2);
 	}
-	fstat(fd, &st);
+	if (fstat(fd, &st) < 0) {
+		fprintf(stderr, "fixdep: error fstat'ing config file: ");
+		perror(filename);
+		exit(2);
+	}
 	if (st.st_size == 0) {
 		close(fd);
 		return;
diff --git a/test/dm/blk.c b/test/dm/blk.c
index f4ea32e..012bf4c 100644
--- a/test/dm/blk.c
+++ b/test/dm/blk.c
@@ -83,12 +83,12 @@
 	ut_asserteq_ptr(usb_dev, dev_get_parent(dev));
 
 	/* Check we have one block device for each mass storage device */
-	ut_asserteq(3, count_blk_devices());
+	ut_asserteq(4, count_blk_devices());
 
 	/* Now go around again, making sure the old devices were unbound */
 	ut_assertok(usb_stop());
 	ut_assertok(usb_init());
-	ut_asserteq(3, count_blk_devices());
+	ut_asserteq(4, count_blk_devices());
 	ut_assertok(usb_stop());
 
 	return 0;
diff --git a/test/dm/mmc.c b/test/dm/mmc.c
index 0461423..5bca4b7 100644
--- a/test/dm/mmc.c
+++ b/test/dm/mmc.c
@@ -25,3 +25,22 @@
 	return 0;
 }
 DM_TEST(dm_test_mmc_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_mmc_blk(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+	struct blk_desc *dev_desc;
+	char cmp[1024];
+
+	ut_assertok(uclass_get_device(UCLASS_MMC, 0, &dev));
+	ut_assertok(blk_get_device_by_str("mmc", "0", &dev_desc));
+
+	/* Read a few blocks and look for the string we expect */
+	ut_asserteq(512, dev_desc->blksz);
+	memset(cmp, '\0', sizeof(cmp));
+	ut_asserteq(2, blk_dread(dev_desc, 0, 2, cmp));
+	ut_assertok(strcmp(cmp, "this is a test"));
+
+	return 0;
+}
+DM_TEST(dm_test_mmc_blk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/tools/Makefile b/tools/Makefile
index da50e1b..63355aa 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -98,6 +98,7 @@
 			common/hash.o \
 			ublimage.o \
 			zynqimage.o \
+			zynqmpimage.o \
 			$(LIBFDT_OBJS) \
 			$(RSA_OBJS-y)
 
diff --git a/tools/buildman/README b/tools/buildman/README
index 4705d26..26755c5 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -898,6 +898,48 @@
 will build commits in us-buildman that are not in upstream/master.
 
 
+Building Faster
+===============
+
+By default, buildman executes 'make mrproper' prior to building the first
+commit for each board. This causes everything to be built from scratch. If you
+trust the build system's incremental build capabilities, you can pass the -I
+flag to skip the 'make mproper' invocation, which will reduce the amount of
+work 'make' does, and hence speed up the build. This flag will speed up any
+buildman invocation, since it reduces the amount of work done on any build.
+
+One possible application of buildman is as part of a continual edit, build,
+edit, build, ... cycle; repeatedly applying buildman to the same change or
+series of changes while making small incremental modifications to the source
+each time. This provides quick feedback regarding the correctness of recent
+modifications. In this scenario, buildman's default choice of build directory
+causes more build work to be performed than strictly necessary.
+
+By default, each buildman thread uses a single directory for all builds. When a
+thread builds multiple boards, the configuration built in this directory will
+cycle through various different configurations, one per board built by the
+thread. Variations in the configuration will force a rebuild of affected source
+files when a thread switches between boards. Ideally, such buildman-induced
+rebuilds would not happen, thus allowing the build to operate as efficiently as
+the build system and source changes allow. buildman's -P flag may be used to
+enable this; -P causes each board to be built in a separate (board-specific)
+directory, thus avoiding any buildman-induced configuration changes in any
+build directory.
+
+U-Boot's build system embeds information such as a build timestamp into the
+final binary. This information varies each time U-Boot is built. This causes
+various files to be rebuilt even if no source changes are made, which in turn
+requires that the final U-Boot binary be re-linked. This unnecessary work can
+be avoided by turning off the timestamp feature. This can be achieved by
+setting the SOURCE_DATE_EPOCH environment variable to 0.
+
+Combining all of these options together yields the command-line shown below.
+This will provide the quickest possible feedback regarding the current content
+of the source tree, thus allowing rapid tested evolution of the code.
+
+    SOURCE_DATE_EPOCH=0 ./tools/buildman/buildman -I -P tegra
+
+
 Other options
 =============
 
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index 141bf64..8ec3551 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -205,7 +205,8 @@
 
     def __init__(self, toolchains, base_dir, git_dir, num_threads, num_jobs,
                  gnu_make='make', checkout=True, show_unknown=True, step=1,
-                 no_subdirs=False, full_path=False, verbose_build=False):
+                 no_subdirs=False, full_path=False, verbose_build=False,
+                 incremental=False, per_board_out_dir=False):
         """Create a new Builder object
 
         Args:
@@ -224,6 +225,10 @@
             full_path: Return the full path in CROSS_COMPILE and don't set
                 PATH
             verbose_build: Run build with V=1 and don't use 'make -s'
+            incremental: Always perform incremental builds; don't run make
+                mrproper when configuring
+            per_board_out_dir: Build in a separate persistent directory per
+                board rather than a thread-specific directory
         """
         self.toolchains = toolchains
         self.base_dir = base_dir
@@ -263,7 +268,8 @@
         self.queue = Queue.Queue()
         self.out_queue = Queue.Queue()
         for i in range(self.num_threads):
-            t = builderthread.BuilderThread(self, i)
+            t = builderthread.BuilderThread(self, i, incremental,
+                    per_board_out_dir)
             t.setDaemon(True)
             t.start()
             self.threads.append(t)
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index cf25bb8..c512d3b 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -80,11 +80,13 @@
         thread_num: Our thread number (0-n-1), used to decide on a
                 temporary directory
     """
-    def __init__(self, builder, thread_num):
+    def __init__(self, builder, thread_num, incremental, per_board_out_dir):
         """Set up a new builder thread"""
         threading.Thread.__init__(self)
         self.builder = builder
         self.thread_num = thread_num
+        self.incremental = incremental
+        self.per_board_out_dir = per_board_out_dir
 
     def Make(self, commit, brd, stage, cwd, *args, **kwargs):
         """Run 'make' on a particular commit and board.
@@ -136,7 +138,11 @@
         if self.builder.in_tree:
             out_dir = work_dir
         else:
-            out_dir = os.path.join(work_dir, 'build')
+            if self.per_board_out_dir:
+                out_rel_dir = os.path.join('..', brd.target)
+            else:
+                out_rel_dir = 'build'
+            out_dir = os.path.join(work_dir, out_rel_dir)
 
         # Check if the job was already completed last time
         done_file = self.builder.GetDoneFile(commit_upto, brd.target)
@@ -197,12 +203,12 @@
                         #
                         # Symlinks can confuse U-Boot's Makefile since
                         # we may use '..' in our path, so remove them.
-                        work_dir = os.path.realpath(work_dir)
-                        args.append('O=%s/build' % work_dir)
+                        out_dir = os.path.realpath(out_dir)
+                        args.append('O=%s' % out_dir)
                         cwd = None
                         src_dir = os.getcwd()
                     else:
-                        args.append('O=build')
+                        args.append('O=%s' % out_rel_dir)
                 if self.builder.verbose_build:
                     args.append('V=1')
                 else:
@@ -215,9 +221,11 @@
 
                 # If we need to reconfigure, do that now
                 if do_config:
-                    result = self.Make(commit, brd, 'mrproper', cwd,
-                            'mrproper', *args, env=env)
-                    config_out = result.combined
+                    config_out = ''
+                    if not self.incremental:
+                        result = self.Make(commit, brd, 'mrproper', cwd,
+                                'mrproper', *args, env=env)
+                        config_out += result.combined
                     result = self.Make(commit, brd, 'config', cwd,
                             *(args + config_args), env=env)
                     config_out += result.combined
diff --git a/tools/buildman/cmdline.py b/tools/buildman/cmdline.py
index 8341ab1..3e3bd63 100644
--- a/tools/buildman/cmdline.py
+++ b/tools/buildman/cmdline.py
@@ -49,6 +49,8 @@
     parser.add_option('-i', '--in-tree', dest='in_tree',
           action='store_true', default=False,
           help='Build in the source tree instead of a separate directory')
+    parser.add_option('-I', '--incremental', action='store_true',
+          default=False, help='Do not run make mrproper (when reconfiguring)')
     parser.add_option('-j', '--jobs', dest='jobs', type='int',
           default=None, help='Number of jobs to run at once (passed to make)')
     parser.add_option('-k', '--keep-outputs', action='store_true',
@@ -70,6 +72,8 @@
           default=False, help='Do a rough build, with limited warning resolution')
     parser.add_option('-p', '--full-path', action='store_true',
           default=False, help="Use full toolchain path in CROSS_COMPILE")
+    parser.add_option('-P', '--per-board-out-dir', action='store_true',
+          default=False, help="Use an O= (output) directory per board rather than per thread")
     parser.add_option('-s', '--summary', action='store_true',
           default=False, help='Show a build summary')
     parser.add_option('-S', '--show-sizes', action='store_true',
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index c2c54bf..aeb128a 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -250,7 +250,9 @@
             options.threads, options.jobs, gnu_make=gnu_make, checkout=True,
             show_unknown=options.show_unknown, step=options.step,
             no_subdirs=options.no_subdirs, full_path=options.full_path,
-            verbose_build=options.verbose_build)
+            verbose_build=options.verbose_build,
+            incremental=options.incremental,
+            per_board_out_dir=options.per_board_out_dir,)
     builder.force_config_on_failure = not options.quick
     if make_func:
         builder.do_make = make_func
diff --git a/tools/imagetool.c b/tools/imagetool.c
index 916ab96..08d191d 100644
--- a/tools/imagetool.c
+++ b/tools/imagetool.c
@@ -51,7 +51,8 @@
 				 * successful
 				 */
 				if ((*curr)->print_header) {
-					(*curr)->print_header(ptr);
+					if (!params->quiet)
+						(*curr)->print_header(ptr);
 				} else {
 					fprintf(stderr,
 						"%s: print_header undefined for %s\n",
diff --git a/tools/imagetool.h b/tools/imagetool.h
index 24f8f4b..a3ed0f4 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -73,6 +73,7 @@
 	struct content_info *content_head;	/* List of files to include */
 	struct content_info *content_tail;
 	bool external_data;	/* Store data outside the FIT */
+	bool quiet;		/* Don't output text in normal operation */
 };
 
 /*
diff --git a/tools/imximage.c b/tools/imximage.c
index 7c21922..092d550 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -209,7 +209,7 @@
 		d = d2;
 		d->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
 		d->write_dcd_command.length = cpu_to_be16(4);
-		d->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
+		d->write_dcd_command.param = DCD_CHECK_BITS_CLR_PARAM;
 		break;
 	default:
 		break;
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 93d1c16..aefe22f 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -136,7 +136,7 @@
 	int opt;
 
 	while ((opt = getopt(argc, argv,
-			     "a:A:b:cC:d:D:e:Ef:Fk:K:ln:O:rR:sT:vVx")) != -1) {
+			     "a:A:b:cC:d:D:e:Ef:Fk:K:ln:O:rR:qsT:vVx")) != -1) {
 		switch (opt) {
 		case 'a':
 			params.addr = strtoull(optarg, &ptr, 16);
@@ -216,6 +216,9 @@
 			if (params.os < 0)
 				usage("Invalid operating system");
 			break;
+		case 'q':
+			params.quiet = 1;
+			break;
 		case 'r':
 			params.require_keys = 1;
 			break;
diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c
new file mode 100644
index 0000000..3f28eb4
--- /dev/null
+++ b/tools/zynqmpimage.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (C) 2016 Michal Simek <michals@xilinx.com>
+ * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * The following Boot Header format/structures and values are defined in the
+ * following documents:
+ *   * ug1085 ZynqMP TRM (Chapter 9, Table 9-3)
+ *
+ * Expected Header Size = 0x9C0
+ * Forced as 'little' endian, 32-bit words
+ *
+ *  0x  0 - Interrupt table (8 words)
+ *  ...     (Default value = 0xeafffffe)
+ *  0x 1f
+ *  0x 20 - Width detection
+ *         * DEFAULT_WIDTHDETECTION    0xaa995566
+ *  0x 24 - Image identifier
+ *         * DEFAULT_IMAGEIDENTIFIER   0x584c4e58
+ *  0x 28 - Encryption
+ *         * 0x00000000 - None
+ *         * 0xa5c3c5a3 - eFuse
+ *         * 0xa5c3c5a7 - obfuscated key in eFUSE
+ *         * 0x3a5c3c5a - bbRam
+ *         * 0xa35c7ca5 - obfuscated key in boot header
+ *  0x 2C - Image load
+ *  0x 30 - Image offset
+ *  0x 34 - PFW image length
+ *  0x 38 - Total PFW image length
+ *  0x 3C - Image length
+ *  0x 40 - Total image length
+ *  0x 44 - Image attributes
+ *  0x 48 - Header checksum
+ *  0x 4c - Obfuscated key
+ *  ...
+ *  0x 68
+ *  0x 6c - Reserved
+ *  0x 70 - User defined
+ *  ...
+ *  0x 9c
+ *  0x a0 - Secure header initialization vector
+ *  ...
+ *  0x a8
+ *  0x ac - Obfuscated key initialization vector
+ *  ...
+ *  0x b4
+ *  0x b8 - Register Initialization, 511 Address and Data word pairs
+ *         * List is terminated with an address of 0xffffffff or
+ *  ...    * at the max number of entries
+ *  0x8b4
+ *  0x8b8 - Reserved
+ *  ...
+ *  0x9bf
+ *  0x9c0 - Data/Image starts here or above
+ */
+
+#include "imagetool.h"
+#include "mkimage.h"
+#include <image.h>
+
+#define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe))
+#define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff))
+#define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566))
+#define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58))
+
+enum {
+	ENCRYPTION_EFUSE = 0xa5c3c5a3,
+	ENCRYPTION_OEFUSE = 0xa5c3c5a7,
+	ENCRYPTION_BBRAM = 0x3a5c3c5a,
+	ENCRYPTION_OBBRAM = 0xa35c7ca5,
+	ENCRYPTION_NONE = 0x0,
+};
+
+struct zynqmp_reginit {
+	uint32_t address;
+	uint32_t data;
+};
+
+#define HEADER_INTERRUPT_VECTORS	8
+#define HEADER_REGINITS			256
+
+struct zynqmp_header {
+	uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */
+	uint32_t width_detection; /* 0x20 */
+	uint32_t image_identifier; /* 0x24 */
+	uint32_t encryption; /* 0x28 */
+	uint32_t image_load; /* 0x2c */
+	uint32_t image_offset; /* 0x30 */
+	uint32_t pfw_image_length; /* 0x34 */
+	uint32_t total_pfw_image_length; /* 0x38 */
+	uint32_t image_size; /* 0x3c */
+	uint32_t image_stored_size; /* 0x40 */
+	uint32_t image_attributes; /* 0x44 */
+	uint32_t checksum; /* 0x48 */
+	uint32_t __reserved1[27]; /* 0x4c */
+	struct zynqmp_reginit register_init[HEADER_REGINITS]; /* 0xb8 */
+	uint32_t __reserved4[66]; /* 0x9c0 */
+};
+
+static struct zynqmp_header zynqmpimage_header;
+
+static uint32_t zynqmpimage_checksum(struct zynqmp_header *ptr)
+{
+	uint32_t checksum = 0;
+
+	if (ptr == NULL)
+		return 0;
+
+	checksum += le32_to_cpu(ptr->width_detection);
+	checksum += le32_to_cpu(ptr->image_identifier);
+	checksum += le32_to_cpu(ptr->encryption);
+	checksum += le32_to_cpu(ptr->image_load);
+	checksum += le32_to_cpu(ptr->image_offset);
+	checksum += le32_to_cpu(ptr->pfw_image_length);
+	checksum += le32_to_cpu(ptr->total_pfw_image_length);
+	checksum += le32_to_cpu(ptr->image_size);
+	checksum += le32_to_cpu(ptr->image_stored_size);
+	checksum += le32_to_cpu(ptr->image_attributes);
+	checksum = ~checksum;
+
+	return cpu_to_le32(checksum);
+}
+
+static void zynqmpimage_default_header(struct zynqmp_header *ptr)
+{
+	int i;
+
+	if (ptr == NULL)
+		return;
+
+	ptr->width_detection = HEADER_WIDTHDETECTION;
+	ptr->image_attributes = 0x800;
+	ptr->image_identifier = HEADER_IMAGEIDENTIFIER;
+	ptr->encryption = cpu_to_le32(ENCRYPTION_NONE);
+
+	/* Setup not-supported/constant/reserved fields */
+	for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++)
+		ptr->interrupt_vectors[i] = HEADER_INTERRUPT_DEFAULT;
+
+	for (i = 0; i < HEADER_REGINITS; i++) {
+		ptr->register_init[i].address = HEADER_REGINIT_NULL;
+		ptr->register_init[i].data = 0;
+	}
+
+	/*
+	 * Certain reserved fields are required to be set to 0, ensure they are
+	 * set as such.
+	 */
+	ptr->pfw_image_length = 0x0;
+	ptr->total_pfw_image_length = 0x0;
+}
+
+/* mkimage glue functions */
+static int zynqmpimage_verify_header(unsigned char *ptr, int image_size,
+		struct image_tool_params *params)
+{
+	struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
+
+	if (image_size < sizeof(struct zynqmp_header))
+		return -1;
+
+	if (zynqhdr->width_detection != HEADER_WIDTHDETECTION)
+		return -1;
+	if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER)
+		return -1;
+
+	if (zynqmpimage_checksum(zynqhdr) != zynqhdr->checksum)
+		return -1;
+
+	return 0;
+}
+
+static void zynqmpimage_print_header(const void *ptr)
+{
+	struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
+	int i;
+
+	printf("Image Type   : Xilinx Zynq Boot Image support\n");
+	printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset));
+	printf("Image Size   : %lu bytes (%lu bytes packed)\n",
+	       (unsigned long)le32_to_cpu(zynqhdr->image_size),
+	       (unsigned long)le32_to_cpu(zynqhdr->image_stored_size));
+	printf("Image Load   : 0x%08x\n", le32_to_cpu(zynqhdr->image_load));
+	printf("Checksum     : 0x%08x\n", le32_to_cpu(zynqhdr->checksum));
+
+	for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) {
+		if (zynqhdr->interrupt_vectors[i] == HEADER_INTERRUPT_DEFAULT)
+			continue;
+
+		printf("Modified Interrupt Vector Address [%d]: 0x%08x\n", i,
+		       le32_to_cpu(zynqhdr->interrupt_vectors[i]));
+	}
+
+	for (i = 0; i < HEADER_REGINITS; i++) {
+		if (zynqhdr->register_init[i].address == HEADER_REGINIT_NULL)
+			break;
+
+		if (i == 0)
+			printf("Custom Register Initialization:\n");
+
+		printf("    @ 0x%08x -> 0x%08x\n",
+		       le32_to_cpu(zynqhdr->register_init[i].address),
+		       le32_to_cpu(zynqhdr->register_init[i].data));
+	}
+}
+
+static int zynqmpimage_check_params(struct image_tool_params *params)
+{
+	if (!params)
+		return 0;
+
+	if (params->addr != 0x0) {
+		fprintf(stderr, "Error: Load Address cannot be specified.\n");
+		return -1;
+	}
+
+	/*
+	 * If the entry point is specified ensure it is 64 byte aligned.
+	 */
+	if (params->eflag && (params->ep % 64 != 0)) {
+		fprintf(stderr,
+			"Error: Entry Point must be aligned to a 64-byte boundary.\n");
+		return -1;
+	}
+
+	return !(params->lflag || params->dflag);
+}
+
+static int zynqmpimage_check_image_types(uint8_t type)
+{
+	if (type == IH_TYPE_ZYNQMPIMAGE)
+		return EXIT_SUCCESS;
+	return EXIT_FAILURE;
+}
+
+static void zynqmpimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+		struct image_tool_params *params)
+{
+	struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
+	zynqmpimage_default_header(zynqhdr);
+
+	/* place image directly after header */
+	zynqhdr->image_offset =
+		cpu_to_le32((uint32_t)sizeof(struct zynqmp_header));
+	zynqhdr->image_size = cpu_to_le32(params->file_size -
+					  sizeof(struct zynqmp_header));
+	zynqhdr->image_stored_size = zynqhdr->image_size;
+	zynqhdr->image_load = 0xfffc0000;
+	if (params->eflag)
+		zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep);
+
+	zynqhdr->checksum = zynqmpimage_checksum(zynqhdr);
+}
+
+U_BOOT_IMAGE_TYPE(
+	zynqmpimage,
+	"Xilinx ZynqMP Boot Image support",
+	sizeof(struct zynqmp_header),
+	(void *)&zynqmpimage_header,
+	zynqmpimage_check_params,
+	zynqmpimage_verify_header,
+	zynqmpimage_print_header,
+	zynqmpimage_set_header,
+	NULL,
+	zynqmpimage_check_image_types,
+	NULL,
+	NULL
+);